[linux-2.6-block.git] / arch / mips / include / asm / pgtable-32.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
 */
#ifndef _ASM_PGTABLE_32_H
#define _ASM_PGTABLE_32_H

#include <asm/addrspace.h>
#include <asm/page.h>

#include <linux/linkage.h>
#include <asm/cachectl.h>
#include <asm/fixmap.h>

#include <asm-generic/pgtable-nopmd.h>

/*
 * - add_wired_entry() add a fixed TLB entry, and move wired register
 */
extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
			       unsigned long entryhi, unsigned long pagemask);

/*
 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
 *	starting at the top and working down. This is for populating the
 *	TLB before trap_init() puts the TLB miss handler in place. It
 *	should be used only for entries matching the actual page tables,
 *	to prevent inconsistencies.
 */
extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
			       unsigned long entryhi, unsigned long pagemask);


/* Basically we have the same two-level (which is the logical three level
 * Linux page table layout folded) page tables as the i386.  Some day
 * when we have proper page coloring support we can have a 1% quicker
 * tlb refill handling mechanism, but for now it is a bit slower but
 * works even with the cache aliasing problem the R4k and above have.
 */

/* PGDIR_SHIFT determines what a third-level page table entry can map */
#define PGDIR_SHIFT	(2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * Entries per page directory level: we use two-level, so
 * we don't really have any PUD/PMD directory physically.
 */
#define __PGD_ORDER	(32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
#define PGD_ORDER	(__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
#define PUD_ORDER	aieeee_attempt_to_allocate_pud
#define PMD_ORDER	1
#define PTE_ORDER	0

#define PTRS_PER_PGD	(USER_PTRS_PER_PGD * 2)
#define PTRS_PER_PTE	((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))

#define USER_PTRS_PER_PGD	(0x80000000UL/PGDIR_SIZE)
#define FIRST_USER_ADDRESS	0

#define VMALLOC_START     MAP_BASE

#define PKMAP_BASE		(0xfe000000UL)

#ifdef CONFIG_HIGHMEM
# define VMALLOC_END	(PKMAP_BASE-2*PAGE_SIZE)
#else
# define VMALLOC_END	(FIXADDR_START-2*PAGE_SIZE)
#endif

#ifdef CONFIG_64BIT_PHYS_ADDR
#define pte_ERROR(e) \
	printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
#else
#define pte_ERROR(e) \
	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
#endif
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))

extern void load_pgd(unsigned long pg_dir);

extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];

/*
 * Empty pgd/pmd entries point to the invalid_pte_table.
 */
static inline int pmd_none(pmd_t pmd)
{
	return pmd_val(pmd) == (unsigned long) invalid_pte_table;
}

#define pmd_bad(pmd)		(pmd_val(pmd) & ~PAGE_MASK)

static inline int pmd_present(pmd_t pmd)
{
	return pmd_val(pmd) != (unsigned long) invalid_pte_table;
}

static inline void pmd_clear(pmd_t *pmdp)
{
	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
}

#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
#define pte_page(x)		pfn_to_page(pte_pfn(x))
#define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))
static inline pte_t
pfn_pte(unsigned long pfn, pgprot_t prot)
{
	pte_t pte;
	pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
	pte.pte_low = pgprot_val(prot);
	return pte;
}

#else

#define pte_page(x)		pfn_to_page(pte_pfn(x))

#ifdef CONFIG_CPU_VR41XX
#define pte_pfn(x)		((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
#define pfn_pte(pfn, prot)	__pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
#else
#define pte_pfn(x)		((unsigned long)((x).pte >> PAGE_SHIFT))
#define pfn_pte(pfn, prot)	__pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
#endif
#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */

#define __pgd_offset(address)	pgd_index(address)
#define __pud_offset(address)	(((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
#define __pmd_offset(address)	(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

#define pgd_index(address)	(((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))

/* to find an entry in a page-table-directory */
#define pgd_offset(mm, addr)	((mm)->pgd + pgd_index(addr))

/* Find an entry in the third-level page table.. */
#define __pte_offset(address)						\
	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset(dir, address)					\
	((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
#define pte_offset_kernel(dir, address)					\
	((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))

#define pte_offset_map(dir, address)                                    \
	((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
#define pte_offset_map_nested(dir, address)                             \
	((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
#define pte_unmap(pte) ((void)(pte))
#define pte_unmap_nested(pte) ((void)(pte))

#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

/* Swap entries must have VALID bit cleared. */
#define __swp_type(x)		(((x).val >> 10) & 0x1f)
#define __swp_offset(x)		((x).val >> 15)
#define __swp_entry(type,offset)	\
	((swp_entry_t) { ((type) << 10) | ((offset) << 15) })

/*
 * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
 */
#define PTE_FILE_MAX_BITS	28

#define pte_to_pgoff(_pte)	((((_pte).pte >> 1 ) & 0x07) | \
				 (((_pte).pte >> 2 ) & 0x38) | \
				 (((_pte).pte >> 10) <<  6 ))

#define pgoff_to_pte(off)	((pte_t) { (((off) & 0x07) << 1 ) | \
					   (((off) & 0x38) << 2 ) | \
					   (((off) >>  6 ) << 10) | \
					   _PAGE_FILE })

#else

/* Swap entries must have VALID and GLOBAL bits cleared. */
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
#define __swp_type(x)		(((x).val >> 2) & 0x1f)
#define __swp_offset(x) 	 ((x).val >> 7)
#define __swp_entry(type,offset)	\
		((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
#else
#define __swp_type(x)		(((x).val >> 8) & 0x1f)
#define __swp_offset(x) 	 ((x).val >> 13)
#define __swp_entry(type,offset)	\
		((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })
#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */

#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
/*
 * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
 */
#define PTE_FILE_MAX_BITS	30

#define pte_to_pgoff(_pte)	((_pte).pte_high >> 2)
#define pgoff_to_pte(off) 	((pte_t) { _PAGE_FILE, (off) << 2 })

#else
/*
 * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
 */
#define PTE_FILE_MAX_BITS	28

#define pte_to_pgoff(_pte)	((((_pte).pte >> 1) & 0x7) | \
				 (((_pte).pte >> 2) & 0x8) | \
				 (((_pte).pte >> 8) <<  4))

#define pgoff_to_pte(off)	((pte_t) { (((off) & 0x7) << 1) | \
					   (((off) & 0x8) << 2) | \
					   (((off) >>  4) << 8) | \
					   _PAGE_FILE })
#endif

#endif

#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
#define __swp_entry_to_pte(x)	((pte_t) { 0, (x).val })
#else
#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)	((pte_t) { (x).val })
#endif

#endif /* _ASM_PGTABLE_32_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
	7	* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
	8	*/
	9	#ifndef _ASM_PGTABLE_32_H
	10	#define _ASM_PGTABLE_32_H
	11
1da177e4 LT	12	#include <asm/addrspace.h>
	13	#include <asm/page.h>
	14
	15	#include <linux/linkage.h>
	16	#include <asm/cachectl.h>
	17	#include <asm/fixmap.h>
	18
c6e8b587 RB	19	#include <asm-generic/pgtable-nopmd.h>
c6e8b587 RB	20
1da177e4 LT	21	/*
	22	* - add_wired_entry() add a fixed TLB entry, and move wired register
	23	*/
	24	extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
	25	unsigned long entryhi, unsigned long pagemask);
	26
	27	/*
	28	* - add_temporary_entry() add a temporary TLB entry. We use TLB entries
	29	* starting at the top and working down. This is for populating the
	30	* TLB before trap_init() puts the TLB miss handler in place. It
	31	* should be used only for entries matching the actual page tables,
	32	* to prevent inconsistencies.
	33	*/
	34	extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
	35	unsigned long entryhi, unsigned long pagemask);
	36
	37
	38	/* Basically we have the same two-level (which is the logical three level
	39	* Linux page table layout folded) page tables as the i386. Some day
	40	* when we have proper page coloring support we can have a 1% quicker
	41	* tlb refill handling mechanism, but for now it is a bit slower but
	42	* works even with the cache aliasing problem the R4k and above have.
	43	*/
	44
1da177e4	45	/* PGDIR_SHIFT determines what a third-level page table entry can map */
4c8081e4	46	#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
1da177e4 LT	47	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	48	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	49
	50	/*
	51	* Entries per page directory level: we use two-level, so
c6e8b587	52	* we don't really have any PUD/PMD directory physically.
1da177e4	53	*/
99e480d8 RB	54	#define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
99e480d8 RB	55	#define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
c6e8b587 RB	56	#define PUD_ORDER aieeee_attempt_to_allocate_pud
c6e8b587 RB	57	#define PMD_ORDER 1
1da177e4	58	#define PTE_ORDER 0
1da177e4	59
5291925a	60	#define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
1da177e4 LT	61	#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
	62
	63	#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
d455a369	64	#define FIRST_USER_ADDRESS 0
1da177e4	65
f29244a5	66	#define VMALLOC_START MAP_BASE
1da177e4	67
2ac7401d RB	68	#define PKMAP_BASE (0xfe000000UL)
2ac7401d RB	69
1da177e4 LT	70	#ifdef CONFIG_HIGHMEM
	71	# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
	72	#else
	73	# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
	74	#endif
	75
	76	#ifdef CONFIG_64BIT_PHYS_ADDR
	77	#define pte_ERROR(e) \
	78	printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
	79	#else
	80	#define pte_ERROR(e) \
	81	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
	82	#endif
1da177e4 LT	83	#define pgd_ERROR(e) \
	84	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
	85
	86	extern void load_pgd(unsigned long pg_dir);
	87
	88	extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
	89
	90	/*
	91	* Empty pgd/pmd entries point to the invalid_pte_table.
	92	*/
	93	static inline int pmd_none(pmd_t pmd)
	94	{
	95	return pmd_val(pmd) == (unsigned long) invalid_pte_table;
	96	}
	97
	98	#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
	99
	100	static inline int pmd_present(pmd_t pmd)
	101	{
	102	return pmd_val(pmd) != (unsigned long) invalid_pte_table;
	103	}
	104
	105	static inline void pmd_clear(pmd_t *pmdp)
	106	{
	107	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
	108	}
	109
962f480e	110	#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
1da177e4 LT	111	#define pte_page(x) pfn_to_page(pte_pfn(x))
	112	#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
	113	static inline pte_t
	114	pfn_pte(unsigned long pfn, pgprot_t prot)
	115	{
	116	pte_t pte;
	117	pte.pte_high = (pfn << 6) \| (pgprot_val(prot) & 0x3f);
	118	pte.pte_low = pgprot_val(prot);
	119	return pte;
	120	}
	121
	122	#else
	123
	124	#define pte_page(x) pfn_to_page(pte_pfn(x))
	125
	126	#ifdef CONFIG_CPU_VR41XX
	127	#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
	128	#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) \| pgprot_val(prot))
	129	#else
	130	#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
533330bf	131	#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) \| pgprot_val(prot))
1da177e4	132	#endif
962f480e	133	#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
1da177e4 LT	134
1da177e4 LT	135	#define __pgd_offset(address) pgd_index(address)
f29244a5	136	#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1da177e4 LT	137	#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
	138
	139	/* to find an entry in a kernel page-table-directory */
	140	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	141
f29244a5	142	#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1da177e4 LT	143
1da177e4 LT	144	/* to find an entry in a page-table-directory */
21a151d8	145	#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
1da177e4	146
1da177e4 LT	147	/* Find an entry in the third-level page table.. */
	148	#define __pte_offset(address) \
	149	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	150	#define pte_offset(dir, address) \
5b70a317 FBH	151	((pte_t ) pmd_page_vaddr((dir)) + __pte_offset(address))
	152	#define pte_offset_kernel(dir, address) \
	153	((pte_t ) pmd_page_vaddr((dir)) + __pte_offset(address))
1da177e4 LT	154
	155	#define pte_offset_map(dir, address) \
	156	((pte_t )page_address(pmd_page((dir))) + __pte_offset(address))
	157	#define pte_offset_map_nested(dir, address) \
	158	((pte_t )page_address(pmd_page((dir))) + __pte_offset(address))
	159	#define pte_unmap(pte) ((void)(pte))
	160	#define pte_unmap_nested(pte) ((void)(pte))
	161
	162	#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
	163
	164	/* Swap entries must have VALID bit cleared. */
	165	#define __swp_type(x) (((x).val >> 10) & 0x1f)
	166	#define __swp_offset(x) ((x).val >> 15)
	167	#define __swp_entry(type,offset) \
	168	((swp_entry_t) { ((type) << 10) \| ((offset) << 15) })
	169
	170	/*
7cb710c9	171	* Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
1da177e4	172	*/
7cb710c9	173	#define PTE_FILE_MAX_BITS 28
1da177e4	174
7cb710c9 SS	175	#define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) \| \
	176	(((_pte).pte >> 2 ) & 0x38) \| \
	177	(((_pte).pte >> 10) << 6 ))
1da177e4	178
7cb710c9 SS	179	#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) \| \
	180	(((off) & 0x38) << 2 ) \| \
	181	(((off) >> 6 ) << 10) \| \
	182	_PAGE_FILE })
1da177e4 LT	183
	184	#else
	185
	186	/* Swap entries must have VALID and GLOBAL bits cleared. */
6ebba0e2 SS	187	#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
	188	#define __swp_type(x) (((x).val >> 2) & 0x1f)
	189	#define __swp_offset(x) ((x).val >> 7)
	190	#define __swp_entry(type,offset) \
	191	((swp_entry_t) { ((type) << 2) \| ((offset) << 7) })
	192	#else
1da177e4	193	#define __swp_type(x) (((x).val >> 8) & 0x1f)
6ebba0e2	194	#define __swp_offset(x) ((x).val >> 13)
1da177e4	195	#define __swp_entry(type,offset) \
6ebba0e2 SS	196	((swp_entry_t) { ((type) << 8) \| ((offset) << 13) })
6ebba0e2 SS	197	#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
1da177e4	198
7cb710c9	199	#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
1da177e4	200	/*
7cb710c9	201	* Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
1da177e4	202	*/
7cb710c9	203	#define PTE_FILE_MAX_BITS 30
1da177e4	204
7cb710c9 SS	205	#define pte_to_pgoff(_pte) ((_pte).pte_high >> 2)
7cb710c9 SS	206	#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 })
1da177e4 LT	207
1da177e4 LT	208	#else
7cb710c9 SS	209	/*
	210	* Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
	211	*/
	212	#define PTE_FILE_MAX_BITS 28
	213
	214	#define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) \| \
	215	(((_pte).pte >> 2) & 0x8) \| \
	216	(((_pte).pte >> 8) << 4))
1da177e4	217
7cb710c9 SS	218	#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) \| \
	219	(((off) & 0x8) << 2) \| \
	220	(((off) >> 4) << 8) \| \
	221	_PAGE_FILE })
1da177e4 LT	222	#endif
	223
	224	#endif
	225
6ebba0e2 SS	226	#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
	227	#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
	228	#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
	229	#else
1da177e4 LT	230	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1da177e4 LT	231	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
6ebba0e2	232	#endif
1da177e4 LT	233
1da177e4 LT	234	#endif /* _ASM_PGTABLE_32_H */