[linux-2.6-block.git] / arch / mips / include / asm / pci.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#ifndef _ASM_PCI_H
#define _ASM_PCI_H

#include <linux/mm.h>

#ifdef __KERNEL__

/*
 * This file essentially defines the interface between board
 * specific PCI code and MIPS common PCI code.  Should potentially put
 * into include/asm/pci.h file.
 */

#include <linux/ioport.h>
#include <linux/of.h>

/*
 * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
 * multiple PCI channels may have multiple PCI host controllers or a
 * single controller supporting multiple channels.
 */
struct pci_controller {
	struct pci_controller *next;
	struct pci_bus *bus;
	struct device_node *of_node;

	struct pci_ops *pci_ops;
	struct resource *mem_resource;
	unsigned long mem_offset;
	struct resource *io_resource;
	unsigned long io_offset;
	unsigned long io_map_base;

	unsigned int index;
	/* For compatibility with current (as of July 2003) pciutils
	   and XFree86. Eventually will be removed. */
	unsigned int need_domain_info;

	int iommu;

	/* Optional access methods for reading/writing the bus number
	   of the PCI controller */
	int (*get_busno)(void);
	void (*set_busno)(int busno);
};

/*
 * Used by boards to register their PCI busses before the actual scanning.
 */
extern struct pci_controller * alloc_pci_controller(void);
extern void register_pci_controller(struct pci_controller *hose);

/*
 * board supplied pci irq fixup routine
 */
extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);


/* Can be used to override the logic in pci_scan_bus for skipping
   already-configured bus numbers - to be used for buggy BIOSes
   or architectures with incomplete PCI setup by the loader */

extern unsigned int pcibios_assign_all_busses(void);

extern unsigned long PCIBIOS_MIN_IO;
extern unsigned long PCIBIOS_MIN_MEM;

#define PCIBIOS_MIN_CARDBUS_IO	0x4000

extern void pcibios_set_master(struct pci_dev *dev);

static inline void pcibios_penalize_isa_irq(int irq, int active)
{
	/* We don't do dynamic PCI IRQ allocation */
}

#define HAVE_PCI_MMAP

extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
	enum pci_mmap_state mmap_state, int write_combine);

/*
 * Dynamic DMA mapping stuff.
 * MIPS has everything mapped statically.
 */

#include <linux/types.h>
#include <linux/slab.h>
#include <asm/scatterlist.h>
#include <linux/string.h>
#include <asm/io.h>
#include <asm-generic/pci-bridge.h>

struct pci_dev;

/*
 * The PCI address space does equal the physical memory address space.  The
 * networking and block device layers use this boolean for bounce buffer
 * decisions.  This is set if any hose does not have an IOMMU.
 */
extern unsigned int PCI_DMA_BUS_IS_PHYS;

#ifdef CONFIG_PCI
static inline void pci_dma_burst_advice(struct pci_dev *pdev,
					enum pci_dma_burst_strategy *strat,
					unsigned long *strategy_parameter)
{
	*strat = PCI_DMA_BURST_INFINITY;
	*strategy_parameter = ~0UL;
}
#endif

#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index

static inline int pci_proc_domain(struct pci_bus *bus)
{
	struct pci_controller *hose = bus->sysdata;
	return hose->need_domain_info;
}

#endif /* __KERNEL__ */

/* implement the pci_ DMA API in terms of the generic device dma_ one */
#include <asm-generic/pci-dma-compat.h>

/* Do platform specific device initialization at pci_enable_device() time */
extern int pcibios_plat_dev_init(struct pci_dev *dev);

/* Chances are this interrupt is wired PC-style ...  */
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
	return channel ? 15 : 14;
}

#ifdef CONFIG_CPU_CAVIUM_OCTEON
/* MSI arch hook for OCTEON */
#define arch_setup_msi_irqs arch_setup_msi_irqs
#endif

extern char * (*pcibios_plat_setup)(char *str);

/* this function parses memory ranges from a device node */
extern void pci_load_of_ranges(struct pci_controller *hose,
			       struct device_node *node);

#endif /* _ASM_PCI_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*/
	6	#ifndef _ASM_PCI_H
	7	#define _ASM_PCI_H
	8
1da177e4 LT	9	#include <linux/mm.h>
	10
	11	#ifdef __KERNEL__
	12
	13	/*
	14	* This file essentially defines the interface between board
	15	* specific PCI code and MIPS common PCI code. Should potentially put
	16	* into include/asm/pci.h file.
	17	*/
	18
	19	#include <linux/ioport.h>
a48cf37a	20	#include <linux/of.h>
1da177e4 LT	21
	22	/*
	23	* Each pci channel is a top-level PCI bus seem by CPU. A machine with
	24	* multiple PCI channels may have multiple PCI host controllers or a
	25	* single controller supporting multiple channels.
	26	*/
	27	struct pci_controller {
	28	struct pci_controller *next;
	29	struct pci_bus *bus;
a48cf37a	30	struct device_node *of_node;
1da177e4 LT	31
	32	struct pci_ops *pci_ops;
	33	struct resource *mem_resource;
	34	unsigned long mem_offset;
	35	struct resource *io_resource;
	36	unsigned long io_offset;
140c1729	37	unsigned long io_map_base;
1da177e4 LT	38
	39	unsigned int index;
	40	/* For compatibility with current (as of July 2003) pciutils
	41	and XFree86. Eventually will be removed. */
	42	unsigned int need_domain_info;
	43
	44	int iommu;
8a1417de AI	45
	46	/* Optional access methods for reading/writing the bus number
	47	of the PCI controller */
	48	int (*get_busno)(void);
	49	void (*set_busno)(int busno);
1da177e4 LT	50	};
	51
	52	/*
	53	* Used by boards to register their PCI busses before the actual scanning.
	54	*/
	55	extern struct pci_controller * alloc_pci_controller(void);
	56	extern void register_pci_controller(struct pci_controller *hose);
	57
	58	/*
	59	* board supplied pci irq fixup routine
	60	*/
19df0d11	61	extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
1da177e4 LT	62
	63
	64	/* Can be used to override the logic in pci_scan_bus for skipping
	65	already-configured bus numbers - to be used for buggy BIOSes
	66	or architectures with incomplete PCI setup by the loader */
	67
	68	extern unsigned int pcibios_assign_all_busses(void);
	69
1da177e4 LT	70	extern unsigned long PCIBIOS_MIN_IO;
	71	extern unsigned long PCIBIOS_MIN_MEM;
	72
	73	#define PCIBIOS_MIN_CARDBUS_IO 0x4000
	74
	75	extern void pcibios_set_master(struct pci_dev *dev);
	76
c9c3e457	77	static inline void pcibios_penalize_isa_irq(int irq, int active)
1da177e4 LT	78	{
	79	/* We don't do dynamic PCI IRQ allocation */
	80	}
	81
98873f53 RB	82	#define HAVE_PCI_MMAP
	83
	84	extern int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	85	enum pci_mmap_state mmap_state, int write_combine);
	86
1da177e4 LT	87	/*
	88	* Dynamic DMA mapping stuff.
	89	* MIPS has everything mapped statically.
	90	*/
	91
	92	#include <linux/types.h>
	93	#include <linux/slab.h>
	94	#include <asm/scatterlist.h>
	95	#include <linux/string.h>
	96	#include <asm/io.h>
29090606	97	#include <asm-generic/pci-bridge.h>
1da177e4 LT	98
	99	struct pci_dev;
	100
	101	/*
	102	* The PCI address space does equal the physical memory address space. The
	103	* networking and block device layers use this boolean for bounce buffer
	104	* decisions. This is set if any hose does not have an IOMMU.
	105	*/
	106	extern unsigned int PCI_DMA_BUS_IS_PHYS;
	107
bb4a61b6	108	#ifdef CONFIG_PCI
e24c2d96 DM	109	static inline void pci_dma_burst_advice(struct pci_dev *pdev,
	110	enum pci_dma_burst_strategy *strat,
	111	unsigned long *strategy_parameter)
	112	{
	113	*strat = PCI_DMA_BURST_INFINITY;
	114	*strategy_parameter = ~0UL;
	115	}
bb4a61b6	116	#endif
e24c2d96	117
1da177e4 LT	118	#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
	119
	120	static inline int pci_proc_domain(struct pci_bus *bus)
	121	{
	122	struct pci_controller *hose = bus->sysdata;
	123	return hose->need_domain_info;
	124	}
	125
1da177e4 LT	126	#endif /* __KERNEL__ */
	127
	128	/* implement the pci_ DMA API in terms of the generic device dma_ one */
	129	#include <asm-generic/pci-dma-compat.h>
	130
1da177e4 LT	131	/* Do platform specific device initialization at pci_enable_device() time */
	132	extern int pcibios_plat_dev_init(struct pci_dev *dev);
	133
5b1d221e RB	134	/* Chances are this interrupt is wired PC-style ... */
	135	static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
	136	{
	137	return channel ? 15 : 14;
	138	}
	139
52a0f00b CC	140	#ifdef CONFIG_CPU_CAVIUM_OCTEON
	141	/* MSI arch hook for OCTEON */
	142	#define arch_setup_msi_irqs arch_setup_msi_irqs
	143	#endif
	144
47a5c976 AN	145	extern char * (pcibios_plat_setup)(char str);
47a5c976 AN	146
a48cf37a	147	/* this function parses memory ranges from a device node */
28eb0e46 GKH	148	extern void pci_load_of_ranges(struct pci_controller *hose,
28eb0e46 GKH	149	struct device_node *node);
a48cf37a	150
1da177e4	151	#endif /* _ASM_PCI_H */