[linux-2.6-block.git] / arch / mips / include / asm / netlogic / haldefs.h

/*
 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
 * reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the NetLogic
 * license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef __NLM_HAL_HALDEFS_H__
#define __NLM_HAL_HALDEFS_H__

#include <linux/irqflags.h>	/* for local_irq_disable */

/*
 * This file contains platform specific memory mapped IO implementation
 * and will provide a way to read 32/64 bit memory mapped registers in
 * all ABIs
 */
static inline uint32_t
nlm_read_reg(uint64_t base, uint32_t reg)
{
	volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;

	return *addr;
}

static inline void
nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
{
	volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;

	*addr = val;
}

/*
 * For o32 compilation, we have to disable interrupts to access 64 bit
 * registers
 *
 * We need to disable interrupts because we save just the lower 32 bits of
 * registers in  interrupt handling. So if we get hit by an interrupt while
 * using the upper 32 bits of a register, we lose.
 */

static inline uint64_t
nlm_read_reg64(uint64_t base, uint32_t reg)
{
	uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
	volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
	uint64_t val;

	if (sizeof(unsigned long) == 4) {
		unsigned long flags;

		local_irq_save(flags);
		__asm__ __volatile__(
			".set	push"			"\n\t"
			".set	mips64"			"\n\t"
			"ld	%L0, %1"		"\n\t"
			"dsra32	%M0, %L0, 0"		"\n\t"
			"sll	%L0, %L0, 0"		"\n\t"
			".set	pop"			"\n"
			: "=r" (val)
			: "m" (*ptr));
		local_irq_restore(flags);
	} else
		val = *ptr;

	return val;
}

static inline void
nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
{
	uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
	volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;

	if (sizeof(unsigned long) == 4) {
		unsigned long flags;
		uint64_t tmp;

		local_irq_save(flags);
		__asm__ __volatile__(
			".set	push"			"\n\t"
			".set	mips64"			"\n\t"
			"dsll32	%L0, %L0, 0"		"\n\t"
			"dsrl32	%L0, %L0, 0"		"\n\t"
			"dsll32	%M0, %M0, 0"		"\n\t"
			"or	%L0, %L0, %M0"		"\n\t"
			"sd	%L0, %2"		"\n\t"
			".set	pop"			"\n"
			: "=r" (tmp)
			: "0" (val), "m" (*ptr));
		local_irq_restore(flags);
	} else
		*ptr = val;
}

/*
 * Routines to store 32/64 bit values to 64 bit addresses,
 * used when going thru XKPHYS to access registers
 */
static inline uint32_t
nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
{
	return nlm_read_reg(base, reg);
}

static inline void
nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
{
	nlm_write_reg(base, reg, val);
}

static inline uint64_t
nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
{
	return nlm_read_reg64(base, reg);
}

static inline void
nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
{
	nlm_write_reg64(base, reg, val);
}

/* Location where IO base is mapped */
extern uint64_t nlm_io_base;

#if defined(CONFIG_CPU_XLP)
static inline uint64_t
nlm_pcicfg_base(uint32_t devoffset)
{
	return nlm_io_base + devoffset;
}

#elif defined(CONFIG_CPU_XLR)

static inline uint64_t
nlm_mmio_base(uint32_t devoffset)
{
	return nlm_io_base + devoffset;
}
#endif

#endif
Commit	Line	Data
0c965407 J	1	/*
	2	* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
	3	* reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the NetLogic
	9	* license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or without
	12	* modification, are permitted provided that the following conditions
	13	* are met:
	14	*
	15	* 1. Redistributions of source code must retain the above copyright
	16	* notice, this list of conditions and the following disclaimer.
	17	* 2. Redistributions in binary form must reproduce the above copyright
	18	* notice, this list of conditions and the following disclaimer in
	19	* the documentation and/or other materials provided with the
	20	* distribution.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
	23	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	24	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	29	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	30	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	31	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	32	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	#ifndef __NLM_HAL_HALDEFS_H__
	36	#define __NLM_HAL_HALDEFS_H__
	37
1ad4af85 J	38	#include <linux/irqflags.h> /* for local_irq_disable */
1ad4af85 J	39
0c965407 J	40	/*
	41	* This file contains platform specific memory mapped IO implementation
	42	* and will provide a way to read 32/64 bit memory mapped registers in
	43	* all ABIs
	44	*/
0c965407 J	45	static inline uint32_t
	46	nlm_read_reg(uint64_t base, uint32_t reg)
	47	{
	48	volatile uint32_t addr = (volatile uint32_t )(long)base + reg;
	49
	50	return *addr;
	51	}
	52
	53	static inline void
	54	nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
	55	{
	56	volatile uint32_t addr = (volatile uint32_t )(long)base + reg;
	57
	58	*addr = val;
	59	}
	60
1ad4af85 J	61	/*
	62	* For o32 compilation, we have to disable interrupts to access 64 bit
	63	* registers
	64	*
	65	* We need to disable interrupts because we save just the lower 32 bits of
	66	* registers in interrupt handling. So if we get hit by an interrupt while
	67	* using the upper 32 bits of a register, we lose.
	68	*/
	69
0c965407 J	70	static inline uint64_t
	71	nlm_read_reg64(uint64_t base, uint32_t reg)
	72	{
	73	uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
	74	volatile uint64_t ptr = (volatile uint64_t )(long)addr;
1ad4af85 J	75	uint64_t val;
	76
	77	if (sizeof(unsigned long) == 4) {
	78	unsigned long flags;
0c965407	79
1ad4af85 J	80	local_irq_save(flags);
	81	__asm__ __volatile__(
	82	".set push" "\n\t"
	83	".set mips64" "\n\t"
	84	"ld %L0, %1" "\n\t"
	85	"dsra32 %M0, %L0, 0" "\n\t"
	86	"sll %L0, %L0, 0" "\n\t"
	87	".set pop" "\n"
	88	: "=r" (val)
	89	: "m" (*ptr));
	90	local_irq_restore(flags);
	91	} else
	92	val = *ptr;
	93
	94	return val;
0c965407 J	95	}
	96
	97	static inline void
	98	nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
	99	{
	100	uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
	101	volatile uint64_t ptr = (volatile uint64_t )(long)addr;
	102
1ad4af85 J	103	if (sizeof(unsigned long) == 4) {
	104	unsigned long flags;
	105	uint64_t tmp;
	106
	107	local_irq_save(flags);
	108	__asm__ __volatile__(
	109	".set push" "\n\t"
	110	".set mips64" "\n\t"
	111	"dsll32 %L0, %L0, 0" "\n\t"
	112	"dsrl32 %L0, %L0, 0" "\n\t"
	113	"dsll32 %M0, %M0, 0" "\n\t"
	114	"or %L0, %L0, %M0" "\n\t"
	115	"sd %L0, %2" "\n\t"
	116	".set pop" "\n"
	117	: "=r" (tmp)
	118	: "0" (val), "m" (*ptr));
	119	local_irq_restore(flags);
	120	} else
	121	*ptr = val;
0c965407 J	122	}
	123
	124	/*
	125	* Routines to store 32/64 bit values to 64 bit addresses,
	126	* used when going thru XKPHYS to access registers
	127	*/
	128	static inline uint32_t
	129	nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
	130	{
	131	return nlm_read_reg(base, reg);
	132	}
	133
	134	static inline void
	135	nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
	136	{
	137	nlm_write_reg(base, reg, val);
	138	}
	139
	140	static inline uint64_t
	141	nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
	142	{
	143	return nlm_read_reg64(base, reg);
	144	}
	145
	146	static inline void
	147	nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
	148	{
	149	nlm_write_reg64(base, reg, val);
	150	}
	151
	152	/* Location where IO base is mapped */
	153	extern uint64_t nlm_io_base;
	154
65040e22 J	155	#if defined(CONFIG_CPU_XLP)
	156	static inline uint64_t
	157	nlm_pcicfg_base(uint32_t devoffset)
	158	{
	159	return nlm_io_base + devoffset;
	160	}
	161
65040e22 J	162	#elif defined(CONFIG_CPU_XLR)
65040e22 J	163
0c965407 J	164	static inline uint64_t
	165	nlm_mmio_base(uint32_t devoffset)
	166	{
	167	return nlm_io_base + devoffset;
	168	}
65040e22	169	#endif
0c965407 J	170
0c965407 J	171	#endif