projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 0c965407 J |
1 | /* |
| 2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | |
| 3 | * reserved. | |
| 4 | * | |
| 5 | * This software is available to you under a choice of one of two | |
| 6 | * licenses. You may choose to be licensed under the terms of the GNU | |
| 7 | * General Public License (GPL) Version 2, available from the file | |
| 8 | * COPYING in the main directory of this source tree, or the NetLogic | |
| 9 | * license below: | |
| 10 | * | |
| 11 | * Redistribution and use in source and binary forms, with or without | |
| 12 | * modification, are permitted provided that the following conditions | |
| 13 | * are met: | |
| 14 | * | |
| 15 | * 1. Redistributions of source code must retain the above copyright | |
| 16 | * notice, this list of conditions and the following disclaimer. | |
| 17 | * 2. Redistributions in binary form must reproduce the above copyright | |
| 18 | * notice, this list of conditions and the following disclaimer in | |
| 19 | * the documentation and/or other materials provided with the | |
| 20 | * distribution. | |
| 21 | * | |
| 22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | |
| 23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
| 24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
| 25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | |
| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
| 27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
| 28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | |
| 29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | |
| 30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | |
| 31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | |
| 32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 33 | */ | |
| 34 | ||
| 35 | #ifndef __NLM_HAL_HALDEFS_H__ | |
| 36 | #define __NLM_HAL_HALDEFS_H__ | |
| 37 | ||
| 38 | /* | |
| 39 | * This file contains platform specific memory mapped IO implementation | |
| 40 | * and will provide a way to read 32/64 bit memory mapped registers in | |
| 41 | * all ABIs | |
| 42 | */ | |
| 43 | /* | |
| 44 | * For o32 compilation, we have to disable interrupts and enable KX bit to | |
| 45 | * access 64 bit addresses or data. | |
| 46 | * | |
| 47 | * We need to disable interrupts because we save just the lower 32 bits of | |
| 48 | * registers in interrupt handling. So if we get hit by an interrupt while | |
| 49 | * using the upper 32 bits of a register, we lose. | |
| 50 | */ | |
| 51 | static inline uint32_t nlm_save_flags_kx(void) | |
| 52 | { | |
| 53 | return change_c0_status(ST0_KX | ST0_IE, ST0_KX); | |
| 54 | } | |
| 55 | ||
| 56 | static inline uint32_t nlm_save_flags_cop2(void) | |
| 57 | { | |
| 58 | return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2); | |
| 59 | } | |
| 60 | ||
| 61 | static inline void nlm_restore_flags(uint32_t sr) | |
| 62 | { | |
| 63 | write_c0_status(sr); | |
| 64 | } | |
| 65 | ||
| 66 | /* | |
| 67 | * The n64 implementations are simple, the o32 implementations when they | |
| 68 | * are added, will have to disable interrupts and enable KX before doing | |
| 69 | * 64 bit ops. | |
| 70 | */ | |
| 71 | static inline uint32_t | |
| 72 | nlm_read_reg(uint64_t base, uint32_t reg) | |
| 73 | { | |
| 74 | volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; | |
| 75 | ||
| 76 | return *addr; | |
| 77 | } | |
| 78 | ||
| 79 | static inline void | |
| 80 | nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) | |
| 81 | { | |
| 82 | volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; | |
| 83 | ||
| 84 | *addr = val; | |
| 85 | } | |
| 86 | ||
| 87 | static inline uint64_t | |
| 88 | nlm_read_reg64(uint64_t base, uint32_t reg) | |
| 89 | { | |
| 90 | uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); | |
| 91 | volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; | |
| 92 | ||
| 93 | return *ptr; | |
| 94 | } | |
| 95 | ||
| 96 | static inline void | |
| 97 | nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) | |
| 98 | { | |
| 99 | uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); | |
| 100 | volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; | |
| 101 | ||
| 102 | *ptr = val; | |
| 103 | } | |
| 104 | ||
| 105 | /* | |
| 106 | * Routines to store 32/64 bit values to 64 bit addresses, | |
| 107 | * used when going thru XKPHYS to access registers | |
| 108 | */ | |
| 109 | static inline uint32_t | |
| 110 | nlm_read_reg_xkphys(uint64_t base, uint32_t reg) | |
| 111 | { | |
| 112 | return nlm_read_reg(base, reg); | |
| 113 | } | |
| 114 | ||
| 115 | static inline void | |
| 116 | nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val) | |
| 117 | { | |
| 118 | nlm_write_reg(base, reg, val); | |
| 119 | } | |
| 120 | ||
| 121 | static inline uint64_t | |
| 122 | nlm_read_reg64_xkphys(uint64_t base, uint32_t reg) | |
| 123 | { | |
| 124 | return nlm_read_reg64(base, reg); | |
| 125 | } | |
| 126 | ||
| 127 | static inline void | |
| 128 | nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) | |
| 129 | { | |
| 130 | nlm_write_reg64(base, reg, val); | |
| 131 | } | |
| 132 | ||
| 133 | /* Location where IO base is mapped */ | |
| 134 | extern uint64_t nlm_io_base; | |
| 135 | ||
| 136 | static inline uint64_t | |
| 137 | nlm_mmio_base(uint32_t devoffset) | |
| 138 | { | |
| 139 | return nlm_io_base + devoffset; | |
| 140 | } | |
| 141 | ||
| 142 | #endif |