projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 5e983ff6 | 2 | /* |
| 6f7a251a | 3 | * Copyright (C) 2009 Lemote, Inc. |
| f7a904df | 4 | * Author: Wu Zhangjin <wuzhangjin@gmail.com> |
| 5e983ff6 WZ |
5 | */ |
| 6 | ||
| 30ad29bb HC |
7 | #ifndef __ASM_MACH_LOONGSON64_LOONGSON_H |
| 8 | #define __ASM_MACH_LOONGSON64_LOONGSON_H | |
| 5e983ff6 WZ |
9 | |
| 10 | #include <linux/io.h> | |
| 11 | #include <linux/init.h> | |
| ca4d3e67 | 12 | #include <linux/irq.h> |
| c7d3555a | 13 | #include <boot_param.h> |
| 5e983ff6 | 14 | |
| 5e983ff6 WZ |
15 | /* loongson internal northbridge initialization */ |
| 16 | extern void bonito_irq_init(void); | |
| 17 | ||
| 85749d24 WZ |
18 | /* machine-specific reboot/halt operation */ |
| 19 | extern void mach_prepare_reboot(void); | |
| 20 | extern void mach_prepare_shutdown(void); | |
| 21 | ||
| 5e983ff6 | 22 | /* environment arguments from bootloader */ |
| 1a08f152 HC |
23 | extern u32 cpu_clock_freq; |
| 24 | extern u32 memsize, highmemsize; | |
| ff2c8252 | 25 | extern const struct plat_smp_ops loongson3_smp_ops; |
| 5e983ff6 WZ |
26 | |
| 27 | /* loongson-specific command line, env and memory initialization */ | |
| 28 | extern void __init prom_init_memory(void); | |
| 29 | extern void __init prom_init_cmdline(void); | |
| 04cfb90a | 30 | extern void __init prom_init_machtype(void); |
| 5e983ff6 | 31 | extern void __init prom_init_env(void); |
| c3d8d850 | 32 | #ifdef CONFIG_LOONGSON_UART_BASE |
| 3adeb256 | 33 | extern unsigned long _loongson_uart_base[], loongson_uart_base[]; |
| c3d8d850 WZ |
34 | extern void prom_init_loongson_uart_base(void); |
| 35 | #endif | |
| 36 | ||
| 37 | static inline void prom_init_uart_base(void) | |
| 38 | { | |
| 39 | #ifdef CONFIG_LOONGSON_UART_BASE | |
| 40 | prom_init_loongson_uart_base(); | |
| 41 | #endif | |
| 42 | } | |
| 5e983ff6 | 43 | |
| 85749d24 WZ |
44 | /* irq operation functions */ |
| 45 | extern void bonito_irqdispatch(void); | |
| 46 | extern void __init bonito_irq_init(void); | |
| 85749d24 WZ |
47 | extern void __init mach_init_irq(void); |
| 48 | extern void mach_irq_dispatch(unsigned int pending); | |
| cb1ed9e1 | 49 | extern int mach_i8259_irq(void); |
| 85749d24 | 50 | |
| 2ee98e0f | 51 | /* We need this in some places... */ |
| 70342287 | 52 | #define delay() ({ \ |
| 2ee98e0f WZ |
53 | int x; \ |
| 54 | for (x = 0; x < 100000; x++) \ | |
| 55 | __asm__ __volatile__(""); \ | |
| 56 | }) | |
| 57 | ||
| e2fee572 WZ |
58 | #define LOONGSON_REG(x) \ |
| 59 | (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) | |
| 60 | ||
| d788bfa9 HC |
61 | #define LOONGSON3_REG8(base, x) \ |
| 62 | (*(volatile u8 *)((char *)TO_UNCAC(base) + (x))) | |
| 63 | ||
| 64 | #define LOONGSON3_REG32(base, x) \ | |
| 65 | (*(volatile u32 *)((char *)TO_UNCAC(base) + (x))) | |
| 66 | ||
| e2fee572 WZ |
67 | #define LOONGSON_IRQ_BASE 32 |
| 68 | #define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ | |
| 69 | ||
| de3bc0e7 WZ |
70 | #include <linux/interrupt.h> |
| 71 | static inline void do_perfcnt_IRQ(void) | |
| 72 | { | |
| a551fafb | 73 | #if IS_ENABLED(CONFIG_OPROFILE) |
| de3bc0e7 WZ |
74 | do_IRQ(LOONGSON2_PERFCNT_IRQ); |
| 75 | #endif | |
| 76 | } | |
| 77 | ||
| e2fee572 WZ |
78 | #define LOONGSON_FLASH_BASE 0x1c000000 |
| 79 | #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */ | |
| 80 | #define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1) | |
| 81 | ||
| 82 | #define LOONGSON_LIO0_BASE 0x1e000000 | |
| 83 | #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */ | |
| 84 | #define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1) | |
| 85 | ||
| 86 | #define LOONGSON_BOOT_BASE 0x1fc00000 | |
| 87 | #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */ | |
| 70342287 RB |
88 | #define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) |
| 89 | #define LOONGSON_REG_BASE 0x1fe00000 | |
| 90 | #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ | |
| e2fee572 | 91 | #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) |
| d788bfa9 HC |
92 | /* Loongson-3 specific registers */ |
| 93 | #define LOONGSON3_REG_BASE 0x3ff00000 | |
| 94 | #define LOONGSON3_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ | |
| 95 | #define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1) | |
| e2fee572 | 96 | |
| 70342287 RB |
97 | #define LOONGSON_LIO1_BASE 0x1ff00000 |
| 98 | #define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */ | |
| e2fee572 WZ |
99 | #define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1) |
| 100 | ||
| 101 | #define LOONGSON_PCILO0_BASE 0x10000000 | |
| 102 | #define LOONGSON_PCILO1_BASE 0x14000000 | |
| 103 | #define LOONGSON_PCILO2_BASE 0x18000000 | |
| 104 | #define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE | |
| 105 | #define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */ | |
| 106 | #define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1) | |
| 107 | ||
| 108 | #define LOONGSON_PCICFG_BASE 0x1fe80000 | |
| 109 | #define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */ | |
| 110 | #define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1) | |
| c7d3555a | 111 | |
| 437f2b8c | 112 | #ifdef CONFIG_CPU_LOONGSON3 |
| c7d3555a HC |
113 | #define LOONGSON_PCIIO_BASE loongson_sysconf.pci_io_base |
| 114 | #else | |
| e2fee572 | 115 | #define LOONGSON_PCIIO_BASE 0x1fd00000 |
| c7d3555a HC |
116 | #endif |
| 117 | ||
| e2fee572 WZ |
118 | #define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */ |
| 119 | #define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1) | |
| 120 | ||
| 121 | /* Loongson Register Bases */ | |
| 122 | ||
| 123 | #define LOONGSON_PCICONFIGBASE 0x00 | |
| 124 | #define LOONGSON_REGBASE 0x100 | |
| 125 | ||
| f7face03 | 126 | /* PCI Configuration Registers */ |
| e2fee572 WZ |
127 | |
| 128 | #define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x)) | |
| 129 | #define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00) | |
| 130 | #define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04) | |
| 70342287 | 131 | #define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08) |
| e2fee572 | 132 | #define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c) |
| 70342287 RB |
133 | #define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10) |
| 134 | #define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14) | |
| 135 | #define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18) | |
| 136 | #define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c) | |
| 137 | #define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20) | |
| e2fee572 WZ |
138 | #define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30) |
| 139 | #define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c) | |
| 140 | ||
| 141 | #define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c) | |
| 142 | ||
| 143 | #define LOONGSON_PCICMD_PERR_CLR 0x80000000 | |
| 144 | #define LOONGSON_PCICMD_SERR_CLR 0x40000000 | |
| 145 | #define LOONGSON_PCICMD_MABORT_CLR 0x20000000 | |
| 146 | #define LOONGSON_PCICMD_MTABORT_CLR 0x10000000 | |
| 147 | #define LOONGSON_PCICMD_TABORT_CLR 0x08000000 | |
| 70342287 | 148 | #define LOONGSON_PCICMD_MPERR_CLR 0x01000000 |
| e2fee572 WZ |
149 | #define LOONGSON_PCICMD_PERRRESPEN 0x00000040 |
| 150 | #define LOONGSON_PCICMD_ASTEPEN 0x00000080 | |
| 151 | #define LOONGSON_PCICMD_SERREN 0x00000100 | |
| 152 | #define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00 | |
| 153 | #define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8 | |
| 154 | ||
| 155 | /* Loongson h/w Configuration */ | |
| 156 | ||
| 157 | #define LOONGSON_GENCFG_OFFSET 0x4 | |
| 70342287 | 158 | #define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET) |
| e2fee572 WZ |
159 | |
| 160 | #define LOONGSON_GENCFG_DEBUGMODE 0x00000001 | |
| 161 | #define LOONGSON_GENCFG_SNOOPEN 0x00000002 | |
| 162 | #define LOONGSON_GENCFG_CPUSELFRESET 0x00000004 | |
| 163 | ||
| 164 | #define LOONGSON_GENCFG_FORCE_IRQA 0x00000008 | |
| 165 | #define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010 | |
| 166 | #define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020 | |
| 167 | #define LOONGSON_GENCFG_BYTESWAP 0x00000040 | |
| 168 | ||
| 169 | #define LOONGSON_GENCFG_UNCACHED 0x00000080 | |
| 170 | #define LOONGSON_GENCFG_PREFETCHEN 0x00000100 | |
| 171 | #define LOONGSON_GENCFG_WBEHINDEN 0x00000200 | |
| 172 | #define LOONGSON_GENCFG_CACHEALG 0x00000c00 | |
| 173 | #define LOONGSON_GENCFG_CACHEALG_SHIFT 10 | |
| 174 | #define LOONGSON_GENCFG_PCIQUEUE 0x00001000 | |
| 175 | #define LOONGSON_GENCFG_CACHESTOP 0x00002000 | |
| 176 | #define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000 | |
| 177 | #define LOONGSON_GENCFG_BUSERREN 0x00008000 | |
| 178 | #define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000 | |
| 179 | #define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000 | |
| 180 | ||
| 181 | /* PCI address map control */ | |
| 182 | ||
| 183 | #define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10) | |
| 184 | #define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14) | |
| 185 | #define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18) | |
| 186 | ||
| 187 | /* GPIO Regs - r/w */ | |
| 188 | ||
| 70342287 | 189 | #define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c) |
| e2fee572 WZ |
190 | #define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20) |
| 191 | ||
| 192 | /* ICU Configuration Regs - r/w */ | |
| 193 | ||
| 194 | #define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24) | |
| 70342287 | 195 | #define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) |
| e2fee572 WZ |
196 | #define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c) |
| 197 | ||
| 198 | /* ICU Enable Regs - IntEn & IntISR are r/o. */ | |
| 199 | ||
| 70342287 RB |
200 | #define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) |
| 201 | #define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) | |
| e2fee572 WZ |
202 | #define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38) |
| 203 | #define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c) | |
| 204 | ||
| 205 | /* ICU */ | |
| 206 | #define LOONGSON_ICU_MBOXES 0x0000000f | |
| 70342287 | 207 | #define LOONGSON_ICU_MBOXES_SHIFT 0 |
| e2fee572 WZ |
208 | #define LOONGSON_ICU_DMARDY 0x00000010 |
| 209 | #define LOONGSON_ICU_DMAEMPTY 0x00000020 | |
| 210 | #define LOONGSON_ICU_COPYRDY 0x00000040 | |
| 211 | #define LOONGSON_ICU_COPYEMPTY 0x00000080 | |
| 212 | #define LOONGSON_ICU_COPYERR 0x00000100 | |
| 213 | #define LOONGSON_ICU_PCIIRQ 0x00000200 | |
| 214 | #define LOONGSON_ICU_MASTERERR 0x00000400 | |
| 215 | #define LOONGSON_ICU_SYSTEMERR 0x00000800 | |
| 216 | #define LOONGSON_ICU_DRAMPERR 0x00001000 | |
| 217 | #define LOONGSON_ICU_RETRYERR 0x00002000 | |
| 218 | #define LOONGSON_ICU_GPIOS 0x01ff0000 | |
| 219 | #define LOONGSON_ICU_GPIOS_SHIFT 16 | |
| 220 | #define LOONGSON_ICU_GPINS 0x7e000000 | |
| 221 | #define LOONGSON_ICU_GPINS_SHIFT 25 | |
| 222 | #define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N))) | |
| 223 | #define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N))) | |
| 224 | #define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N))) | |
| 225 | ||
| 226 | /* PCI prefetch window base & mask */ | |
| 227 | ||
| 70342287 RB |
228 | #define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40) |
| 229 | #define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44) | |
| 230 | #define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48) | |
| 231 | #define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c) | |
| f7face03 WZ |
232 | |
| 233 | /* PCI_Hit*_Sel_* */ | |
| 234 | ||
| e2fee572 WZ |
235 | #define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50) |
| 236 | #define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54) | |
| 237 | #define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58) | |
| 238 | #define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c) | |
| 239 | #define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60) | |
| 240 | #define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64) | |
| f7face03 WZ |
241 | |
| 242 | /* PXArb Config & Status */ | |
| 243 | ||
| e2fee572 WZ |
244 | #define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68) |
| 245 | #define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c) | |
| 246 | ||
| 140e39c1 HC |
247 | #define MAX_PACKAGES 4 |
| 248 | ||
| 249 | /* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */ | |
| 250 | extern u64 loongson_chipcfg[MAX_PACKAGES]; | |
| 251 | #define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id])) | |
| c4a987db | 252 | |
| 64f09aa9 HC |
253 | /* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */ |
| 254 | extern u64 loongson_chiptemp[MAX_PACKAGES]; | |
| 255 | #define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id])) | |
| 256 | ||
| e7841be5 HC |
257 | /* Freq Control register of each physical cpu package, PRid >= Loongson-3B */ |
| 258 | extern u64 loongson_freqctrl[MAX_PACKAGES]; | |
| 259 | #define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id])) | |
| 260 | ||
| e2fee572 | 261 | /* pcimap */ |
| f7face03 | 262 | |
| e2fee572 WZ |
263 | #define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f |
| 264 | #define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0 | |
| 265 | #define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0 | |
| 266 | #define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6 | |
| 267 | #define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000 | |
| 268 | #define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12 | |
| 269 | #define LOONGSON_PCIMAP_PCIMAP_2 0x00040000 | |
| 270 | #define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ | |
| 271 | ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) | |
| 67b35e5d | 272 | |
| 55045ff5 | 273 | #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ |
| f8ede0f7 | 274 | #include <linux/cpufreq.h> |
| f8ede0f7 | 275 | extern struct cpufreq_frequency_table loongson2_clockmod_table[]; |
| 6f7a251a WZ |
276 | #endif |
| 277 | ||
| 278 | /* | |
| 279 | * address windows configuration module | |
| 280 | * | |
| 281 | * loongson2e do not have this module | |
| 282 | */ | |
| 55045ff5 | 283 | #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG |
| 6f7a251a WZ |
284 | |
| 285 | /* address window config module base address */ | |
| 286 | #define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul | |
| 287 | #define LOONGSON_ADDRWINCFG_SIZE 0x180 | |
| 288 | ||
| 289 | extern unsigned long _loongson_addrwincfg_base; | |
| 290 | #define LOONGSON_ADDRWINCFG(offset) \ | |
| 291 | (*(volatile u64 *)(_loongson_addrwincfg_base + (offset))) | |
| 292 | ||
| 293 | #define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00) | |
| 294 | #define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08) | |
| 295 | #define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10) | |
| 296 | #define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18) | |
| 297 | ||
| 298 | #define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20) | |
| 299 | #define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28) | |
| 300 | #define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30) | |
| 301 | #define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38) | |
| 302 | ||
| 303 | #define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40) | |
| 304 | #define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48) | |
| 305 | #define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50) | |
| 306 | #define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58) | |
| 307 | ||
| 308 | #define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60) | |
| 309 | #define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68) | |
| 310 | #define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70) | |
| 311 | #define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78) | |
| 312 | ||
| 313 | #define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80) | |
| 314 | #define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88) | |
| 315 | #define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90) | |
| 316 | #define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98) | |
| 317 | ||
| 318 | #define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0) | |
| 319 | #define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8) | |
| 320 | #define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0) | |
| 321 | #define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8) | |
| 322 | ||
| 323 | #define ADDRWIN_WIN0 0 | |
| 324 | #define ADDRWIN_WIN1 1 | |
| 325 | #define ADDRWIN_WIN2 2 | |
| 326 | #define ADDRWIN_WIN3 3 | |
| 327 | ||
| 328 | #define ADDRWIN_MAP_DST_DDR 0 | |
| 329 | #define ADDRWIN_MAP_DST_PCI 1 | |
| 330 | #define ADDRWIN_MAP_DST_LIO 1 | |
| 331 | ||
| 332 | /* | |
| 333 | * s: CPU, PCIDMA | |
| 334 | * d: DDR, PCI, LIO | |
| 335 | * win: 0, 1, 2, 3 | |
| 336 | * src: map source | |
| 337 | * dst: map destination | |
| 338 | * size: ~mask + 1 | |
| 339 | */ | |
| 340 | #define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\ | |
| 341 | s##_WIN##w##_BASE = (src); \ | |
| 94c26c9a | 342 | s##_WIN##w##_MMAP = (dst) | ADDRWIN_MAP_DST_##d; \ |
| 6f7a251a WZ |
343 | s##_WIN##w##_MASK = ~(size-1); \ |
| 344 | } while (0) | |
| 345 | ||
| 346 | #define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \ | |
| 347 | LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size) | |
| 348 | #define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \ | |
| 349 | LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size) | |
| 350 | #define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \ | |
| 351 | LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size) | |
| 352 | ||
| 55045ff5 | 353 | #endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */ |
| 6f7a251a | 354 | |
| 30ad29bb | 355 | #endif /* __ASM_MACH_LOONGSON64_LOONGSON_H */ |