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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994-1996 Linus Torvalds & authors | |
7 | * | |
8 | * Copied from i386; many of the especially older MIPS or ISA-based platforms | |
9 | * are basically identical. Using this file probably implies i8259 PIC | |
10 | * support in a system but the very least interrupt numbers 0 - 15 need to | |
11 | * be put aside for legacy devices. | |
12 | */ | |
13 | #ifndef __ASM_MACH_GENERIC_IDE_H | |
14 | #define __ASM_MACH_GENERIC_IDE_H | |
15 | ||
16 | #ifdef __KERNEL__ | |
17 | ||
1da177e4 LT |
18 | #include <linux/pci.h> |
19 | #include <linux/stddef.h> | |
9447cbfc | 20 | #include <asm/processor.h> |
1da177e4 | 21 | |
1da177e4 | 22 | /* MIPS port and memory-mapped I/O string operations. */ |
7e3bfc7c RB |
23 | static inline void __ide_flush_prologue(void) |
24 | { | |
25 | #ifdef CONFIG_SMP | |
26 | if (cpu_has_dc_aliases) | |
27 | preempt_disable(); | |
28 | #endif | |
29 | } | |
30 | ||
31 | static inline void __ide_flush_epilogue(void) | |
32 | { | |
33 | #ifdef CONFIG_SMP | |
34 | if (cpu_has_dc_aliases) | |
35 | preempt_enable(); | |
36 | #endif | |
37 | } | |
1da177e4 | 38 | |
9447cbfc RB |
39 | static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) |
40 | { | |
41 | if (cpu_has_dc_aliases) { | |
42 | unsigned long end = addr + size; | |
7e3bfc7c RB |
43 | |
44 | while (addr < end) { | |
45 | local_flush_data_cache_page((void *)addr); | |
46 | addr += PAGE_SIZE; | |
47 | } | |
9447cbfc RB |
48 | } |
49 | } | |
50 | ||
7e3bfc7c RB |
51 | /* |
52 | * insw() and gang might be called with interrupts disabled, so we can't | |
53 | * send IPIs for flushing due to the potencial of deadlocks, see the comment | |
70342287 | 54 | * above smp_call_function() in arch/mips/kernel/smp.c. We work around the |
7e3bfc7c RB |
55 | * problem by disabling preemption so we know we actually perform the flush |
56 | * on the processor that actually has the lines to be flushed which hopefully | |
57 | * is even better for performance anyway. | |
58 | */ | |
9447cbfc RB |
59 | static inline void __ide_insw(unsigned long port, void *addr, |
60 | unsigned int count) | |
61 | { | |
7e3bfc7c | 62 | __ide_flush_prologue(); |
9447cbfc RB |
63 | insw(port, addr, count); |
64 | __ide_flush_dcache_range((unsigned long)addr, count * 2); | |
7e3bfc7c | 65 | __ide_flush_epilogue(); |
9447cbfc RB |
66 | } |
67 | ||
68 | static inline void __ide_insl(unsigned long port, void *addr, unsigned int count) | |
69 | { | |
7e3bfc7c | 70 | __ide_flush_prologue(); |
9447cbfc RB |
71 | insl(port, addr, count); |
72 | __ide_flush_dcache_range((unsigned long)addr, count * 4); | |
7e3bfc7c | 73 | __ide_flush_epilogue(); |
9447cbfc RB |
74 | } |
75 | ||
76 | static inline void __ide_outsw(unsigned long port, const void *addr, | |
77 | unsigned long count) | |
78 | { | |
7e3bfc7c | 79 | __ide_flush_prologue(); |
9447cbfc RB |
80 | outsw(port, addr, count); |
81 | __ide_flush_dcache_range((unsigned long)addr, count * 2); | |
7e3bfc7c | 82 | __ide_flush_epilogue(); |
9447cbfc RB |
83 | } |
84 | ||
85 | static inline void __ide_outsl(unsigned long port, const void *addr, | |
86 | unsigned long count) | |
87 | { | |
7e3bfc7c | 88 | __ide_flush_prologue(); |
9447cbfc RB |
89 | outsl(port, addr, count); |
90 | __ide_flush_dcache_range((unsigned long)addr, count * 4); | |
7e3bfc7c | 91 | __ide_flush_epilogue(); |
9447cbfc RB |
92 | } |
93 | ||
94 | static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count) | |
95 | { | |
7e3bfc7c | 96 | __ide_flush_prologue(); |
9447cbfc RB |
97 | readsw(port, addr, count); |
98 | __ide_flush_dcache_range((unsigned long)addr, count * 2); | |
7e3bfc7c | 99 | __ide_flush_epilogue(); |
9447cbfc RB |
100 | } |
101 | ||
102 | static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count) | |
103 | { | |
7e3bfc7c | 104 | __ide_flush_prologue(); |
9447cbfc RB |
105 | readsl(port, addr, count); |
106 | __ide_flush_dcache_range((unsigned long)addr, count * 4); | |
7e3bfc7c | 107 | __ide_flush_epilogue(); |
9447cbfc RB |
108 | } |
109 | ||
110 | static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count) | |
111 | { | |
7e3bfc7c | 112 | __ide_flush_prologue(); |
9447cbfc RB |
113 | writesw(port, addr, count); |
114 | __ide_flush_dcache_range((unsigned long)addr, count * 2); | |
7e3bfc7c | 115 | __ide_flush_epilogue(); |
9447cbfc RB |
116 | } |
117 | ||
118 | static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count) | |
119 | { | |
7e3bfc7c | 120 | __ide_flush_prologue(); |
9447cbfc RB |
121 | writesl(port, addr, count); |
122 | __ide_flush_dcache_range((unsigned long)addr, count * 4); | |
7e3bfc7c | 123 | __ide_flush_epilogue(); |
9447cbfc | 124 | } |
1da177e4 | 125 | |
70342287 | 126 | /* ide_insw calls insw, not __ide_insw. Why? */ |
9447cbfc RB |
127 | #undef insw |
128 | #undef insl | |
a06d61c6 AN |
129 | #undef outsw |
130 | #undef outsl | |
9447cbfc RB |
131 | #define insw(port, addr, count) __ide_insw(port, addr, count) |
132 | #define insl(port, addr, count) __ide_insl(port, addr, count) | |
a06d61c6 AN |
133 | #define outsw(port, addr, count) __ide_outsw(port, addr, count) |
134 | #define outsl(port, addr, count) __ide_outsl(port, addr, count) | |
1da177e4 LT |
135 | |
136 | #endif /* __KERNEL__ */ | |
137 | ||
138 | #endif /* __ASM_MACH_GENERIC_IDE_H */ |