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MIPS: BCM63XX: Cleanup cpu registers.
[linux-2.6-block.git] / arch / mips / include / asm / mach-bcm63xx / bcm63xx_cpu.h
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e7300d04
MB		 1#ifndef BCM63XX_CPU_H_
2#define BCM63XX_CPU_H_
3
4#include <linux/types.h>
5#include <linux/init.h>
6
7/*
8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types)
11 */
12#define BCM6338_CPU_ID 0x6338
13#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348
15#define BCM6358_CPU_ID 0x6358
16
17void __init bcm63xx_cpu_init(void);
18u16 __bcm63xx_get_cpu_id(void);
19u16 bcm63xx_get_cpu_rev(void);
20unsigned int bcm63xx_get_cpu_freq(void);
21
22#ifdef CONFIG_BCM63XX_CPU_6338
23# ifdef bcm63xx_get_cpu_id
24# undef bcm63xx_get_cpu_id
25# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
26# define BCMCPU_RUNTIME_DETECT
27# else
28# define bcm63xx_get_cpu_id() BCM6338_CPU_ID
29# endif
30# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
31#else
32# define BCMCPU_IS_6338() (0)
33#endif
34
35#ifdef CONFIG_BCM63XX_CPU_6345
36# ifdef bcm63xx_get_cpu_id
37# undef bcm63xx_get_cpu_id
38# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
39# define BCMCPU_RUNTIME_DETECT
40# else
41# define bcm63xx_get_cpu_id() BCM6345_CPU_ID
42# endif
43# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
44#else
45# define BCMCPU_IS_6345() (0)
46#endif
47
48#ifdef CONFIG_BCM63XX_CPU_6348
49# ifdef bcm63xx_get_cpu_id
50# undef bcm63xx_get_cpu_id
51# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
52# define BCMCPU_RUNTIME_DETECT
53# else
54# define bcm63xx_get_cpu_id() BCM6348_CPU_ID
55# endif
56# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
57#else
58# define BCMCPU_IS_6348() (0)
59#endif
60
61#ifdef CONFIG_BCM63XX_CPU_6358
62# ifdef bcm63xx_get_cpu_id
63# undef bcm63xx_get_cpu_id
64# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
65# define BCMCPU_RUNTIME_DETECT
66# else
67# define bcm63xx_get_cpu_id() BCM6358_CPU_ID
68# endif
69# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
70#else
71# define BCMCPU_IS_6358() (0)
72#endif
73
74#ifndef bcm63xx_get_cpu_id
75#error "No CPU support configured"
76#endif
77
78/*
79 * While registers sets are (mostly) the same across 63xx CPU, base
80 * address of these sets do change.
81 */
82enum bcm63xx_regs_set {
83 RSET_DSL_LMEM = 0,
84 RSET_PERF,
85 RSET_TIMER,
86 RSET_WDT,
87 RSET_UART0,
524ef29c 88 RSET_UART1,
e7300d04
MB		 89 RSET_GPIO,
90 RSET_SPI,
91 RSET_UDC0,
92 RSET_OHCI0,
93 RSET_OHCI_PRIV,
94 RSET_USBH_PRIV,
95 RSET_MPI,
96 RSET_PCMCIA,
97 RSET_DSL,
98 RSET_ENET0,
99 RSET_ENET1,
100 RSET_ENETDMA,
101 RSET_EHCI0,
102 RSET_SDRAM,
103 RSET_MEMC,
104 RSET_DDR,
105};
106
107#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
108#define RSET_DSL_SIZE 4096
109#define RSET_WDT_SIZE 12
110#define RSET_ENET_SIZE 2048
111#define RSET_ENETDMA_SIZE 2048
112#define RSET_UART_SIZE 24
113#define RSET_UDC_SIZE 256
114#define RSET_OHCI_SIZE 256
115#define RSET_EHCI_SIZE 256
116#define RSET_PCMCIA_SIZE 12
117
118/*
119 * 6338 register sets base address
120 */
121#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
122#define BCM_6338_PERF_BASE (0xfffe0000)
123#define BCM_6338_BB_BASE (0xfffe0100)
124#define BCM_6338_TIMER_BASE (0xfffe0200)
125#define BCM_6338_WDT_BASE (0xfffe021c)
126#define BCM_6338_UART0_BASE (0xfffe0300)
524ef29c 127#define BCM_6338_UART1_BASE (0xdeadbeef)
e7300d04
MB		 128#define BCM_6338_GPIO_BASE (0xfffe0400)
129#define BCM_6338_SPI_BASE (0xfffe0c00)
130#define BCM_6338_UDC0_BASE (0xdeadbeef)
131#define BCM_6338_USBDMA_BASE (0xfffe2400)
132#define BCM_6338_OHCI0_BASE (0xdeadbeef)
133#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
134#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
135#define BCM_6338_MPI_BASE (0xfffe3160)
136#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
137#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
138#define BCM_6338_DSL_BASE (0xfffe1000)
139#define BCM_6338_SAR_BASE (0xfffe2000)
140#define BCM_6338_UBUS_BASE (0xdeadbeef)
141#define BCM_6338_ENET0_BASE (0xfffe2800)
142#define BCM_6338_ENET1_BASE (0xdeadbeef)
143#define BCM_6338_ENETDMA_BASE (0xfffe2400)
144#define BCM_6338_EHCI0_BASE (0xdeadbeef)
145#define BCM_6338_SDRAM_BASE (0xfffe3100)
146#define BCM_6338_MEMC_BASE (0xdeadbeef)
147#define BCM_6338_DDR_BASE (0xdeadbeef)
148
149/*
150 * 6345 register sets base address
151 */
152#define BCM_6345_DSL_LMEM_BASE (0xfff00000)
153#define BCM_6345_PERF_BASE (0xfffe0000)
154#define BCM_6345_BB_BASE (0xfffe0100)
155#define BCM_6345_TIMER_BASE (0xfffe0200)
156#define BCM_6345_WDT_BASE (0xfffe021c)
157#define BCM_6345_UART0_BASE (0xfffe0300)
524ef29c 158#define BCM_6345_UART1_BASE (0xdeadbeef)
e7300d04
MB		 159#define BCM_6345_GPIO_BASE (0xfffe0400)
160#define BCM_6345_SPI_BASE (0xdeadbeef)
161#define BCM_6345_UDC0_BASE (0xdeadbeef)
162#define BCM_6345_USBDMA_BASE (0xfffe2800)
163#define BCM_6345_ENET0_BASE (0xfffe1800)
164#define BCM_6345_ENETDMA_BASE (0xfffe2800)
165#define BCM_6345_PCMCIA_BASE (0xfffe2028)
166#define BCM_6345_MPI_BASE (0xdeadbeef)
167#define BCM_6345_OHCI0_BASE (0xfffe2100)
168#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
169#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
170#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
171#define BCM_6345_DSL_BASE (0xdeadbeef)
172#define BCM_6345_SAR_BASE (0xdeadbeef)
173#define BCM_6345_UBUS_BASE (0xdeadbeef)
174#define BCM_6345_ENET1_BASE (0xdeadbeef)
175#define BCM_6345_EHCI0_BASE (0xdeadbeef)
176#define BCM_6345_SDRAM_BASE (0xfffe2300)
177#define BCM_6345_MEMC_BASE (0xdeadbeef)
178#define BCM_6345_DDR_BASE (0xdeadbeef)
179
180/*
181 * 6348 register sets base address
182 */
183#define BCM_6348_DSL_LMEM_BASE (0xfff00000)
184#define BCM_6348_PERF_BASE (0xfffe0000)
185#define BCM_6348_TIMER_BASE (0xfffe0200)
186#define BCM_6348_WDT_BASE (0xfffe021c)
187#define BCM_6348_UART0_BASE (0xfffe0300)
524ef29c 188#define BCM_6348_UART1_BASE (0xdeadbeef)
e7300d04
MB		 189#define BCM_6348_GPIO_BASE (0xfffe0400)
190#define BCM_6348_SPI_BASE (0xfffe0c00)
191#define BCM_6348_UDC0_BASE (0xfffe1000)
192#define BCM_6348_OHCI0_BASE (0xfffe1b00)
193#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
194#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
195#define BCM_6348_MPI_BASE (0xfffe2000)
196#define BCM_6348_PCMCIA_BASE (0xfffe2054)
197#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
198#define BCM_6348_DSL_BASE (0xfffe3000)
199#define BCM_6348_ENET0_BASE (0xfffe6000)
200#define BCM_6348_ENET1_BASE (0xfffe6800)
201#define BCM_6348_ENETDMA_BASE (0xfffe7000)
202#define BCM_6348_EHCI0_BASE (0xdeadbeef)
203#define BCM_6348_SDRAM_BASE (0xfffe2300)
204#define BCM_6348_MEMC_BASE (0xdeadbeef)
205#define BCM_6348_DDR_BASE (0xdeadbeef)
206
207/*
208 * 6358 register sets base address
209 */
210#define BCM_6358_DSL_LMEM_BASE (0xfff00000)
211#define BCM_6358_PERF_BASE (0xfffe0000)
212#define BCM_6358_TIMER_BASE (0xfffe0040)
213#define BCM_6358_WDT_BASE (0xfffe005c)
214#define BCM_6358_UART0_BASE (0xfffe0100)
524ef29c 215#define BCM_6358_UART1_BASE (0xfffe0120)
e7300d04
MB		 216#define BCM_6358_GPIO_BASE (0xfffe0080)
217#define BCM_6358_SPI_BASE (0xdeadbeef)
218#define BCM_6358_UDC0_BASE (0xfffe0800)
219#define BCM_6358_OHCI0_BASE (0xfffe1400)
220#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
221#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
222#define BCM_6358_MPI_BASE (0xfffe1000)
223#define BCM_6358_PCMCIA_BASE (0xfffe1054)
224#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
225#define BCM_6358_DSL_BASE (0xfffe3000)
226#define BCM_6358_ENET0_BASE (0xfffe4000)
227#define BCM_6358_ENET1_BASE (0xfffe4800)
228#define BCM_6358_ENETDMA_BASE (0xfffe5000)
229#define BCM_6358_EHCI0_BASE (0xfffe1300)
230#define BCM_6358_SDRAM_BASE (0xdeadbeef)
231#define BCM_6358_MEMC_BASE (0xfffe1200)
232#define BCM_6358_DDR_BASE (0xfffe12a0)
233
234
235extern const unsigned long *bcm63xx_regs_base;
236
ec68c520
MB		 237#define __GEN_RSET_BASE(__cpu, __rset) \
238 case RSET_## __rset : \
239 return BCM_## __cpu ##_## __rset ##_BASE;
240
241#define __GEN_RSET(__cpu) \
242 switch (set) { \
243 __GEN_RSET_BASE(__cpu, DSL_LMEM) \
244 __GEN_RSET_BASE(__cpu, PERF) \
245 __GEN_RSET_BASE(__cpu, TIMER) \
246 __GEN_RSET_BASE(__cpu, WDT) \
247 __GEN_RSET_BASE(__cpu, UART0) \
248 __GEN_RSET_BASE(__cpu, UART1) \
249 __GEN_RSET_BASE(__cpu, GPIO) \
250 __GEN_RSET_BASE(__cpu, SPI) \
251 __GEN_RSET_BASE(__cpu, UDC0) \
252 __GEN_RSET_BASE(__cpu, OHCI0) \
253 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
254 __GEN_RSET_BASE(__cpu, USBH_PRIV) \
255 __GEN_RSET_BASE(__cpu, MPI) \
256 __GEN_RSET_BASE(__cpu, PCMCIA) \
257 __GEN_RSET_BASE(__cpu, DSL) \
258 __GEN_RSET_BASE(__cpu, ENET0) \
259 __GEN_RSET_BASE(__cpu, ENET1) \
260 __GEN_RSET_BASE(__cpu, ENETDMA) \
261 __GEN_RSET_BASE(__cpu, EHCI0) \
262 __GEN_RSET_BASE(__cpu, SDRAM) \
263 __GEN_RSET_BASE(__cpu, MEMC) \
264 __GEN_RSET_BASE(__cpu, DDR) \
265 }
266
267#define __GEN_CPU_REGS_TABLE(__cpu) \
268 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
269 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
270 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
271 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
272 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
273 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
274 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
275 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
276 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
277 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
278 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
279 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
280 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
281 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
282 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
283 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
284 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
285 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
286 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
287 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
288 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
289 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
290
291
e7300d04
MB		 292static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
293{
294#ifdef BCMCPU_RUNTIME_DETECT
295 return bcm63xx_regs_base[set];
296#else
297#ifdef CONFIG_BCM63XX_CPU_6338
ec68c520 298 __GEN_RSET(6338)
e7300d04
MB		 299#endif
300#ifdef CONFIG_BCM63XX_CPU_6345
ec68c520 301 __GEN_RSET(6345)
e7300d04
MB		 302#endif
303#ifdef CONFIG_BCM63XX_CPU_6348
ec68c520 304 __GEN_RSET(6348)
e7300d04
MB		 305#endif
306#ifdef CONFIG_BCM63XX_CPU_6358
ec68c520 307 __GEN_RSET(6358)
e7300d04
MB		 308#endif
309#endif
310 /* unreached */
311 return 0;
312}
313
314/*
315 * IRQ number changes across CPU too
316 */
317enum bcm63xx_irq {
318 IRQ_TIMER = 0,
319 IRQ_UART0,
524ef29c 320 IRQ_UART1,
e7300d04
MB		 321 IRQ_DSL,
322 IRQ_ENET0,
323 IRQ_ENET1,
324 IRQ_ENET_PHY,
325 IRQ_OHCI0,
326 IRQ_EHCI0,
e7300d04
MB		 327 IRQ_ENET0_RXDMA,
328 IRQ_ENET0_TXDMA,
329 IRQ_ENET1_RXDMA,
330 IRQ_ENET1_TXDMA,
331 IRQ_PCI,
332 IRQ_PCMCIA,
333};
334
335/*
336 * 6338 irqs
337 */
338#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
e7300d04 339#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
ec68c520 340#define BCM_6338_UART1_IRQ 0
e7300d04 341#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
e7300d04 342#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
ec68c520 343#define BCM_6338_ENET1_IRQ 0
e7300d04 344#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
ec68c520
MB		 345#define BCM_6338_OHCI0_IRQ 0
346#define BCM_6338_EHCI0_IRQ 0
e7300d04
MB		 347#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
348#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
ec68c520
MB		 349#define BCM_6338_ENET1_RXDMA_IRQ 0
350#define BCM_6338_ENET1_TXDMA_IRQ 0
351#define BCM_6338_PCI_IRQ 0
352#define BCM_6338_PCMCIA_IRQ 0
e7300d04
MB		 353
354/*
355 * 6345 irqs
356 */
357#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
358#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
ec68c520 359#define BCM_6345_UART1_IRQ 0
e7300d04 360#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
e7300d04 361#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
ec68c520 362#define BCM_6345_ENET1_IRQ 0
e7300d04 363#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
ec68c520
MB		 364#define BCM_6345_OHCI0_IRQ 0
365#define BCM_6345_EHCI0_IRQ 0
e7300d04
MB		 366#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
367#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
ec68c520
MB		 368#define BCM_6345_ENET1_RXDMA_IRQ 0
369#define BCM_6345_ENET1_TXDMA_IRQ 0
370#define BCM_6345_PCI_IRQ 0
371#define BCM_6345_PCMCIA_IRQ 0
e7300d04
MB		 372
373/*
374 * 6348 irqs
375 */
376#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
377#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
ec68c520 378#define BCM_6348_UART1_IRQ 0
e7300d04 379#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
e7300d04 380#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
ec68c520 381#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
e7300d04
MB		 382#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
383#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
ec68c520 384#define BCM_6348_EHCI0_IRQ 0
e7300d04
MB		 385#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
386#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
387#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
388#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
e7300d04 389#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
ec68c520 390#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
e7300d04
MB		 391
392/*
393 * 6358 irqs
394 */
395#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
396#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
524ef29c 397#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
ec68c520 398#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
e7300d04 399#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
ec68c520 400#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
e7300d04 401#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
ec68c520 402#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
e7300d04
MB		 403#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
404#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
405#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
406#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
407#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
e7300d04
MB		 408#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
409#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
410
411extern const int *bcm63xx_irqs;
412
ec68c520
MB		 413#define __GEN_CPU_IRQ_TABLE(__cpu) \
414 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
415 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
416 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
417 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
418 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
419 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
420 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
421 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
422 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
423 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
424 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
425 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
426 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
427 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
428 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
429
e7300d04
MB		 430static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
431{
432 return bcm63xx_irqs[irq];
433}
434
435/*
436 * return installed memory size
437 */
438unsigned int bcm63xx_get_memory_size(void);
439
440#endif /* !BCM63XX_CPU_H_ */
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