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740765ce SL |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
7 | * Authors: Sanjay Lal <sanjayl@kymasys.com> | |
8 | */ | |
9 | ||
10 | #ifndef __MIPS_KVM_HOST_H__ | |
11 | #define __MIPS_KVM_HOST_H__ | |
12 | ||
13 | #include <linux/mutex.h> | |
14 | #include <linux/hrtimer.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/kvm.h> | |
18 | #include <linux/kvm_types.h> | |
19 | #include <linux/threads.h> | |
20 | #include <linux/spinlock.h> | |
21 | ||
48a3c4e4 JH |
22 | /* MIPS KVM register ids */ |
23 | #define MIPS_CP0_32(_R, _S) \ | |
24 | (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S))) | |
25 | ||
26 | #define MIPS_CP0_64(_R, _S) \ | |
27 | (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S))) | |
28 | ||
29 | #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) | |
30 | #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0) | |
31 | #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0) | |
32 | #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) | |
33 | #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) | |
34 | #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) | |
35 | #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) | |
36 | #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) | |
37 | #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) | |
38 | #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) | |
39 | #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) | |
40 | #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) | |
41 | #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) | |
42 | #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) | |
43 | #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) | |
44 | #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) | |
1068eaaf | 45 | #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) |
48a3c4e4 JH |
46 | #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) |
47 | #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) | |
48 | #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) | |
49 | #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) | |
50 | #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) | |
51 | #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7) | |
52 | #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) | |
53 | #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) | |
54 | ||
740765ce SL |
55 | |
56 | #define KVM_MAX_VCPUS 1 | |
57 | #define KVM_USER_MEM_SLOTS 8 | |
58 | /* memory slots that does not exposed to userspace */ | |
59 | #define KVM_PRIVATE_MEM_SLOTS 0 | |
60 | ||
61 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 | |
62 | ||
740765ce SL |
63 | |
64 | ||
65 | /* Special address that contains the comm page, used for reducing # of traps */ | |
22027945 | 66 | #define KVM_GUEST_COMMPAGE_ADDR 0x0 |
740765ce SL |
67 | |
68 | #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \ | |
69 | ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0)) | |
70 | ||
22027945 JH |
71 | #define KVM_GUEST_KUSEG 0x00000000UL |
72 | #define KVM_GUEST_KSEG0 0x40000000UL | |
73 | #define KVM_GUEST_KSEG23 0x60000000UL | |
74 | #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000) | |
75 | #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) | |
740765ce SL |
76 | |
77 | #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) | |
78 | #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) | |
79 | #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) | |
80 | ||
81 | /* | |
82 | * Map an address to a certain kernel segment | |
83 | */ | |
84 | #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) | |
85 | #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) | |
86 | #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) | |
87 | ||
22027945 JH |
88 | #define KVM_INVALID_PAGE 0xdeadbeef |
89 | #define KVM_INVALID_INST 0xdeadbeef | |
90 | #define KVM_INVALID_ADDR 0xdeadbeef | |
740765ce | 91 | |
22027945 | 92 | #define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL |
740765ce | 93 | |
22027945 JH |
94 | #define GUEST_TICKS_PER_JIFFY (40000000/HZ) |
95 | #define MS_TO_NS(x) (x * 1E6L) | |
740765ce | 96 | |
22027945 JH |
97 | #define CAUSEB_DC 27 |
98 | #define CAUSEF_DC (_ULCAST_(1) << 27) | |
740765ce | 99 | |
740765ce SL |
100 | extern atomic_t kvm_mips_instance; |
101 | extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn); | |
102 | extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn); | |
103 | extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn); | |
104 | ||
105 | struct kvm_vm_stat { | |
106 | u32 remote_tlb_flush; | |
107 | }; | |
108 | ||
109 | struct kvm_vcpu_stat { | |
110 | u32 wait_exits; | |
111 | u32 cache_exits; | |
112 | u32 signal_exits; | |
113 | u32 int_exits; | |
114 | u32 cop_unusable_exits; | |
115 | u32 tlbmod_exits; | |
116 | u32 tlbmiss_ld_exits; | |
117 | u32 tlbmiss_st_exits; | |
118 | u32 addrerr_st_exits; | |
119 | u32 addrerr_ld_exits; | |
120 | u32 syscall_exits; | |
121 | u32 resvd_inst_exits; | |
122 | u32 break_inst_exits; | |
0a560427 | 123 | u32 trap_inst_exits; |
740765ce | 124 | u32 flush_dcache_exits; |
f7819512 | 125 | u32 halt_successful_poll; |
740765ce SL |
126 | u32 halt_wakeup; |
127 | }; | |
128 | ||
129 | enum kvm_mips_exit_types { | |
130 | WAIT_EXITS, | |
131 | CACHE_EXITS, | |
132 | SIGNAL_EXITS, | |
133 | INT_EXITS, | |
134 | COP_UNUSABLE_EXITS, | |
135 | TLBMOD_EXITS, | |
136 | TLBMISS_LD_EXITS, | |
137 | TLBMISS_ST_EXITS, | |
138 | ADDRERR_ST_EXITS, | |
139 | ADDRERR_LD_EXITS, | |
140 | SYSCALL_EXITS, | |
141 | RESVD_INST_EXITS, | |
142 | BREAK_INST_EXITS, | |
0a560427 | 143 | TRAP_INST_EXITS, |
740765ce SL |
144 | FLUSH_DCACHE_EXITS, |
145 | MAX_KVM_MIPS_EXIT_TYPES | |
146 | }; | |
147 | ||
148 | struct kvm_arch_memory_slot { | |
149 | }; | |
150 | ||
151 | struct kvm_arch { | |
152 | /* Guest GVA->HPA page table */ | |
153 | unsigned long *guest_pmap; | |
154 | unsigned long guest_pmap_npages; | |
155 | ||
156 | /* Wired host TLB used for the commpage */ | |
157 | int commpage_tlb; | |
158 | }; | |
159 | ||
22027945 JH |
160 | #define N_MIPS_COPROC_REGS 32 |
161 | #define N_MIPS_COPROC_SEL 8 | |
740765ce SL |
162 | |
163 | struct mips_coproc { | |
164 | unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; | |
165 | #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS | |
166 | unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; | |
167 | #endif | |
168 | }; | |
169 | ||
170 | /* | |
171 | * Coprocessor 0 register names | |
172 | */ | |
22027945 JH |
173 | #define MIPS_CP0_TLB_INDEX 0 |
174 | #define MIPS_CP0_TLB_RANDOM 1 | |
175 | #define MIPS_CP0_TLB_LOW 2 | |
176 | #define MIPS_CP0_TLB_LO0 2 | |
177 | #define MIPS_CP0_TLB_LO1 3 | |
178 | #define MIPS_CP0_TLB_CONTEXT 4 | |
179 | #define MIPS_CP0_TLB_PG_MASK 5 | |
180 | #define MIPS_CP0_TLB_WIRED 6 | |
181 | #define MIPS_CP0_HWRENA 7 | |
182 | #define MIPS_CP0_BAD_VADDR 8 | |
183 | #define MIPS_CP0_COUNT 9 | |
184 | #define MIPS_CP0_TLB_HI 10 | |
185 | #define MIPS_CP0_COMPARE 11 | |
186 | #define MIPS_CP0_STATUS 12 | |
187 | #define MIPS_CP0_CAUSE 13 | |
188 | #define MIPS_CP0_EXC_PC 14 | |
189 | #define MIPS_CP0_PRID 15 | |
190 | #define MIPS_CP0_CONFIG 16 | |
191 | #define MIPS_CP0_LLADDR 17 | |
192 | #define MIPS_CP0_WATCH_LO 18 | |
193 | #define MIPS_CP0_WATCH_HI 19 | |
194 | #define MIPS_CP0_TLB_XCONTEXT 20 | |
195 | #define MIPS_CP0_ECC 26 | |
196 | #define MIPS_CP0_CACHE_ERR 27 | |
197 | #define MIPS_CP0_TAG_LO 28 | |
198 | #define MIPS_CP0_TAG_HI 29 | |
199 | #define MIPS_CP0_ERROR_PC 30 | |
200 | #define MIPS_CP0_DEBUG 23 | |
201 | #define MIPS_CP0_DEPC 24 | |
202 | #define MIPS_CP0_PERFCNT 25 | |
203 | #define MIPS_CP0_ERRCTL 26 | |
204 | #define MIPS_CP0_DATA_LO 28 | |
205 | #define MIPS_CP0_DATA_HI 29 | |
206 | #define MIPS_CP0_DESAVE 31 | |
207 | ||
208 | #define MIPS_CP0_CONFIG_SEL 0 | |
209 | #define MIPS_CP0_CONFIG1_SEL 1 | |
210 | #define MIPS_CP0_CONFIG2_SEL 2 | |
211 | #define MIPS_CP0_CONFIG3_SEL 3 | |
740765ce SL |
212 | |
213 | /* Config0 register bits */ | |
22027945 JH |
214 | #define CP0C0_M 31 |
215 | #define CP0C0_K23 28 | |
216 | #define CP0C0_KU 25 | |
217 | #define CP0C0_MDU 20 | |
218 | #define CP0C0_MM 17 | |
219 | #define CP0C0_BM 16 | |
220 | #define CP0C0_BE 15 | |
221 | #define CP0C0_AT 13 | |
222 | #define CP0C0_AR 10 | |
223 | #define CP0C0_MT 7 | |
224 | #define CP0C0_VI 3 | |
225 | #define CP0C0_K0 0 | |
740765ce SL |
226 | |
227 | /* Config1 register bits */ | |
22027945 JH |
228 | #define CP0C1_M 31 |
229 | #define CP0C1_MMU 25 | |
230 | #define CP0C1_IS 22 | |
231 | #define CP0C1_IL 19 | |
232 | #define CP0C1_IA 16 | |
233 | #define CP0C1_DS 13 | |
234 | #define CP0C1_DL 10 | |
235 | #define CP0C1_DA 7 | |
236 | #define CP0C1_C2 6 | |
237 | #define CP0C1_MD 5 | |
238 | #define CP0C1_PC 4 | |
239 | #define CP0C1_WR 3 | |
240 | #define CP0C1_CA 2 | |
241 | #define CP0C1_EP 1 | |
242 | #define CP0C1_FP 0 | |
740765ce SL |
243 | |
244 | /* Config2 Register bits */ | |
22027945 JH |
245 | #define CP0C2_M 31 |
246 | #define CP0C2_TU 28 | |
247 | #define CP0C2_TS 24 | |
248 | #define CP0C2_TL 20 | |
249 | #define CP0C2_TA 16 | |
250 | #define CP0C2_SU 12 | |
251 | #define CP0C2_SS 8 | |
252 | #define CP0C2_SL 4 | |
253 | #define CP0C2_SA 0 | |
740765ce SL |
254 | |
255 | /* Config3 Register bits */ | |
22027945 JH |
256 | #define CP0C3_M 31 |
257 | #define CP0C3_ISA_ON_EXC 16 | |
258 | #define CP0C3_ULRI 13 | |
259 | #define CP0C3_DSPP 10 | |
260 | #define CP0C3_LPA 7 | |
261 | #define CP0C3_VEIC 6 | |
262 | #define CP0C3_VInt 5 | |
263 | #define CP0C3_SP 4 | |
264 | #define CP0C3_MT 2 | |
265 | #define CP0C3_SM 1 | |
266 | #define CP0C3_TL 0 | |
740765ce SL |
267 | |
268 | /* Have config1, Cacheable, noncoherent, write-back, write allocate*/ | |
22027945 | 269 | #define MIPS_CONFIG0 \ |
740765ce SL |
270 | ((1 << CP0C0_M) | (0x3 << CP0C0_K0)) |
271 | ||
272 | /* Have config2, no coprocessor2 attached, no MDMX support attached, | |
273 | no performance counters, watch registers present, | |
274 | no code compression, EJTAG present, no FPU, no watch registers */ | |
22027945 JH |
275 | #define MIPS_CONFIG1 \ |
276 | ((1 << CP0C1_M) | \ | |
277 | (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ | |
278 | (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ | |
740765ce SL |
279 | (0 << CP0C1_FP)) |
280 | ||
281 | /* Have config3, no tertiary/secondary caches implemented */ | |
22027945 | 282 | #define MIPS_CONFIG2 \ |
740765ce SL |
283 | ((1 << CP0C2_M)) |
284 | ||
285 | /* No config4, no DSP ASE, no large physaddr (PABITS), | |
286 | no external interrupt controller, no vectored interrupts, | |
287 | no 1kb pages, no SmartMIPS ASE, no trace logic */ | |
22027945 JH |
288 | #define MIPS_CONFIG3 \ |
289 | ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ | |
290 | (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ | |
740765ce SL |
291 | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
292 | ||
293 | /* MMU types, the first four entries have the same layout as the | |
294 | CP0C0_MT field. */ | |
295 | enum mips_mmu_types { | |
296 | MMU_TYPE_NONE, | |
297 | MMU_TYPE_R4000, | |
298 | MMU_TYPE_RESERVED, | |
299 | MMU_TYPE_FMT, | |
300 | MMU_TYPE_R3000, | |
301 | MMU_TYPE_R6000, | |
302 | MMU_TYPE_R8000 | |
303 | }; | |
304 | ||
305 | /* | |
306 | * Trap codes | |
307 | */ | |
22027945 JH |
308 | #define T_INT 0 /* Interrupt pending */ |
309 | #define T_TLB_MOD 1 /* TLB modified fault */ | |
310 | #define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */ | |
311 | #define T_TLB_ST_MISS 3 /* TLB miss on a store */ | |
312 | #define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */ | |
313 | #define T_ADDR_ERR_ST 5 /* Address error on a store */ | |
314 | #define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */ | |
315 | #define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */ | |
316 | #define T_SYSCALL 8 /* System call */ | |
317 | #define T_BREAK 9 /* Breakpoint */ | |
318 | #define T_RES_INST 10 /* Reserved instruction exception */ | |
319 | #define T_COP_UNUSABLE 11 /* Coprocessor unusable */ | |
320 | #define T_OVFLOW 12 /* Arithmetic overflow */ | |
740765ce SL |
321 | |
322 | /* | |
323 | * Trap definitions added for r4000 port. | |
324 | */ | |
22027945 JH |
325 | #define T_TRAP 13 /* Trap instruction */ |
326 | #define T_VCEI 14 /* Virtual coherency exception */ | |
327 | #define T_FPE 15 /* Floating point exception */ | |
98119ad5 | 328 | #define T_MSADIS 21 /* MSA disabled exception */ |
22027945 JH |
329 | #define T_WATCH 23 /* Watch address reference */ |
330 | #define T_VCED 31 /* Virtual coherency data */ | |
740765ce SL |
331 | |
332 | /* Resume Flags */ | |
22027945 JH |
333 | #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */ |
334 | #define RESUME_FLAG_HOST (1<<1) /* Resume host? */ | |
740765ce | 335 | |
22027945 JH |
336 | #define RESUME_GUEST 0 |
337 | #define RESUME_GUEST_DR RESUME_FLAG_DR | |
338 | #define RESUME_HOST RESUME_FLAG_HOST | |
740765ce SL |
339 | |
340 | enum emulation_result { | |
341 | EMULATE_DONE, /* no further processing */ | |
342 | EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */ | |
343 | EMULATE_FAIL, /* can't emulate this instruction */ | |
344 | EMULATE_WAIT, /* WAIT instruction */ | |
345 | EMULATE_PRIV_FAIL, | |
346 | }; | |
347 | ||
22027945 JH |
348 | #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */ |
349 | #define MIPS3_PG_V 0x00000002 /* Valid */ | |
350 | #define MIPS3_PG_NV 0x00000000 | |
351 | #define MIPS3_PG_D 0x00000004 /* Dirty */ | |
740765ce SL |
352 | |
353 | #define mips3_paddr_to_tlbpfn(x) \ | |
22027945 | 354 | (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME) |
740765ce | 355 | #define mips3_tlbpfn_to_paddr(x) \ |
22027945 | 356 | ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT) |
740765ce | 357 | |
22027945 JH |
358 | #define MIPS3_PG_SHIFT 6 |
359 | #define MIPS3_PG_FRAME 0x3fffffc0 | |
740765ce | 360 | |
22027945 | 361 | #define VPN2_MASK 0xffffe000 |
d116e812 | 362 | #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \ |
22027945 JH |
363 | ((x).tlb_lo1 & MIPS3_PG_G)) |
364 | #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK) | |
365 | #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK) | |
d116e812 DCZ |
366 | #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \ |
367 | ? ((x).tlb_lo1 & MIPS3_PG_V) \ | |
22027945 | 368 | : ((x).tlb_lo0 & MIPS3_PG_V)) |
d116e812 DCZ |
369 | #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \ |
370 | ((y) & VPN2_MASK & ~(x).tlb_mask)) | |
371 | #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \ | |
372 | TLB_ASID(x) == ((y) & ASID_MASK)) | |
740765ce SL |
373 | |
374 | struct kvm_mips_tlb { | |
375 | long tlb_mask; | |
376 | long tlb_hi; | |
377 | long tlb_lo0; | |
378 | long tlb_lo1; | |
379 | }; | |
380 | ||
22027945 | 381 | #define KVM_MIPS_GUEST_TLB_SIZE 64 |
740765ce SL |
382 | struct kvm_vcpu_arch { |
383 | void *host_ebase, *guest_ebase; | |
384 | unsigned long host_stack; | |
385 | unsigned long host_gp; | |
386 | ||
387 | /* Host CP0 registers used when handling exits from guest */ | |
388 | unsigned long host_cp0_badvaddr; | |
389 | unsigned long host_cp0_cause; | |
390 | unsigned long host_cp0_epc; | |
391 | unsigned long host_cp0_entryhi; | |
392 | uint32_t guest_inst; | |
393 | ||
394 | /* GPRS */ | |
395 | unsigned long gprs[32]; | |
396 | unsigned long hi; | |
397 | unsigned long lo; | |
398 | unsigned long pc; | |
399 | ||
400 | /* FPU State */ | |
401 | struct mips_fpu_struct fpu; | |
402 | ||
403 | /* COP0 State */ | |
404 | struct mips_coproc *cop0; | |
405 | ||
406 | /* Host KSEG0 address of the EI/DI offset */ | |
407 | void *kseg0_commpage; | |
408 | ||
409 | u32 io_gpr; /* GPR used as IO source/target */ | |
410 | ||
e30492bb | 411 | struct hrtimer comparecount_timer; |
f8239342 JH |
412 | /* Count timer control KVM register */ |
413 | uint32_t count_ctl; | |
e30492bb JH |
414 | /* Count bias from the raw time */ |
415 | uint32_t count_bias; | |
416 | /* Frequency of timer in Hz */ | |
417 | uint32_t count_hz; | |
418 | /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */ | |
419 | s64 count_dyn_bias; | |
f8239342 JH |
420 | /* Resume time */ |
421 | ktime_t count_resume; | |
e30492bb JH |
422 | /* Period of timer tick in ns */ |
423 | u64 count_period; | |
740765ce SL |
424 | |
425 | /* Bitmask of exceptions that are pending */ | |
426 | unsigned long pending_exceptions; | |
427 | ||
428 | /* Bitmask of pending exceptions to be cleared */ | |
429 | unsigned long pending_exceptions_clr; | |
430 | ||
431 | unsigned long pending_load_cause; | |
432 | ||
433 | /* Save/Restore the entryhi register when are are preempted/scheduled back in */ | |
434 | unsigned long preempt_entryhi; | |
435 | ||
436 | /* S/W Based TLB for guest */ | |
437 | struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE]; | |
438 | ||
439 | /* Cached guest kernel/user ASIDs */ | |
440 | uint32_t guest_user_asid[NR_CPUS]; | |
441 | uint32_t guest_kernel_asid[NR_CPUS]; | |
442 | struct mm_struct guest_kernel_mm, guest_user_mm; | |
443 | ||
740765ce SL |
444 | int last_sched_cpu; |
445 | ||
446 | /* WAIT executed */ | |
447 | int wait; | |
448 | }; | |
449 | ||
450 | ||
22027945 JH |
451 | #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0]) |
452 | #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val) | |
453 | #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0]) | |
454 | #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0]) | |
455 | #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0]) | |
456 | #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val)) | |
457 | #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2]) | |
7767b7d2 | 458 | #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val)) |
22027945 JH |
459 | #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0]) |
460 | #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val)) | |
461 | #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0]) | |
462 | #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val)) | |
26f4f3b5 JH |
463 | #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0]) |
464 | #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val)) | |
22027945 JH |
465 | #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0]) |
466 | #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val)) | |
467 | #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0]) | |
468 | #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val)) | |
469 | #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0]) | |
470 | #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val)) | |
471 | #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0]) | |
472 | #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val)) | |
473 | #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0]) | |
474 | #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val)) | |
475 | #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1]) | |
476 | #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val)) | |
477 | #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0]) | |
478 | #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val)) | |
479 | #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0]) | |
480 | #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val)) | |
481 | #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0]) | |
482 | #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val)) | |
483 | #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1]) | |
484 | #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val)) | |
485 | #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0]) | |
486 | #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1]) | |
487 | #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2]) | |
488 | #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3]) | |
489 | #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7]) | |
490 | #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val)) | |
491 | #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val)) | |
492 | #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val)) | |
493 | #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val)) | |
494 | #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val)) | |
495 | #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0]) | |
496 | #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val)) | |
497 | ||
c73c99b0 JH |
498 | /* |
499 | * Some of the guest registers may be modified asynchronously (e.g. from a | |
500 | * hrtimer callback in hard irq context) and therefore need stronger atomicity | |
501 | * guarantees than other registers. | |
502 | */ | |
503 | ||
504 | static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg, | |
505 | unsigned long val) | |
506 | { | |
507 | unsigned long temp; | |
508 | do { | |
509 | __asm__ __volatile__( | |
510 | " .set mips3 \n" | |
511 | " " __LL "%0, %1 \n" | |
512 | " or %0, %2 \n" | |
513 | " " __SC "%0, %1 \n" | |
514 | " .set mips0 \n" | |
515 | : "=&r" (temp), "+m" (*reg) | |
516 | : "r" (val)); | |
517 | } while (unlikely(!temp)); | |
518 | } | |
519 | ||
520 | static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg, | |
521 | unsigned long val) | |
522 | { | |
523 | unsigned long temp; | |
524 | do { | |
525 | __asm__ __volatile__( | |
526 | " .set mips3 \n" | |
527 | " " __LL "%0, %1 \n" | |
528 | " and %0, %2 \n" | |
529 | " " __SC "%0, %1 \n" | |
530 | " .set mips0 \n" | |
531 | : "=&r" (temp), "+m" (*reg) | |
532 | : "r" (~val)); | |
533 | } while (unlikely(!temp)); | |
534 | } | |
535 | ||
536 | static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg, | |
537 | unsigned long change, | |
538 | unsigned long val) | |
539 | { | |
540 | unsigned long temp; | |
541 | do { | |
542 | __asm__ __volatile__( | |
543 | " .set mips3 \n" | |
544 | " " __LL "%0, %1 \n" | |
545 | " and %0, %2 \n" | |
546 | " or %0, %3 \n" | |
547 | " " __SC "%0, %1 \n" | |
548 | " .set mips0 \n" | |
549 | : "=&r" (temp), "+m" (*reg) | |
550 | : "r" (~change), "r" (val & change)); | |
551 | } while (unlikely(!temp)); | |
552 | } | |
553 | ||
22027945 JH |
554 | #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val)) |
555 | #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val)) | |
c73c99b0 JH |
556 | |
557 | /* Cause can be modified asynchronously from hardirq hrtimer callback */ | |
558 | #define kvm_set_c0_guest_cause(cop0, val) \ | |
559 | _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val) | |
560 | #define kvm_clear_c0_guest_cause(cop0, val) \ | |
561 | _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val) | |
22027945 | 562 | #define kvm_change_c0_guest_cause(cop0, change, val) \ |
c73c99b0 JH |
563 | _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \ |
564 | change, val) | |
565 | ||
22027945 JH |
566 | #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val)) |
567 | #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val)) | |
568 | #define kvm_change_c0_guest_ebase(cop0, change, val) \ | |
569 | { \ | |
570 | kvm_clear_c0_guest_ebase(cop0, change); \ | |
571 | kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \ | |
740765ce SL |
572 | } |
573 | ||
574 | ||
575 | struct kvm_mips_callbacks { | |
2dca3725 JH |
576 | int (*handle_cop_unusable)(struct kvm_vcpu *vcpu); |
577 | int (*handle_tlb_mod)(struct kvm_vcpu *vcpu); | |
578 | int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu); | |
579 | int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu); | |
580 | int (*handle_addr_err_st)(struct kvm_vcpu *vcpu); | |
581 | int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu); | |
582 | int (*handle_syscall)(struct kvm_vcpu *vcpu); | |
583 | int (*handle_res_inst)(struct kvm_vcpu *vcpu); | |
584 | int (*handle_break)(struct kvm_vcpu *vcpu); | |
0a560427 | 585 | int (*handle_trap)(struct kvm_vcpu *vcpu); |
98119ad5 | 586 | int (*handle_msa_disabled)(struct kvm_vcpu *vcpu); |
2dca3725 JH |
587 | int (*vm_init)(struct kvm *kvm); |
588 | int (*vcpu_init)(struct kvm_vcpu *vcpu); | |
589 | int (*vcpu_setup)(struct kvm_vcpu *vcpu); | |
590 | gpa_t (*gva_to_gpa)(gva_t gva); | |
591 | void (*queue_timer_int)(struct kvm_vcpu *vcpu); | |
592 | void (*dequeue_timer_int)(struct kvm_vcpu *vcpu); | |
593 | void (*queue_io_int)(struct kvm_vcpu *vcpu, | |
594 | struct kvm_mips_interrupt *irq); | |
595 | void (*dequeue_io_int)(struct kvm_vcpu *vcpu, | |
596 | struct kvm_mips_interrupt *irq); | |
597 | int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority, | |
598 | uint32_t cause); | |
599 | int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority, | |
600 | uint32_t cause); | |
f8be02da JH |
601 | int (*get_one_reg)(struct kvm_vcpu *vcpu, |
602 | const struct kvm_one_reg *reg, s64 *v); | |
603 | int (*set_one_reg)(struct kvm_vcpu *vcpu, | |
604 | const struct kvm_one_reg *reg, s64 v); | |
740765ce SL |
605 | }; |
606 | extern struct kvm_mips_callbacks *kvm_mips_callbacks; | |
607 | int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks); | |
608 | ||
609 | /* Debug: dump vcpu state */ | |
610 | int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu); | |
611 | ||
612 | /* Trampoline ASM routine to start running in "Guest" context */ | |
613 | extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu); | |
614 | ||
615 | /* TLB handling */ | |
616 | uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu); | |
617 | ||
618 | uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu); | |
619 | ||
620 | uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu); | |
621 | ||
622 | extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr, | |
623 | struct kvm_vcpu *vcpu); | |
624 | ||
625 | extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr, | |
626 | struct kvm_vcpu *vcpu); | |
627 | ||
628 | extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu, | |
629 | struct kvm_mips_tlb *tlb, | |
630 | unsigned long *hpa0, | |
631 | unsigned long *hpa1); | |
632 | ||
633 | extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause, | |
634 | uint32_t *opc, | |
635 | struct kvm_run *run, | |
636 | struct kvm_vcpu *vcpu); | |
637 | ||
638 | extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause, | |
639 | uint32_t *opc, | |
640 | struct kvm_run *run, | |
641 | struct kvm_vcpu *vcpu); | |
642 | ||
643 | extern void kvm_mips_dump_host_tlbs(void); | |
644 | extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu); | |
740765ce SL |
645 | extern void kvm_mips_flush_host_tlb(int skip_kseg0); |
646 | extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi); | |
647 | extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index); | |
648 | ||
649 | extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, | |
650 | unsigned long entryhi); | |
651 | extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr); | |
652 | extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu, | |
653 | unsigned long gva); | |
654 | extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, | |
655 | struct kvm_vcpu *vcpu); | |
740765ce | 656 | extern void kvm_local_flush_tlb_all(void); |
740765ce SL |
657 | extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu); |
658 | extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu); | |
659 | extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu); | |
660 | ||
661 | /* Emulation */ | |
662 | uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu); | |
663 | enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause); | |
664 | ||
665 | extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause, | |
666 | uint32_t *opc, | |
667 | struct kvm_run *run, | |
668 | struct kvm_vcpu *vcpu); | |
669 | ||
670 | extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause, | |
671 | uint32_t *opc, | |
672 | struct kvm_run *run, | |
673 | struct kvm_vcpu *vcpu); | |
674 | ||
675 | extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause, | |
676 | uint32_t *opc, | |
677 | struct kvm_run *run, | |
678 | struct kvm_vcpu *vcpu); | |
679 | ||
680 | extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause, | |
681 | uint32_t *opc, | |
682 | struct kvm_run *run, | |
683 | struct kvm_vcpu *vcpu); | |
684 | ||
685 | extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause, | |
686 | uint32_t *opc, | |
687 | struct kvm_run *run, | |
688 | struct kvm_vcpu *vcpu); | |
689 | ||
690 | extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause, | |
691 | uint32_t *opc, | |
692 | struct kvm_run *run, | |
693 | struct kvm_vcpu *vcpu); | |
694 | ||
695 | extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause, | |
696 | uint32_t *opc, | |
697 | struct kvm_run *run, | |
698 | struct kvm_vcpu *vcpu); | |
699 | ||
700 | extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause, | |
701 | uint32_t *opc, | |
702 | struct kvm_run *run, | |
703 | struct kvm_vcpu *vcpu); | |
704 | ||
705 | extern enum emulation_result kvm_mips_handle_ri(unsigned long cause, | |
706 | uint32_t *opc, | |
707 | struct kvm_run *run, | |
708 | struct kvm_vcpu *vcpu); | |
709 | ||
710 | extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause, | |
711 | uint32_t *opc, | |
712 | struct kvm_run *run, | |
713 | struct kvm_vcpu *vcpu); | |
714 | ||
715 | extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause, | |
716 | uint32_t *opc, | |
717 | struct kvm_run *run, | |
718 | struct kvm_vcpu *vcpu); | |
719 | ||
0a560427 JH |
720 | extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause, |
721 | uint32_t *opc, | |
722 | struct kvm_run *run, | |
723 | struct kvm_vcpu *vcpu); | |
724 | ||
740765ce SL |
725 | extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu, |
726 | struct kvm_run *run); | |
727 | ||
e30492bb JH |
728 | uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu); |
729 | void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count); | |
730 | void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare); | |
731 | void kvm_mips_init_count(struct kvm_vcpu *vcpu); | |
f8239342 JH |
732 | int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl); |
733 | int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume); | |
f74a8e22 | 734 | int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz); |
e30492bb JH |
735 | void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu); |
736 | void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu); | |
737 | enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu); | |
740765ce SL |
738 | |
739 | enum emulation_result kvm_mips_check_privilege(unsigned long cause, | |
740 | uint32_t *opc, | |
741 | struct kvm_run *run, | |
742 | struct kvm_vcpu *vcpu); | |
743 | ||
744 | enum emulation_result kvm_mips_emulate_cache(uint32_t inst, | |
745 | uint32_t *opc, | |
746 | uint32_t cause, | |
747 | struct kvm_run *run, | |
748 | struct kvm_vcpu *vcpu); | |
749 | enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, | |
750 | uint32_t *opc, | |
751 | uint32_t cause, | |
752 | struct kvm_run *run, | |
753 | struct kvm_vcpu *vcpu); | |
754 | enum emulation_result kvm_mips_emulate_store(uint32_t inst, | |
755 | uint32_t cause, | |
756 | struct kvm_run *run, | |
757 | struct kvm_vcpu *vcpu); | |
758 | enum emulation_result kvm_mips_emulate_load(uint32_t inst, | |
759 | uint32_t cause, | |
760 | struct kvm_run *run, | |
761 | struct kvm_vcpu *vcpu); | |
762 | ||
763 | /* Dynamic binary translation */ | |
764 | extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc, | |
765 | struct kvm_vcpu *vcpu); | |
766 | extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc, | |
767 | struct kvm_vcpu *vcpu); | |
768 | extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc, | |
769 | struct kvm_vcpu *vcpu); | |
770 | extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc, | |
771 | struct kvm_vcpu *vcpu); | |
772 | ||
773 | /* Misc */ | |
d98403a5 | 774 | extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu); |
740765ce SL |
775 | extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm); |
776 | ||
13a34e06 | 777 | static inline void kvm_arch_hardware_disable(void) {} |
0865e636 RK |
778 | static inline void kvm_arch_hardware_unsetup(void) {} |
779 | static inline void kvm_arch_sync_events(struct kvm *kvm) {} | |
780 | static inline void kvm_arch_free_memslot(struct kvm *kvm, | |
781 | struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {} | |
782 | static inline void kvm_arch_memslots_updated(struct kvm *kvm) {} | |
783 | static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {} | |
784 | static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm, | |
785 | struct kvm_memory_slot *slot) {} | |
786 | static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} | |
787 | static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} | |
740765ce SL |
788 | |
789 | #endif /* __MIPS_KVM_HOST_H__ */ |