projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 740765ce SL |
1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | * License. See the file "COPYING" in the main directory of this archive | |
| 4 | * for more details. | |
| 5 | * | |
| 6 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
| 7 | * Authors: Sanjay Lal <sanjayl@kymasys.com> | |
| 8 | */ | |
| 9 | ||
| 10 | #ifndef __MIPS_KVM_HOST_H__ | |
| 11 | #define __MIPS_KVM_HOST_H__ | |
| 12 | ||
| 13 | #include <linux/mutex.h> | |
| 14 | #include <linux/hrtimer.h> | |
| 15 | #include <linux/interrupt.h> | |
| 16 | #include <linux/types.h> | |
| 17 | #include <linux/kvm.h> | |
| 18 | #include <linux/kvm_types.h> | |
| 19 | #include <linux/threads.h> | |
| 20 | #include <linux/spinlock.h> | |
| 21 | ||
| 48a3c4e4 JH |
22 | /* MIPS KVM register ids */ |
| 23 | #define MIPS_CP0_32(_R, _S) \ | |
| 7bd4acec | 24 | (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) |
| 48a3c4e4 JH |
25 | |
| 26 | #define MIPS_CP0_64(_R, _S) \ | |
| 7bd4acec | 27 | (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) |
| 48a3c4e4 JH |
28 | |
| 29 | #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) | |
| 30 | #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0) | |
| 31 | #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0) | |
| 32 | #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) | |
| 33 | #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) | |
| 34 | #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) | |
| 35 | #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) | |
| 36 | #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) | |
| 37 | #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) | |
| 38 | #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) | |
| 39 | #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) | |
| 40 | #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) | |
| 41 | #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) | |
| 42 | #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) | |
| 43 | #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) | |
| 44 | #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) | |
| 1068eaaf | 45 | #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) |
| 48a3c4e4 JH |
46 | #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) |
| 47 | #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) | |
| 48 | #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) | |
| 49 | #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) | |
| 50 | #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) | |
| c771607a JH |
51 | #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) |
| 52 | #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) | |
| 48a3c4e4 JH |
53 | #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7) |
| 54 | #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) | |
| 55 | #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) | |
| 56 | ||
| 740765ce SL |
57 | |
| 58 | #define KVM_MAX_VCPUS 1 | |
| 59 | #define KVM_USER_MEM_SLOTS 8 | |
| 60 | /* memory slots that does not exposed to userspace */ | |
| 61 | #define KVM_PRIVATE_MEM_SLOTS 0 | |
| 62 | ||
| 63 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 | |
| 64 | ||
| 740765ce SL |
65 | |
| 66 | ||
| 67 | /* Special address that contains the comm page, used for reducing # of traps */ | |
| 22027945 | 68 | #define KVM_GUEST_COMMPAGE_ADDR 0x0 |
| 740765ce SL |
69 | |
| 70 | #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \ | |
| 71 | ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0)) | |
| 72 | ||
| 22027945 JH |
73 | #define KVM_GUEST_KUSEG 0x00000000UL |
| 74 | #define KVM_GUEST_KSEG0 0x40000000UL | |
| 75 | #define KVM_GUEST_KSEG23 0x60000000UL | |
| 76 | #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000) | |
| 77 | #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) | |
| 740765ce SL |
78 | |
| 79 | #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) | |
| 80 | #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) | |
| 81 | #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) | |
| 82 | ||
| 83 | /* | |
| 84 | * Map an address to a certain kernel segment | |
| 85 | */ | |
| 86 | #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) | |
| 87 | #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) | |
| 88 | #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) | |
| 89 | ||
| 22027945 JH |
90 | #define KVM_INVALID_PAGE 0xdeadbeef |
| 91 | #define KVM_INVALID_INST 0xdeadbeef | |
| 92 | #define KVM_INVALID_ADDR 0xdeadbeef | |
| 740765ce | 93 | |
| 22027945 | 94 | #define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL |
| 740765ce | 95 | |
| 22027945 JH |
96 | #define GUEST_TICKS_PER_JIFFY (40000000/HZ) |
| 97 | #define MS_TO_NS(x) (x * 1E6L) | |
| 740765ce | 98 | |
| 22027945 JH |
99 | #define CAUSEB_DC 27 |
| 100 | #define CAUSEF_DC (_ULCAST_(1) << 27) | |
| 740765ce | 101 | |
| 740765ce SL |
102 | extern atomic_t kvm_mips_instance; |
| 103 | extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn); | |
| 104 | extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn); | |
| 105 | extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn); | |
| 106 | ||
| 107 | struct kvm_vm_stat { | |
| 108 | u32 remote_tlb_flush; | |
| 109 | }; | |
| 110 | ||
| 111 | struct kvm_vcpu_stat { | |
| 112 | u32 wait_exits; | |
| 113 | u32 cache_exits; | |
| 114 | u32 signal_exits; | |
| 115 | u32 int_exits; | |
| 116 | u32 cop_unusable_exits; | |
| 117 | u32 tlbmod_exits; | |
| 118 | u32 tlbmiss_ld_exits; | |
| 119 | u32 tlbmiss_st_exits; | |
| 120 | u32 addrerr_st_exits; | |
| 121 | u32 addrerr_ld_exits; | |
| 122 | u32 syscall_exits; | |
| 123 | u32 resvd_inst_exits; | |
| 124 | u32 break_inst_exits; | |
| 0a560427 | 125 | u32 trap_inst_exits; |
| 1c0cd66a | 126 | u32 fpe_exits; |
| 740765ce | 127 | u32 flush_dcache_exits; |
| f7819512 | 128 | u32 halt_successful_poll; |
| 740765ce SL |
129 | u32 halt_wakeup; |
| 130 | }; | |
| 131 | ||
| 132 | enum kvm_mips_exit_types { | |
| 133 | WAIT_EXITS, | |
| 134 | CACHE_EXITS, | |
| 135 | SIGNAL_EXITS, | |
| 136 | INT_EXITS, | |
| 137 | COP_UNUSABLE_EXITS, | |
| 138 | TLBMOD_EXITS, | |
| 139 | TLBMISS_LD_EXITS, | |
| 140 | TLBMISS_ST_EXITS, | |
| 141 | ADDRERR_ST_EXITS, | |
| 142 | ADDRERR_LD_EXITS, | |
| 143 | SYSCALL_EXITS, | |
| 144 | RESVD_INST_EXITS, | |
| 145 | BREAK_INST_EXITS, | |
| 0a560427 | 146 | TRAP_INST_EXITS, |
| 1c0cd66a | 147 | FPE_EXITS, |
| 740765ce SL |
148 | FLUSH_DCACHE_EXITS, |
| 149 | MAX_KVM_MIPS_EXIT_TYPES | |
| 150 | }; | |
| 151 | ||
| 152 | struct kvm_arch_memory_slot { | |
| 153 | }; | |
| 154 | ||
| 155 | struct kvm_arch { | |
| 156 | /* Guest GVA->HPA page table */ | |
| 157 | unsigned long *guest_pmap; | |
| 158 | unsigned long guest_pmap_npages; | |
| 159 | ||
| 160 | /* Wired host TLB used for the commpage */ | |
| 161 | int commpage_tlb; | |
| 162 | }; | |
| 163 | ||
| 22027945 JH |
164 | #define N_MIPS_COPROC_REGS 32 |
| 165 | #define N_MIPS_COPROC_SEL 8 | |
| 740765ce SL |
166 | |
| 167 | struct mips_coproc { | |
| 168 | unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; | |
| 169 | #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS | |
| 170 | unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; | |
| 171 | #endif | |
| 172 | }; | |
| 173 | ||
| 174 | /* | |
| 175 | * Coprocessor 0 register names | |
| 176 | */ | |
| 22027945 JH |
177 | #define MIPS_CP0_TLB_INDEX 0 |
| 178 | #define MIPS_CP0_TLB_RANDOM 1 | |
| 179 | #define MIPS_CP0_TLB_LOW 2 | |
| 180 | #define MIPS_CP0_TLB_LO0 2 | |
| 181 | #define MIPS_CP0_TLB_LO1 3 | |
| 182 | #define MIPS_CP0_TLB_CONTEXT 4 | |
| 183 | #define MIPS_CP0_TLB_PG_MASK 5 | |
| 184 | #define MIPS_CP0_TLB_WIRED 6 | |
| 185 | #define MIPS_CP0_HWRENA 7 | |
| 186 | #define MIPS_CP0_BAD_VADDR 8 | |
| 187 | #define MIPS_CP0_COUNT 9 | |
| 188 | #define MIPS_CP0_TLB_HI 10 | |
| 189 | #define MIPS_CP0_COMPARE 11 | |
| 190 | #define MIPS_CP0_STATUS 12 | |
| 191 | #define MIPS_CP0_CAUSE 13 | |
| 192 | #define MIPS_CP0_EXC_PC 14 | |
| 193 | #define MIPS_CP0_PRID 15 | |
| 194 | #define MIPS_CP0_CONFIG 16 | |
| 195 | #define MIPS_CP0_LLADDR 17 | |
| 196 | #define MIPS_CP0_WATCH_LO 18 | |
| 197 | #define MIPS_CP0_WATCH_HI 19 | |
| 198 | #define MIPS_CP0_TLB_XCONTEXT 20 | |
| 199 | #define MIPS_CP0_ECC 26 | |
| 200 | #define MIPS_CP0_CACHE_ERR 27 | |
| 201 | #define MIPS_CP0_TAG_LO 28 | |
| 202 | #define MIPS_CP0_TAG_HI 29 | |
| 203 | #define MIPS_CP0_ERROR_PC 30 | |
| 204 | #define MIPS_CP0_DEBUG 23 | |
| 205 | #define MIPS_CP0_DEPC 24 | |
| 206 | #define MIPS_CP0_PERFCNT 25 | |
| 207 | #define MIPS_CP0_ERRCTL 26 | |
| 208 | #define MIPS_CP0_DATA_LO 28 | |
| 209 | #define MIPS_CP0_DATA_HI 29 | |
| 210 | #define MIPS_CP0_DESAVE 31 | |
| 211 | ||
| 212 | #define MIPS_CP0_CONFIG_SEL 0 | |
| 213 | #define MIPS_CP0_CONFIG1_SEL 1 | |
| 214 | #define MIPS_CP0_CONFIG2_SEL 2 | |
| 215 | #define MIPS_CP0_CONFIG3_SEL 3 | |
| c771607a JH |
216 | #define MIPS_CP0_CONFIG4_SEL 4 |
| 217 | #define MIPS_CP0_CONFIG5_SEL 5 | |
| 740765ce SL |
218 | |
| 219 | /* Config0 register bits */ | |
| 22027945 JH |
220 | #define CP0C0_M 31 |
| 221 | #define CP0C0_K23 28 | |
| 222 | #define CP0C0_KU 25 | |
| 223 | #define CP0C0_MDU 20 | |
| 224 | #define CP0C0_MM 17 | |
| 225 | #define CP0C0_BM 16 | |
| 226 | #define CP0C0_BE 15 | |
| 227 | #define CP0C0_AT 13 | |
| 228 | #define CP0C0_AR 10 | |
| 229 | #define CP0C0_MT 7 | |
| 230 | #define CP0C0_VI 3 | |
| 231 | #define CP0C0_K0 0 | |
| 740765ce SL |
232 | |
| 233 | /* Config1 register bits */ | |
| 22027945 JH |
234 | #define CP0C1_M 31 |
| 235 | #define CP0C1_MMU 25 | |
| 236 | #define CP0C1_IS 22 | |
| 237 | #define CP0C1_IL 19 | |
| 238 | #define CP0C1_IA 16 | |
| 239 | #define CP0C1_DS 13 | |
| 240 | #define CP0C1_DL 10 | |
| 241 | #define CP0C1_DA 7 | |
| 242 | #define CP0C1_C2 6 | |
| 243 | #define CP0C1_MD 5 | |
| 244 | #define CP0C1_PC 4 | |
| 245 | #define CP0C1_WR 3 | |
| 246 | #define CP0C1_CA 2 | |
| 247 | #define CP0C1_EP 1 | |
| 248 | #define CP0C1_FP 0 | |
| 740765ce SL |
249 | |
| 250 | /* Config2 Register bits */ | |
| 22027945 JH |
251 | #define CP0C2_M 31 |
| 252 | #define CP0C2_TU 28 | |
| 253 | #define CP0C2_TS 24 | |
| 254 | #define CP0C2_TL 20 | |
| 255 | #define CP0C2_TA 16 | |
| 256 | #define CP0C2_SU 12 | |
| 257 | #define CP0C2_SS 8 | |
| 258 | #define CP0C2_SL 4 | |
| 259 | #define CP0C2_SA 0 | |
| 740765ce SL |
260 | |
| 261 | /* Config3 Register bits */ | |
| 22027945 JH |
262 | #define CP0C3_M 31 |
| 263 | #define CP0C3_ISA_ON_EXC 16 | |
| 264 | #define CP0C3_ULRI 13 | |
| 265 | #define CP0C3_DSPP 10 | |
| 266 | #define CP0C3_LPA 7 | |
| 267 | #define CP0C3_VEIC 6 | |
| 268 | #define CP0C3_VInt 5 | |
| 269 | #define CP0C3_SP 4 | |
| 270 | #define CP0C3_MT 2 | |
| 271 | #define CP0C3_SM 1 | |
| 272 | #define CP0C3_TL 0 | |
| 740765ce | 273 | |
| 740765ce SL |
274 | /* MMU types, the first four entries have the same layout as the |
| 275 | CP0C0_MT field. */ | |
| 276 | enum mips_mmu_types { | |
| 277 | MMU_TYPE_NONE, | |
| 278 | MMU_TYPE_R4000, | |
| 279 | MMU_TYPE_RESERVED, | |
| 280 | MMU_TYPE_FMT, | |
| 281 | MMU_TYPE_R3000, | |
| 282 | MMU_TYPE_R6000, | |
| 283 | MMU_TYPE_R8000 | |
| 284 | }; | |
| 285 | ||
| 286 | /* | |
| 287 | * Trap codes | |
| 288 | */ | |
| 22027945 JH |
289 | #define T_INT 0 /* Interrupt pending */ |
| 290 | #define T_TLB_MOD 1 /* TLB modified fault */ | |
| 291 | #define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */ | |
| 292 | #define T_TLB_ST_MISS 3 /* TLB miss on a store */ | |
| 293 | #define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */ | |
| 294 | #define T_ADDR_ERR_ST 5 /* Address error on a store */ | |
| 295 | #define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */ | |
| 296 | #define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */ | |
| 297 | #define T_SYSCALL 8 /* System call */ | |
| 298 | #define T_BREAK 9 /* Breakpoint */ | |
| 299 | #define T_RES_INST 10 /* Reserved instruction exception */ | |
| 300 | #define T_COP_UNUSABLE 11 /* Coprocessor unusable */ | |
| 301 | #define T_OVFLOW 12 /* Arithmetic overflow */ | |
| 740765ce SL |
302 | |
| 303 | /* | |
| 304 | * Trap definitions added for r4000 port. | |
| 305 | */ | |
| 22027945 JH |
306 | #define T_TRAP 13 /* Trap instruction */ |
| 307 | #define T_VCEI 14 /* Virtual coherency exception */ | |
| 308 | #define T_FPE 15 /* Floating point exception */ | |
| 98119ad5 | 309 | #define T_MSADIS 21 /* MSA disabled exception */ |
| 22027945 JH |
310 | #define T_WATCH 23 /* Watch address reference */ |
| 311 | #define T_VCED 31 /* Virtual coherency data */ | |
| 740765ce SL |
312 | |
| 313 | /* Resume Flags */ | |
| 22027945 JH |
314 | #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */ |
| 315 | #define RESUME_FLAG_HOST (1<<1) /* Resume host? */ | |
| 740765ce | 316 | |
| 22027945 JH |
317 | #define RESUME_GUEST 0 |
| 318 | #define RESUME_GUEST_DR RESUME_FLAG_DR | |
| 319 | #define RESUME_HOST RESUME_FLAG_HOST | |
| 740765ce SL |
320 | |
| 321 | enum emulation_result { | |
| 322 | EMULATE_DONE, /* no further processing */ | |
| 323 | EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */ | |
| 324 | EMULATE_FAIL, /* can't emulate this instruction */ | |
| 325 | EMULATE_WAIT, /* WAIT instruction */ | |
| 326 | EMULATE_PRIV_FAIL, | |
| 327 | }; | |
| 328 | ||
| 22027945 JH |
329 | #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */ |
| 330 | #define MIPS3_PG_V 0x00000002 /* Valid */ | |
| 331 | #define MIPS3_PG_NV 0x00000000 | |
| 332 | #define MIPS3_PG_D 0x00000004 /* Dirty */ | |
| 740765ce SL |
333 | |
| 334 | #define mips3_paddr_to_tlbpfn(x) \ | |
| 22027945 | 335 | (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME) |
| 740765ce | 336 | #define mips3_tlbpfn_to_paddr(x) \ |
| 22027945 | 337 | ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT) |
| 740765ce | 338 | |
| 22027945 JH |
339 | #define MIPS3_PG_SHIFT 6 |
| 340 | #define MIPS3_PG_FRAME 0x3fffffc0 | |
| 740765ce | 341 | |
| 22027945 | 342 | #define VPN2_MASK 0xffffe000 |
| d116e812 | 343 | #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \ |
| 22027945 JH |
344 | ((x).tlb_lo1 & MIPS3_PG_G)) |
| 345 | #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK) | |
| 346 | #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK) | |
| d116e812 DCZ |
347 | #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \ |
| 348 | ? ((x).tlb_lo1 & MIPS3_PG_V) \ | |
| 22027945 | 349 | : ((x).tlb_lo0 & MIPS3_PG_V)) |
| d116e812 DCZ |
350 | #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \ |
| 351 | ((y) & VPN2_MASK & ~(x).tlb_mask)) | |
| 352 | #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \ | |
| 353 | TLB_ASID(x) == ((y) & ASID_MASK)) | |
| 740765ce SL |
354 | |
| 355 | struct kvm_mips_tlb { | |
| 356 | long tlb_mask; | |
| 357 | long tlb_hi; | |
| 358 | long tlb_lo0; | |
| 359 | long tlb_lo1; | |
| 360 | }; | |
| 361 | ||
| 98e91b84 | 362 | #define KVM_MIPS_FPU_FPU 0x1 |
| 539cb89f | 363 | #define KVM_MIPS_FPU_MSA 0x2 |
| 98e91b84 | 364 | |
| 22027945 | 365 | #define KVM_MIPS_GUEST_TLB_SIZE 64 |
| 740765ce SL |
366 | struct kvm_vcpu_arch { |
| 367 | void *host_ebase, *guest_ebase; | |
| 368 | unsigned long host_stack; | |
| 369 | unsigned long host_gp; | |
| 370 | ||
| 371 | /* Host CP0 registers used when handling exits from guest */ | |
| 372 | unsigned long host_cp0_badvaddr; | |
| 373 | unsigned long host_cp0_cause; | |
| 374 | unsigned long host_cp0_epc; | |
| 375 | unsigned long host_cp0_entryhi; | |
| 376 | uint32_t guest_inst; | |
| 377 | ||
| 378 | /* GPRS */ | |
| 379 | unsigned long gprs[32]; | |
| 380 | unsigned long hi; | |
| 381 | unsigned long lo; | |
| 382 | unsigned long pc; | |
| 383 | ||
| 384 | /* FPU State */ | |
| 385 | struct mips_fpu_struct fpu; | |
| 98e91b84 JH |
386 | /* Which FPU state is loaded (KVM_MIPS_FPU_*) */ |
| 387 | unsigned int fpu_inuse; | |
| 740765ce SL |
388 | |
| 389 | /* COP0 State */ | |
| 390 | struct mips_coproc *cop0; | |
| 391 | ||
| 392 | /* Host KSEG0 address of the EI/DI offset */ | |
| 393 | void *kseg0_commpage; | |
| 394 | ||
| 395 | u32 io_gpr; /* GPR used as IO source/target */ | |
| 396 | ||
| e30492bb | 397 | struct hrtimer comparecount_timer; |
| f8239342 JH |
398 | /* Count timer control KVM register */ |
| 399 | uint32_t count_ctl; | |
| e30492bb JH |
400 | /* Count bias from the raw time */ |
| 401 | uint32_t count_bias; | |
| 402 | /* Frequency of timer in Hz */ | |
| 403 | uint32_t count_hz; | |
| 404 | /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */ | |
| 405 | s64 count_dyn_bias; | |
| f8239342 JH |
406 | /* Resume time */ |
| 407 | ktime_t count_resume; | |
| e30492bb JH |
408 | /* Period of timer tick in ns */ |
| 409 | u64 count_period; | |
| 740765ce SL |
410 | |
| 411 | /* Bitmask of exceptions that are pending */ | |
| 412 | unsigned long pending_exceptions; | |
| 413 | ||
| 414 | /* Bitmask of pending exceptions to be cleared */ | |
| 415 | unsigned long pending_exceptions_clr; | |
| 416 | ||
| 417 | unsigned long pending_load_cause; | |
| 418 | ||
| 419 | /* Save/Restore the entryhi register when are are preempted/scheduled back in */ | |
| 420 | unsigned long preempt_entryhi; | |
| 421 | ||
| 422 | /* S/W Based TLB for guest */ | |
| 423 | struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE]; | |
| 424 | ||
| 425 | /* Cached guest kernel/user ASIDs */ | |
| 426 | uint32_t guest_user_asid[NR_CPUS]; | |
| 427 | uint32_t guest_kernel_asid[NR_CPUS]; | |
| 428 | struct mm_struct guest_kernel_mm, guest_user_mm; | |
| 429 | ||
| 740765ce SL |
430 | int last_sched_cpu; |
| 431 | ||
| 432 | /* WAIT executed */ | |
| 433 | int wait; | |
| 98e91b84 JH |
434 | |
| 435 | u8 fpu_enabled; | |
| 539cb89f | 436 | u8 msa_enabled; |
| 740765ce SL |
437 | }; |
| 438 | ||
| 439 | ||
| 22027945 JH |
440 | #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0]) |
| 441 | #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val) | |
| 442 | #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0]) | |
| 443 | #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0]) | |
| 444 | #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0]) | |
| 445 | #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val)) | |
| 446 | #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2]) | |
| 7767b7d2 | 447 | #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val)) |
| 22027945 JH |
448 | #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0]) |
| 449 | #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val)) | |
| 450 | #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0]) | |
| 451 | #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val)) | |
| 26f4f3b5 JH |
452 | #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0]) |
| 453 | #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val)) | |
| 22027945 JH |
454 | #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0]) |
| 455 | #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val)) | |
| 456 | #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0]) | |
| 457 | #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val)) | |
| 458 | #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0]) | |
| 459 | #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val)) | |
| 460 | #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0]) | |
| 461 | #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val)) | |
| 462 | #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0]) | |
| 463 | #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val)) | |
| 464 | #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1]) | |
| 465 | #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val)) | |
| 466 | #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0]) | |
| 467 | #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val)) | |
| 468 | #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0]) | |
| 469 | #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val)) | |
| 470 | #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0]) | |
| 471 | #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val)) | |
| 472 | #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1]) | |
| 473 | #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val)) | |
| 474 | #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0]) | |
| 475 | #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1]) | |
| 476 | #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2]) | |
| 477 | #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3]) | |
| c771607a JH |
478 | #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4]) |
| 479 | #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5]) | |
| 22027945 JH |
480 | #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7]) |
| 481 | #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val)) | |
| 482 | #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val)) | |
| 483 | #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val)) | |
| 484 | #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val)) | |
| c771607a JH |
485 | #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val)) |
| 486 | #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val)) | |
| 22027945 JH |
487 | #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val)) |
| 488 | #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0]) | |
| 489 | #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val)) | |
| 490 | ||
| c73c99b0 JH |
491 | /* |
| 492 | * Some of the guest registers may be modified asynchronously (e.g. from a | |
| 493 | * hrtimer callback in hard irq context) and therefore need stronger atomicity | |
| 494 | * guarantees than other registers. | |
| 495 | */ | |
| 496 | ||
| 497 | static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg, | |
| 498 | unsigned long val) | |
| 499 | { | |
| 500 | unsigned long temp; | |
| 501 | do { | |
| 502 | __asm__ __volatile__( | |
| 503 | " .set mips3 \n" | |
| 504 | " " __LL "%0, %1 \n" | |
| 505 | " or %0, %2 \n" | |
| 506 | " " __SC "%0, %1 \n" | |
| 507 | " .set mips0 \n" | |
| 508 | : "=&r" (temp), "+m" (*reg) | |
| 509 | : "r" (val)); | |
| 510 | } while (unlikely(!temp)); | |
| 511 | } | |
| 512 | ||
| 513 | static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg, | |
| 514 | unsigned long val) | |
| 515 | { | |
| 516 | unsigned long temp; | |
| 517 | do { | |
| 518 | __asm__ __volatile__( | |
| 519 | " .set mips3 \n" | |
| 520 | " " __LL "%0, %1 \n" | |
| 521 | " and %0, %2 \n" | |
| 522 | " " __SC "%0, %1 \n" | |
| 523 | " .set mips0 \n" | |
| 524 | : "=&r" (temp), "+m" (*reg) | |
| 525 | : "r" (~val)); | |
| 526 | } while (unlikely(!temp)); | |
| 527 | } | |
| 528 | ||
| 529 | static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg, | |
| 530 | unsigned long change, | |
| 531 | unsigned long val) | |
| 532 | { | |
| 533 | unsigned long temp; | |
| 534 | do { | |
| 535 | __asm__ __volatile__( | |
| 536 | " .set mips3 \n" | |
| 537 | " " __LL "%0, %1 \n" | |
| 538 | " and %0, %2 \n" | |
| 539 | " or %0, %3 \n" | |
| 540 | " " __SC "%0, %1 \n" | |
| 541 | " .set mips0 \n" | |
| 542 | : "=&r" (temp), "+m" (*reg) | |
| 543 | : "r" (~change), "r" (val & change)); | |
| 544 | } while (unlikely(!temp)); | |
| 545 | } | |
| 546 | ||
| 22027945 JH |
547 | #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val)) |
| 548 | #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val)) | |
| c73c99b0 JH |
549 | |
| 550 | /* Cause can be modified asynchronously from hardirq hrtimer callback */ | |
| 551 | #define kvm_set_c0_guest_cause(cop0, val) \ | |
| 552 | _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val) | |
| 553 | #define kvm_clear_c0_guest_cause(cop0, val) \ | |
| 554 | _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val) | |
| 22027945 | 555 | #define kvm_change_c0_guest_cause(cop0, change, val) \ |
| c73c99b0 JH |
556 | _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \ |
| 557 | change, val) | |
| 558 | ||
| 22027945 JH |
559 | #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val)) |
| 560 | #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val)) | |
| 561 | #define kvm_change_c0_guest_ebase(cop0, change, val) \ | |
| 562 | { \ | |
| 563 | kvm_clear_c0_guest_ebase(cop0, change); \ | |
| 564 | kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \ | |
| 740765ce SL |
565 | } |
| 566 | ||
| 98e91b84 JH |
567 | /* Helpers */ |
| 568 | ||
| 569 | static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu) | |
| 570 | { | |
| 571 | return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) && | |
| 572 | vcpu->fpu_enabled; | |
| 573 | } | |
| 574 | ||
| 575 | static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu) | |
| 576 | { | |
| 577 | return kvm_mips_guest_can_have_fpu(vcpu) && | |
| 578 | kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP; | |
| 579 | } | |
| 740765ce | 580 | |
| 539cb89f JH |
581 | static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu) |
| 582 | { | |
| 583 | return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) && | |
| 584 | vcpu->msa_enabled; | |
| 585 | } | |
| 586 | ||
| 587 | static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu) | |
| 588 | { | |
| 589 | return kvm_mips_guest_can_have_msa(vcpu) && | |
| 590 | kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA; | |
| 591 | } | |
| 592 | ||
| 740765ce | 593 | struct kvm_mips_callbacks { |
| 2dca3725 JH |
594 | int (*handle_cop_unusable)(struct kvm_vcpu *vcpu); |
| 595 | int (*handle_tlb_mod)(struct kvm_vcpu *vcpu); | |
| 596 | int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu); | |
| 597 | int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu); | |
| 598 | int (*handle_addr_err_st)(struct kvm_vcpu *vcpu); | |
| 599 | int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu); | |
| 600 | int (*handle_syscall)(struct kvm_vcpu *vcpu); | |
| 601 | int (*handle_res_inst)(struct kvm_vcpu *vcpu); | |
| 602 | int (*handle_break)(struct kvm_vcpu *vcpu); | |
| 0a560427 | 603 | int (*handle_trap)(struct kvm_vcpu *vcpu); |
| 1c0cd66a | 604 | int (*handle_fpe)(struct kvm_vcpu *vcpu); |
| 98119ad5 | 605 | int (*handle_msa_disabled)(struct kvm_vcpu *vcpu); |
| 2dca3725 JH |
606 | int (*vm_init)(struct kvm *kvm); |
| 607 | int (*vcpu_init)(struct kvm_vcpu *vcpu); | |
| 608 | int (*vcpu_setup)(struct kvm_vcpu *vcpu); | |
| 609 | gpa_t (*gva_to_gpa)(gva_t gva); | |
| 610 | void (*queue_timer_int)(struct kvm_vcpu *vcpu); | |
| 611 | void (*dequeue_timer_int)(struct kvm_vcpu *vcpu); | |
| 612 | void (*queue_io_int)(struct kvm_vcpu *vcpu, | |
| 613 | struct kvm_mips_interrupt *irq); | |
| 614 | void (*dequeue_io_int)(struct kvm_vcpu *vcpu, | |
| 615 | struct kvm_mips_interrupt *irq); | |
| 616 | int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority, | |
| 617 | uint32_t cause); | |
| 618 | int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority, | |
| 619 | uint32_t cause); | |
| f8be02da JH |
620 | int (*get_one_reg)(struct kvm_vcpu *vcpu, |
| 621 | const struct kvm_one_reg *reg, s64 *v); | |
| 622 | int (*set_one_reg)(struct kvm_vcpu *vcpu, | |
| 623 | const struct kvm_one_reg *reg, s64 v); | |
| b86ecb37 JH |
624 | int (*vcpu_get_regs)(struct kvm_vcpu *vcpu); |
| 625 | int (*vcpu_set_regs)(struct kvm_vcpu *vcpu); | |
| 740765ce SL |
626 | }; |
| 627 | extern struct kvm_mips_callbacks *kvm_mips_callbacks; | |
| 628 | int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks); | |
| 629 | ||
| 630 | /* Debug: dump vcpu state */ | |
| 631 | int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu); | |
| 632 | ||
| 633 | /* Trampoline ASM routine to start running in "Guest" context */ | |
| 634 | extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu); | |
| 635 | ||
| 539cb89f | 636 | /* FPU/MSA context management */ |
| 98e91b84 JH |
637 | void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu); |
| 638 | void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu); | |
| 639 | void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu); | |
| 539cb89f JH |
640 | void __kvm_save_msa(struct kvm_vcpu_arch *vcpu); |
| 641 | void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu); | |
| 642 | void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu); | |
| 643 | void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu); | |
| 98e91b84 | 644 | void kvm_own_fpu(struct kvm_vcpu *vcpu); |
| 539cb89f | 645 | void kvm_own_msa(struct kvm_vcpu *vcpu); |
| 98e91b84 JH |
646 | void kvm_drop_fpu(struct kvm_vcpu *vcpu); |
| 647 | void kvm_lose_fpu(struct kvm_vcpu *vcpu); | |
| 648 | ||
| 740765ce SL |
649 | /* TLB handling */ |
| 650 | uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu); | |
| 651 | ||
| 652 | uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu); | |
| 653 | ||
| 654 | uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu); | |
| 655 | ||
| 656 | extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr, | |
| 657 | struct kvm_vcpu *vcpu); | |
| 658 | ||
| 659 | extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr, | |
| 660 | struct kvm_vcpu *vcpu); | |
| 661 | ||
| 662 | extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu, | |
| 663 | struct kvm_mips_tlb *tlb, | |
| 664 | unsigned long *hpa0, | |
| 665 | unsigned long *hpa1); | |
| 666 | ||
| 667 | extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause, | |
| 668 | uint32_t *opc, | |
| 669 | struct kvm_run *run, | |
| 670 | struct kvm_vcpu *vcpu); | |
| 671 | ||
| 672 | extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause, | |
| 673 | uint32_t *opc, | |
| 674 | struct kvm_run *run, | |
| 675 | struct kvm_vcpu *vcpu); | |
| 676 | ||
| 677 | extern void kvm_mips_dump_host_tlbs(void); | |
| 678 | extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu); | |
| 740765ce SL |
679 | extern void kvm_mips_flush_host_tlb(int skip_kseg0); |
| 680 | extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi); | |
| 681 | extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index); | |
| 682 | ||
| 683 | extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, | |
| 684 | unsigned long entryhi); | |
| 685 | extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr); | |
| 686 | extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu, | |
| 687 | unsigned long gva); | |
| 688 | extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, | |
| 689 | struct kvm_vcpu *vcpu); | |
| 740765ce | 690 | extern void kvm_local_flush_tlb_all(void); |
| 740765ce SL |
691 | extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu); |
| 692 | extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu); | |
| 693 | extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu); | |
| 694 | ||
| 695 | /* Emulation */ | |
| 696 | uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu); | |
| 697 | enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause); | |
| 698 | ||
| 699 | extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause, | |
| 700 | uint32_t *opc, | |
| 701 | struct kvm_run *run, | |
| 702 | struct kvm_vcpu *vcpu); | |
| 703 | ||
| 704 | extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause, | |
| 705 | uint32_t *opc, | |
| 706 | struct kvm_run *run, | |
| 707 | struct kvm_vcpu *vcpu); | |
| 708 | ||
| 709 | extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause, | |
| 710 | uint32_t *opc, | |
| 711 | struct kvm_run *run, | |
| 712 | struct kvm_vcpu *vcpu); | |
| 713 | ||
| 714 | extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause, | |
| 715 | uint32_t *opc, | |
| 716 | struct kvm_run *run, | |
| 717 | struct kvm_vcpu *vcpu); | |
| 718 | ||
| 719 | extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause, | |
| 720 | uint32_t *opc, | |
| 721 | struct kvm_run *run, | |
| 722 | struct kvm_vcpu *vcpu); | |
| 723 | ||
| 724 | extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause, | |
| 725 | uint32_t *opc, | |
| 726 | struct kvm_run *run, | |
| 727 | struct kvm_vcpu *vcpu); | |
| 728 | ||
| 729 | extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause, | |
| 730 | uint32_t *opc, | |
| 731 | struct kvm_run *run, | |
| 732 | struct kvm_vcpu *vcpu); | |
| 733 | ||
| 734 | extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause, | |
| 735 | uint32_t *opc, | |
| 736 | struct kvm_run *run, | |
| 737 | struct kvm_vcpu *vcpu); | |
| 738 | ||
| 739 | extern enum emulation_result kvm_mips_handle_ri(unsigned long cause, | |
| 740 | uint32_t *opc, | |
| 741 | struct kvm_run *run, | |
| 742 | struct kvm_vcpu *vcpu); | |
| 743 | ||
| 744 | extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause, | |
| 745 | uint32_t *opc, | |
| 746 | struct kvm_run *run, | |
| 747 | struct kvm_vcpu *vcpu); | |
| 748 | ||
| 749 | extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause, | |
| 750 | uint32_t *opc, | |
| 751 | struct kvm_run *run, | |
| 752 | struct kvm_vcpu *vcpu); | |
| 753 | ||
| 0a560427 JH |
754 | extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause, |
| 755 | uint32_t *opc, | |
| 756 | struct kvm_run *run, | |
| 757 | struct kvm_vcpu *vcpu); | |
| 758 | ||
| 1c0cd66a JH |
759 | extern enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause, |
| 760 | uint32_t *opc, | |
| 761 | struct kvm_run *run, | |
| 762 | struct kvm_vcpu *vcpu); | |
| 763 | ||
| 740765ce SL |
764 | extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu, |
| 765 | struct kvm_run *run); | |
| 766 | ||
| e30492bb JH |
767 | uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu); |
| 768 | void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count); | |
| 769 | void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare); | |
| 770 | void kvm_mips_init_count(struct kvm_vcpu *vcpu); | |
| f8239342 JH |
771 | int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl); |
| 772 | int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume); | |
| f74a8e22 | 773 | int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz); |
| e30492bb JH |
774 | void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu); |
| 775 | void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu); | |
| 776 | enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu); | |
| 740765ce SL |
777 | |
| 778 | enum emulation_result kvm_mips_check_privilege(unsigned long cause, | |
| 779 | uint32_t *opc, | |
| 780 | struct kvm_run *run, | |
| 781 | struct kvm_vcpu *vcpu); | |
| 782 | ||
| 783 | enum emulation_result kvm_mips_emulate_cache(uint32_t inst, | |
| 784 | uint32_t *opc, | |
| 785 | uint32_t cause, | |
| 786 | struct kvm_run *run, | |
| 787 | struct kvm_vcpu *vcpu); | |
| 788 | enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, | |
| 789 | uint32_t *opc, | |
| 790 | uint32_t cause, | |
| 791 | struct kvm_run *run, | |
| 792 | struct kvm_vcpu *vcpu); | |
| 793 | enum emulation_result kvm_mips_emulate_store(uint32_t inst, | |
| 794 | uint32_t cause, | |
| 795 | struct kvm_run *run, | |
| 796 | struct kvm_vcpu *vcpu); | |
| 797 | enum emulation_result kvm_mips_emulate_load(uint32_t inst, | |
| 798 | uint32_t cause, | |
| 799 | struct kvm_run *run, | |
| 800 | struct kvm_vcpu *vcpu); | |
| 801 | ||
| c771607a JH |
802 | unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu); |
| 803 | unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu); | |
| 804 | unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu); | |
| 805 | unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu); | |
| 806 | ||
| 740765ce SL |
807 | /* Dynamic binary translation */ |
| 808 | extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc, | |
| 809 | struct kvm_vcpu *vcpu); | |
| 810 | extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc, | |
| 811 | struct kvm_vcpu *vcpu); | |
| 812 | extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc, | |
| 813 | struct kvm_vcpu *vcpu); | |
| 814 | extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc, | |
| 815 | struct kvm_vcpu *vcpu); | |
| 816 | ||
| 817 | /* Misc */ | |
| d98403a5 | 818 | extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu); |
| 740765ce SL |
819 | extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm); |
| 820 | ||
| 13a34e06 | 821 | static inline void kvm_arch_hardware_disable(void) {} |
| 0865e636 RK |
822 | static inline void kvm_arch_hardware_unsetup(void) {} |
| 823 | static inline void kvm_arch_sync_events(struct kvm *kvm) {} | |
| 824 | static inline void kvm_arch_free_memslot(struct kvm *kvm, | |
| 825 | struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {} | |
| 826 | static inline void kvm_arch_memslots_updated(struct kvm *kvm) {} | |
| 827 | static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {} | |
| 828 | static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm, | |
| 829 | struct kvm_memory_slot *slot) {} | |
| 830 | static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} | |
| 831 | static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} | |
| 740765ce SL |
832 | |
| 833 | #endif /* __MIPS_KVM_HOST_H__ */ |