Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2002 MontaVista Software Inc. | |
3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | */ | |
10 | #ifndef _ASM_FPU_H | |
11 | #define _ASM_FPU_H | |
12 | ||
1da177e4 LT |
13 | #include <linux/sched.h> |
14 | #include <linux/thread_info.h> | |
1977f032 | 15 | #include <linux/bitops.h> |
1da177e4 LT |
16 | |
17 | #include <asm/mipsregs.h> | |
18 | #include <asm/cpu.h> | |
19 | #include <asm/cpu-features.h> | |
e0cc3a42 | 20 | #include <asm/fpu_emulator.h> |
0b624956 | 21 | #include <asm/hazards.h> |
1da177e4 LT |
22 | #include <asm/processor.h> |
23 | #include <asm/current.h> | |
33c771ba | 24 | #include <asm/msa.h> |
1da177e4 | 25 | |
f088fc84 RB |
26 | #ifdef CONFIG_MIPS_MT_FPAFF |
27 | #include <asm/mips_mt.h> | |
28 | #endif | |
29 | ||
1da177e4 LT |
30 | struct sigcontext; |
31 | struct sigcontext32; | |
32 | ||
1da177e4 LT |
33 | extern void _init_fpu(void); |
34 | extern void _save_fp(struct task_struct *); | |
35 | extern void _restore_fp(struct task_struct *); | |
36 | ||
597ce172 PB |
37 | /* |
38 | * This enum specifies a mode in which we want the FPU to operate, for cores | |
4227a2d4 PB |
39 | * which implement the Status.FR bit. Note that the bottom bit of the value |
40 | * purposefully matches the desired value of the Status.FR bit. | |
597ce172 PB |
41 | */ |
42 | enum fpu_mode { | |
43 | FPU_32BIT = 0, /* FR = 0 */ | |
4227a2d4 | 44 | FPU_64BIT, /* FR = 1, FRE = 0 */ |
597ce172 | 45 | FPU_AS_IS, |
4227a2d4 PB |
46 | FPU_HYBRID, /* FR = 1, FRE = 1 */ |
47 | ||
48 | #define FPU_FR_MASK 0x1 | |
597ce172 PB |
49 | }; |
50 | ||
51 | static inline int __enable_fpu(enum fpu_mode mode) | |
52 | { | |
53 | int fr; | |
54 | ||
55 | switch (mode) { | |
56 | case FPU_AS_IS: | |
57 | /* just enable the FPU in its current mode */ | |
58 | set_c0_status(ST0_CU1); | |
59 | enable_fpu_hazard(); | |
60 | return 0; | |
61 | ||
4227a2d4 PB |
62 | case FPU_HYBRID: |
63 | if (!cpu_has_fre) | |
64 | return SIGFPE; | |
65 | ||
66 | /* set FRE */ | |
d33e6fe3 | 67 | set_c0_config5(MIPS_CONF5_FRE); |
4227a2d4 PB |
68 | goto fr_common; |
69 | ||
597ce172 | 70 | case FPU_64BIT: |
6134d949 MC |
71 | #if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6) \ |
72 | || defined(CONFIG_64BIT)) | |
597ce172 PB |
73 | /* we only have a 32-bit FPU */ |
74 | return SIGFPE; | |
75 | #endif | |
76 | /* fall through */ | |
77 | case FPU_32BIT: | |
b0c34f61 RB |
78 | if (cpu_has_fre) { |
79 | /* clear FRE */ | |
d33e6fe3 | 80 | clear_c0_config5(MIPS_CONF5_FRE); |
b0c34f61 | 81 | } |
4227a2d4 | 82 | fr_common: |
597ce172 | 83 | /* set CU1 & change FR appropriately */ |
4227a2d4 | 84 | fr = (int)mode & FPU_FR_MASK; |
597ce172 PB |
85 | change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0)); |
86 | enable_fpu_hazard(); | |
87 | ||
88 | /* check FR has the desired value */ | |
89 | return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE; | |
90 | ||
91 | default: | |
92 | BUG(); | |
93 | } | |
97b8b16b AK |
94 | |
95 | return SIGFPE; | |
597ce172 | 96 | } |
1da177e4 LT |
97 | |
98 | #define __disable_fpu() \ | |
99 | do { \ | |
100 | clear_c0_status(ST0_CU1); \ | |
70342287 | 101 | disable_fpu_hazard(); \ |
1da177e4 LT |
102 | } while (0) |
103 | ||
1da177e4 LT |
104 | #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) |
105 | ||
1d74f6bc RB |
106 | static inline int __is_fpu_owner(void) |
107 | { | |
108 | return test_thread_flag(TIF_USEDFPU); | |
109 | } | |
110 | ||
1da177e4 LT |
111 | static inline int is_fpu_owner(void) |
112 | { | |
1d74f6bc | 113 | return cpu_has_fpu && __is_fpu_owner(); |
1da177e4 LT |
114 | } |
115 | ||
597ce172 | 116 | static inline int __own_fpu(void) |
1da177e4 | 117 | { |
597ce172 PB |
118 | enum fpu_mode mode; |
119 | int ret; | |
120 | ||
4227a2d4 PB |
121 | if (test_thread_flag(TIF_HYBRID_FPREGS)) |
122 | mode = FPU_HYBRID; | |
123 | else | |
124 | mode = !test_thread_flag(TIF_32BIT_FPREGS); | |
125 | ||
597ce172 PB |
126 | ret = __enable_fpu(mode); |
127 | if (ret) | |
128 | return ret; | |
129 | ||
53dc8028 | 130 | KSTK_STATUS(current) |= ST0_CU1; |
4227a2d4 | 131 | if (mode == FPU_64BIT || mode == FPU_HYBRID) |
597ce172 PB |
132 | KSTK_STATUS(current) |= ST0_FR; |
133 | else /* mode == FPU_32BIT */ | |
134 | KSTK_STATUS(current) &= ~ST0_FR; | |
135 | ||
53dc8028 | 136 | set_thread_flag(TIF_USEDFPU); |
597ce172 | 137 | return 0; |
53dc8028 AN |
138 | } |
139 | ||
597ce172 | 140 | static inline int own_fpu_inatomic(int restore) |
53dc8028 | 141 | { |
597ce172 PB |
142 | int ret = 0; |
143 | ||
53dc8028 | 144 | if (cpu_has_fpu && !__is_fpu_owner()) { |
597ce172 PB |
145 | ret = __own_fpu(); |
146 | if (restore && !ret) | |
53dc8028 | 147 | _restore_fp(current); |
1da177e4 | 148 | } |
597ce172 | 149 | return ret; |
faea6234 AN |
150 | } |
151 | ||
597ce172 | 152 | static inline int own_fpu(int restore) |
faea6234 | 153 | { |
597ce172 PB |
154 | int ret; |
155 | ||
faea6234 | 156 | preempt_disable(); |
597ce172 | 157 | ret = own_fpu_inatomic(restore); |
53dc8028 | 158 | preempt_enable(); |
597ce172 | 159 | return ret; |
1da177e4 LT |
160 | } |
161 | ||
53dc8028 | 162 | static inline void lose_fpu(int save) |
1da177e4 | 163 | { |
53dc8028 | 164 | preempt_disable(); |
33c771ba PB |
165 | if (is_msa_enabled()) { |
166 | if (save) { | |
167 | save_msa(current); | |
842dfc11 ML |
168 | current->thread.fpu.fcr31 = |
169 | read_32bit_cp1_register(CP1_STATUS); | |
33c771ba PB |
170 | } |
171 | disable_msa(); | |
172 | clear_thread_flag(TIF_USEDMSA); | |
f8483988 | 173 | __disable_fpu(); |
33c771ba | 174 | } else if (is_fpu_owner()) { |
53dc8028 AN |
175 | if (save) |
176 | _save_fp(current); | |
1da177e4 LT |
177 | __disable_fpu(); |
178 | } | |
33c771ba PB |
179 | KSTK_STATUS(current) &= ~ST0_CU1; |
180 | clear_thread_flag(TIF_USEDFPU); | |
53dc8028 | 181 | preempt_enable(); |
1da177e4 LT |
182 | } |
183 | ||
597ce172 | 184 | static inline int init_fpu(void) |
1da177e4 | 185 | { |
597ce172 PB |
186 | int ret = 0; |
187 | ||
1da177e4 | 188 | if (cpu_has_fpu) { |
b0c34f61 RB |
189 | unsigned int config5; |
190 | ||
597ce172 | 191 | ret = __own_fpu(); |
b0c34f61 RB |
192 | if (ret) |
193 | return ret; | |
4227a2d4 | 194 | |
b0c34f61 | 195 | if (!cpu_has_fre) { |
597ce172 | 196 | _init_fpu(); |
4227a2d4 | 197 | |
b0c34f61 | 198 | return 0; |
4227a2d4 | 199 | } |
b0c34f61 | 200 | |
b0c34f61 RB |
201 | /* |
202 | * Ensure FRE is clear whilst running _init_fpu, since | |
203 | * single precision FP instructions are used. If FRE | |
204 | * was set then we'll just end up initialising all 32 | |
205 | * 64b registers. | |
206 | */ | |
d33e6fe3 | 207 | config5 = clear_c0_config5(MIPS_CONF5_FRE); |
b0c34f61 RB |
208 | enable_fpu_hazard(); |
209 | ||
210 | _init_fpu(); | |
211 | ||
212 | /* Restore FRE */ | |
213 | write_c0_config5(config5); | |
214 | enable_fpu_hazard(); | |
e0cc3a42 | 215 | } else |
1da177e4 | 216 | fpu_emulator_init_fpu(); |
597ce172 | 217 | |
597ce172 | 218 | return ret; |
1da177e4 LT |
219 | } |
220 | ||
221 | static inline void save_fp(struct task_struct *tsk) | |
222 | { | |
223 | if (cpu_has_fpu) | |
224 | _save_fp(tsk); | |
225 | } | |
226 | ||
227 | static inline void restore_fp(struct task_struct *tsk) | |
228 | { | |
229 | if (cpu_has_fpu) | |
230 | _restore_fp(tsk); | |
231 | } | |
232 | ||
bbd426f5 | 233 | static inline union fpureg *get_fpu_regs(struct task_struct *tsk) |
1da177e4 | 234 | { |
e04582b7 AN |
235 | if (tsk == current) { |
236 | preempt_disable(); | |
237 | if (is_fpu_owner()) | |
1da177e4 | 238 | _save_fp(current); |
e04582b7 | 239 | preempt_enable(); |
1da177e4 LT |
240 | } |
241 | ||
eae89076 | 242 | return tsk->thread.fpu.fpr; |
1da177e4 LT |
243 | } |
244 | ||
245 | #endif /* _ASM_FPU_H */ |