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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
f039b5d3 RB |
5 | * |
6 | * Much of this is taken from binutils and GNU libc ... | |
1da177e4 LT |
7 | */ |
8 | #ifndef _ASM_ELF_H | |
9 | #define _ASM_ELF_H | |
10 | ||
ebb5e78c | 11 | #include <linux/auxvec.h> |
90cee759 PB |
12 | #include <linux/fs.h> |
13 | #include <uapi/linux/elf.h> | |
1da177e4 | 14 | |
9b26616c MR |
15 | #include <asm/current.h> |
16 | ||
1da177e4 LT |
17 | /* ELF header e_flags defines. */ |
18 | /* MIPS architecture level. */ | |
70342287 RB |
19 | #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ |
20 | #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ | |
21 | #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ | |
22 | #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ | |
23 | #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ | |
24 | #define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ | |
25 | #define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ | |
97fb5de1 RB |
26 | #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32 R2 code. */ |
27 | #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64 R2 code. */ | |
1da177e4 LT |
28 | |
29 | /* The ABI of a file. */ | |
30 | #define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */ | |
31 | #define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */ | |
32 | ||
33 | #define PT_MIPS_REGINFO 0x70000000 | |
34 | #define PT_MIPS_RTPROC 0x70000001 | |
35 | #define PT_MIPS_OPTIONS 0x70000002 | |
6cd96229 | 36 | #define PT_MIPS_ABIFLAGS 0x70000003 |
1da177e4 LT |
37 | |
38 | /* Flags in the e_flags field of the header */ | |
39 | #define EF_MIPS_NOREORDER 0x00000001 | |
40 | #define EF_MIPS_PIC 0x00000002 | |
41 | #define EF_MIPS_CPIC 0x00000004 | |
42 | #define EF_MIPS_ABI2 0x00000020 | |
43 | #define EF_MIPS_OPTIONS_FIRST 0x00000080 | |
44 | #define EF_MIPS_32BITMODE 0x00000100 | |
597ce172 | 45 | #define EF_MIPS_FP64 0x00000200 |
2b5e869e | 46 | #define EF_MIPS_NAN2008 0x00000400 |
1da177e4 LT |
47 | #define EF_MIPS_ABI 0x0000f000 |
48 | #define EF_MIPS_ARCH 0xf0000000 | |
49 | ||
50 | #define DT_MIPS_RLD_VERSION 0x70000001 | |
51 | #define DT_MIPS_TIME_STAMP 0x70000002 | |
52 | #define DT_MIPS_ICHECKSUM 0x70000003 | |
53 | #define DT_MIPS_IVERSION 0x70000004 | |
54 | #define DT_MIPS_FLAGS 0x70000005 | |
55 | #define RHF_NONE 0x00000000 | |
56 | #define RHF_HARDWAY 0x00000001 | |
57 | #define RHF_NOTPOT 0x00000002 | |
58 | #define RHF_SGI_ONLY 0x00000010 | |
59 | #define DT_MIPS_BASE_ADDRESS 0x70000006 | |
60 | #define DT_MIPS_CONFLICT 0x70000008 | |
61 | #define DT_MIPS_LIBLIST 0x70000009 | |
62 | #define DT_MIPS_LOCAL_GOTNO 0x7000000a | |
63 | #define DT_MIPS_CONFLICTNO 0x7000000b | |
64 | #define DT_MIPS_LIBLISTNO 0x70000010 | |
65 | #define DT_MIPS_SYMTABNO 0x70000011 | |
66 | #define DT_MIPS_UNREFEXTNO 0x70000012 | |
67 | #define DT_MIPS_GOTSYM 0x70000013 | |
68 | #define DT_MIPS_HIPAGENO 0x70000014 | |
69 | #define DT_MIPS_RLD_MAP 0x70000016 | |
70 | ||
71 | #define R_MIPS_NONE 0 | |
72 | #define R_MIPS_16 1 | |
73 | #define R_MIPS_32 2 | |
74 | #define R_MIPS_REL32 3 | |
75 | #define R_MIPS_26 4 | |
76 | #define R_MIPS_HI16 5 | |
77 | #define R_MIPS_LO16 6 | |
78 | #define R_MIPS_GPREL16 7 | |
79 | #define R_MIPS_LITERAL 8 | |
80 | #define R_MIPS_GOT16 9 | |
81 | #define R_MIPS_PC16 10 | |
82 | #define R_MIPS_CALL16 11 | |
83 | #define R_MIPS_GPREL32 12 | |
84 | /* The remaining relocs are defined on Irix, although they are not | |
70342287 | 85 | in the MIPS ELF ABI. */ |
1da177e4 LT |
86 | #define R_MIPS_UNUSED1 13 |
87 | #define R_MIPS_UNUSED2 14 | |
88 | #define R_MIPS_UNUSED3 15 | |
89 | #define R_MIPS_SHIFT5 16 | |
90 | #define R_MIPS_SHIFT6 17 | |
91 | #define R_MIPS_64 18 | |
92 | #define R_MIPS_GOT_DISP 19 | |
93 | #define R_MIPS_GOT_PAGE 20 | |
94 | #define R_MIPS_GOT_OFST 21 | |
95 | /* | |
96 | * The following two relocation types are specified in the MIPS ABI | |
97 | * conformance guide version 1.2 but not yet in the psABI. | |
98 | */ | |
99 | #define R_MIPS_GOTHI16 22 | |
100 | #define R_MIPS_GOTLO16 23 | |
101 | #define R_MIPS_SUB 24 | |
102 | #define R_MIPS_INSERT_A 25 | |
103 | #define R_MIPS_INSERT_B 26 | |
104 | #define R_MIPS_DELETE 27 | |
105 | #define R_MIPS_HIGHER 28 | |
106 | #define R_MIPS_HIGHEST 29 | |
107 | /* | |
108 | * The following two relocation types are specified in the MIPS ABI | |
109 | * conformance guide version 1.2 but not yet in the psABI. | |
110 | */ | |
111 | #define R_MIPS_CALLHI16 30 | |
112 | #define R_MIPS_CALLLO16 31 | |
113 | /* | |
114 | * This range is reserved for vendor specific relocations. | |
115 | */ | |
116 | #define R_MIPS_LOVENDOR 100 | |
117 | #define R_MIPS_HIVENDOR 127 | |
118 | ||
f039b5d3 RB |
119 | #define SHN_MIPS_ACCOMON 0xff00 /* Allocated common symbols */ |
120 | #define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ | |
121 | #define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ | |
122 | #define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ | |
123 | #define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ | |
1da177e4 LT |
124 | |
125 | #define SHT_MIPS_LIST 0x70000000 | |
126 | #define SHT_MIPS_CONFLICT 0x70000002 | |
127 | #define SHT_MIPS_GPTAB 0x70000003 | |
128 | #define SHT_MIPS_UCODE 0x70000004 | |
84ada9f8 RB |
129 | #define SHT_MIPS_DEBUG 0x70000005 |
130 | #define SHT_MIPS_REGINFO 0x70000006 | |
131 | #define SHT_MIPS_PACKAGE 0x70000007 | |
132 | #define SHT_MIPS_PACKSYM 0x70000008 | |
133 | #define SHT_MIPS_RELD 0x70000009 | |
134 | #define SHT_MIPS_IFACE 0x7000000b | |
135 | #define SHT_MIPS_CONTENT 0x7000000c | |
136 | #define SHT_MIPS_OPTIONS 0x7000000d | |
137 | #define SHT_MIPS_SHDR 0x70000010 | |
138 | #define SHT_MIPS_FDESC 0x70000011 | |
139 | #define SHT_MIPS_EXTSYM 0x70000012 | |
140 | #define SHT_MIPS_DENSE 0x70000013 | |
141 | #define SHT_MIPS_PDESC 0x70000014 | |
142 | #define SHT_MIPS_LOCSYM 0x70000015 | |
143 | #define SHT_MIPS_AUXSYM 0x70000016 | |
144 | #define SHT_MIPS_OPTSYM 0x70000017 | |
145 | #define SHT_MIPS_LOCSTR 0x70000018 | |
146 | #define SHT_MIPS_LINE 0x70000019 | |
147 | #define SHT_MIPS_RFDESC 0x7000001a | |
148 | #define SHT_MIPS_DELTASYM 0x7000001b | |
149 | #define SHT_MIPS_DELTAINST 0x7000001c | |
150 | #define SHT_MIPS_DELTACLASS 0x7000001d | |
151 | #define SHT_MIPS_DWARF 0x7000001e | |
152 | #define SHT_MIPS_DELTADECL 0x7000001f | |
153 | #define SHT_MIPS_SYMBOL_LIB 0x70000020 | |
154 | #define SHT_MIPS_EVENTS 0x70000021 | |
155 | #define SHT_MIPS_TRANSLATE 0x70000022 | |
156 | #define SHT_MIPS_PIXIE 0x70000023 | |
157 | #define SHT_MIPS_XLATE 0x70000024 | |
158 | #define SHT_MIPS_XLATE_DEBUG 0x70000025 | |
159 | #define SHT_MIPS_WHIRL 0x70000026 | |
160 | #define SHT_MIPS_EH_REGION 0x70000027 | |
161 | #define SHT_MIPS_XLATE_OLD 0x70000028 | |
162 | #define SHT_MIPS_PDR_EXCEPTION 0x70000029 | |
1da177e4 | 163 | |
84ada9f8 RB |
164 | #define SHF_MIPS_GPREL 0x10000000 |
165 | #define SHF_MIPS_MERGE 0x20000000 | |
166 | #define SHF_MIPS_ADDR 0x40000000 | |
167 | #define SHF_MIPS_STRING 0x80000000 | |
168 | #define SHF_MIPS_NOSTRIP 0x08000000 | |
169 | #define SHF_MIPS_LOCAL 0x04000000 | |
170 | #define SHF_MIPS_NAMES 0x02000000 | |
171 | #define SHF_MIPS_NODUPES 0x01000000 | |
1da177e4 LT |
172 | |
173 | #ifndef ELF_ARCH | |
174 | /* ELF register definitions */ | |
175 | #define ELF_NGREG 45 | |
176 | #define ELF_NFPREG 33 | |
177 | ||
178 | typedef unsigned long elf_greg_t; | |
179 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | |
180 | ||
181 | typedef double elf_fpreg_t; | |
182 | typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; | |
183 | ||
6cd96229 PB |
184 | struct mips_elf_abiflags_v0 { |
185 | uint16_t version; /* Version of flags structure */ | |
186 | uint8_t isa_level; /* The level of the ISA: 1-5, 32, 64 */ | |
187 | uint8_t isa_rev; /* The revision of ISA: 0 for MIPS V and below, | |
188 | 1-n otherwise */ | |
189 | uint8_t gpr_size; /* The size of general purpose registers */ | |
190 | uint8_t cpr1_size; /* The size of co-processor 1 registers */ | |
191 | uint8_t cpr2_size; /* The size of co-processor 2 registers */ | |
192 | uint8_t fp_abi; /* The floating-point ABI */ | |
193 | uint32_t isa_ext; /* Mask of processor-specific extensions */ | |
194 | uint32_t ases; /* Mask of ASEs used */ | |
195 | uint32_t flags1; /* Mask of general flags */ | |
196 | uint32_t flags2; | |
197 | }; | |
198 | ||
199 | #define MIPS_ABI_FP_ANY 0 /* FP ABI doesn't matter */ | |
200 | #define MIPS_ABI_FP_DOUBLE 1 /* -mdouble-float */ | |
201 | #define MIPS_ABI_FP_SINGLE 2 /* -msingle-float */ | |
202 | #define MIPS_ABI_FP_SOFT 3 /* -msoft-float */ | |
203 | #define MIPS_ABI_FP_OLD_64 4 /* -mips32r2 -mfp64 */ | |
204 | #define MIPS_ABI_FP_XX 5 /* -mfpxx */ | |
205 | #define MIPS_ABI_FP_64 6 /* -mips32r2 -mfp64 */ | |
206 | #define MIPS_ABI_FP_64A 7 /* -mips32r2 -mfp64 -mno-odd-spreg */ | |
207 | ||
875d43e7 | 208 | #ifdef CONFIG_32BIT |
1da177e4 | 209 | |
597ce172 PB |
210 | /* |
211 | * In order to be sure that we don't attempt to execute an O32 binary which | |
212 | * requires 64 bit FP (FR=1) on a system which does not support it we refuse | |
213 | * to execute any binary which has bits specified by the following macro set | |
214 | * in its ELF header flags. | |
215 | */ | |
216 | #ifdef CONFIG_MIPS_O32_FP64_SUPPORT | |
217 | # define __MIPS_O32_FP64_MUST_BE_ZERO 0 | |
218 | #else | |
219 | # define __MIPS_O32_FP64_MUST_BE_ZERO EF_MIPS_FP64 | |
220 | #endif | |
221 | ||
1da177e4 LT |
222 | /* |
223 | * This is used to ensure we don't load something for the wrong architecture. | |
224 | */ | |
225 | #define elf_check_arch(hdr) \ | |
226 | ({ \ | |
227 | int __res = 1; \ | |
228 | struct elfhdr *__h = (hdr); \ | |
229 | \ | |
f4d3d504 | 230 | if (!mips_elf_check_machine(__h)) \ |
1da177e4 LT |
231 | __res = 0; \ |
232 | if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ | |
233 | __res = 0; \ | |
234 | if ((__h->e_flags & EF_MIPS_ABI2) != 0) \ | |
235 | __res = 0; \ | |
236 | if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ | |
237 | ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ | |
597ce172 PB |
238 | __res = 0; \ |
239 | if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO) \ | |
1da177e4 LT |
240 | __res = 0; \ |
241 | \ | |
242 | __res; \ | |
243 | }) | |
244 | ||
245 | /* | |
246 | * These are used to set parameters in the core dumps. | |
247 | */ | |
248 | #define ELF_CLASS ELFCLASS32 | |
249 | ||
875d43e7 | 250 | #endif /* CONFIG_32BIT */ |
1da177e4 | 251 | |
875d43e7 | 252 | #ifdef CONFIG_64BIT |
1da177e4 LT |
253 | /* |
254 | * This is used to ensure we don't load something for the wrong architecture. | |
255 | */ | |
256 | #define elf_check_arch(hdr) \ | |
257 | ({ \ | |
258 | int __res = 1; \ | |
259 | struct elfhdr *__h = (hdr); \ | |
260 | \ | |
f4d3d504 | 261 | if (!mips_elf_check_machine(__h)) \ |
1da177e4 | 262 | __res = 0; \ |
70342287 | 263 | if (__h->e_ident[EI_CLASS] != ELFCLASS64) \ |
1da177e4 LT |
264 | __res = 0; \ |
265 | \ | |
266 | __res; \ | |
267 | }) | |
268 | ||
269 | /* | |
270 | * These are used to set parameters in the core dumps. | |
271 | */ | |
272 | #define ELF_CLASS ELFCLASS64 | |
273 | ||
875d43e7 | 274 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
275 | |
276 | /* | |
277 | * These are used to set parameters in the core dumps. | |
278 | */ | |
279 | #ifdef __MIPSEB__ | |
280 | #define ELF_DATA ELFDATA2MSB | |
08d9d1c4 | 281 | #elif defined(__MIPSEL__) |
1da177e4 LT |
282 | #define ELF_DATA ELFDATA2LSB |
283 | #endif | |
284 | #define ELF_ARCH EM_MIPS | |
285 | ||
286 | #endif /* !defined(ELF_ARCH) */ | |
287 | ||
f4d3d504 DW |
288 | #define mips_elf_check_machine(x) ((x)->e_machine == EM_MIPS) |
289 | ||
290 | #define vmcore_elf32_check_arch mips_elf_check_machine | |
291 | #define vmcore_elf64_check_arch mips_elf_check_machine | |
292 | ||
e50c0a8f RB |
293 | struct mips_abi; |
294 | ||
295 | extern struct mips_abi mips_abi; | |
296 | extern struct mips_abi mips_abi_32; | |
297 | extern struct mips_abi mips_abi_n32; | |
298 | ||
875d43e7 | 299 | #ifdef CONFIG_32BIT |
1da177e4 | 300 | |
90cee759 | 301 | #define SET_PERSONALITY2(ex, state) \ |
e50c0a8f | 302 | do { \ |
1c0d52b9 DD |
303 | if (personality(current->personality) != PER_LINUX) \ |
304 | set_personality(PER_LINUX); \ | |
e50c0a8f | 305 | \ |
48f8eaee MC |
306 | clear_thread_flag(TIF_HYBRID_FPREGS); \ |
307 | set_thread_flag(TIF_32BIT_FPREGS); \ | |
308 | \ | |
90cee759 PB |
309 | mips_set_personality_fp(state); \ |
310 | \ | |
e50c0a8f | 311 | current->thread.abi = &mips_abi; \ |
9b26616c | 312 | \ |
2b5e869e | 313 | mips_set_personality_nan(state); \ |
1da177e4 LT |
314 | } while (0) |
315 | ||
875d43e7 | 316 | #endif /* CONFIG_32BIT */ |
1da177e4 | 317 | |
875d43e7 | 318 | #ifdef CONFIG_64BIT |
1da177e4 | 319 | |
e50c0a8f RB |
320 | #ifdef CONFIG_MIPS32_N32 |
321 | #define __SET_PERSONALITY32_N32() \ | |
322 | do { \ | |
293c5bd1 | 323 | set_thread_flag(TIF_32BIT_ADDR); \ |
e50c0a8f RB |
324 | current->thread.abi = &mips_abi_n32; \ |
325 | } while (0) | |
326 | #else | |
327 | #define __SET_PERSONALITY32_N32() \ | |
328 | do { } while (0) | |
329 | #endif | |
330 | ||
331 | #ifdef CONFIG_MIPS32_O32 | |
90cee759 | 332 | #define __SET_PERSONALITY32_O32(ex, state) \ |
e50c0a8f | 333 | do { \ |
293c5bd1 RB |
334 | set_thread_flag(TIF_32BIT_REGS); \ |
335 | set_thread_flag(TIF_32BIT_ADDR); \ | |
48f8eaee MC |
336 | clear_thread_flag(TIF_HYBRID_FPREGS); \ |
337 | set_thread_flag(TIF_32BIT_FPREGS); \ | |
597ce172 | 338 | \ |
90cee759 | 339 | mips_set_personality_fp(state); \ |
597ce172 | 340 | \ |
e50c0a8f RB |
341 | current->thread.abi = &mips_abi_32; \ |
342 | } while (0) | |
343 | #else | |
90cee759 | 344 | #define __SET_PERSONALITY32_O32(ex, state) \ |
e50c0a8f RB |
345 | do { } while (0) |
346 | #endif | |
347 | ||
348 | #ifdef CONFIG_MIPS32_COMPAT | |
90cee759 | 349 | #define __SET_PERSONALITY32(ex, state) \ |
e50c0a8f RB |
350 | do { \ |
351 | if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \ | |
352 | ((ex).e_flags & EF_MIPS_ABI) == 0) \ | |
353 | __SET_PERSONALITY32_N32(); \ | |
354 | else \ | |
90cee759 | 355 | __SET_PERSONALITY32_O32(ex, state); \ |
e50c0a8f RB |
356 | } while (0) |
357 | #else | |
90cee759 | 358 | #define __SET_PERSONALITY32(ex, state) do { } while (0) |
e50c0a8f RB |
359 | #endif |
360 | ||
90cee759 | 361 | #define SET_PERSONALITY2(ex, state) \ |
e50c0a8f | 362 | do { \ |
1c0d52b9 DD |
363 | unsigned int p; \ |
364 | \ | |
293c5bd1 | 365 | clear_thread_flag(TIF_32BIT_REGS); \ |
597ce172 | 366 | clear_thread_flag(TIF_32BIT_FPREGS); \ |
4227a2d4 | 367 | clear_thread_flag(TIF_HYBRID_FPREGS); \ |
293c5bd1 RB |
368 | clear_thread_flag(TIF_32BIT_ADDR); \ |
369 | \ | |
e50c0a8f | 370 | if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ |
90cee759 | 371 | __SET_PERSONALITY32(ex, state); \ |
293c5bd1 | 372 | else \ |
e50c0a8f | 373 | current->thread.abi = &mips_abi; \ |
e50c0a8f | 374 | \ |
2b5e869e | 375 | mips_set_personality_nan(state); \ |
9b26616c | 376 | \ |
1c0d52b9 DD |
377 | p = personality(current->personality); \ |
378 | if (p != PER_LINUX32 && p != PER_LINUX) \ | |
e50c0a8f | 379 | set_personality(PER_LINUX); \ |
1da177e4 LT |
380 | } while (0) |
381 | ||
875d43e7 | 382 | #endif /* CONFIG_64BIT */ |
1da177e4 | 383 | |
6a9c001b | 384 | #define CORE_DUMP_USE_REGSET |
1da177e4 LT |
385 | #define ELF_EXEC_PAGESIZE PAGE_SIZE |
386 | ||
387 | /* This yields a mask that user programs can use to figure out what | |
388 | instruction set this cpu supports. This could be done in userspace, | |
389 | but it's not easy, and we've already done it here. */ | |
390 | ||
e14f1db7 PB |
391 | #define ELF_HWCAP (elf_hwcap) |
392 | extern unsigned int elf_hwcap; | |
393 | #include <asm/hwcap.h> | |
1da177e4 | 394 | |
874fd3b5 DD |
395 | /* |
396 | * This yields a string that ld.so will use to load implementation | |
70342287 | 397 | * specific libraries for optimization. This is more specific in |
874fd3b5 DD |
398 | * intent than poking at uname or /proc/cpuinfo. |
399 | */ | |
1da177e4 | 400 | |
874fd3b5 DD |
401 | #define ELF_PLATFORM __elf_platform |
402 | extern const char *__elf_platform; | |
1da177e4 LT |
403 | |
404 | /* | |
405 | * See comments in asm-alpha/elf.h, this is the same thing | |
406 | * on the MIPS. | |
407 | */ | |
408 | #define ELF_PLAT_INIT(_r, load_addr) do { \ | |
409 | _r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0; \ | |
410 | _r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0; \ | |
411 | _r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0; \ | |
412 | _r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0; \ | |
413 | _r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0; \ | |
414 | _r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0; \ | |
415 | _r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0; \ | |
416 | _r->regs[30] = _r->regs[31] = 0; \ | |
417 | } while (0) | |
418 | ||
419 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical | |
420 | use of this is to invoke "./ld.so someprog" to test out a new version of | |
70342287 RB |
421 | the loader. We need to make sure that it is out of the way of the program |
422 | that it will "exec", and that there is sufficient room for the brk. */ | |
1da177e4 LT |
423 | |
424 | #ifndef ELF_ET_DYN_BASE | |
70342287 | 425 | #define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) |
1da177e4 LT |
426 | #endif |
427 | ||
ebb5e78c AS |
428 | #define ARCH_DLINFO \ |
429 | do { \ | |
430 | NEW_AUX_ENT(AT_SYSINFO_EHDR, \ | |
431 | (unsigned long)current->mm->context.vdso); \ | |
432 | } while (0) | |
433 | ||
c52d0d30 DD |
434 | #define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1 |
435 | struct linux_binprm; | |
436 | extern int arch_setup_additional_pages(struct linux_binprm *bprm, | |
437 | int uses_interp); | |
652b14aa | 438 | |
90cee759 | 439 | struct arch_elf_state { |
2b5e869e | 440 | int nan_2008; |
90cee759 PB |
441 | int fp_abi; |
442 | int interp_fp_abi; | |
46490b57 | 443 | int overall_fp_mode; |
90cee759 PB |
444 | }; |
445 | ||
46490b57 MC |
446 | #define MIPS_ABI_FP_UNKNOWN (-1) /* Unknown FP ABI (kernel internal) */ |
447 | ||
90cee759 | 448 | #define INIT_ARCH_ELF_STATE { \ |
2b5e869e | 449 | .nan_2008 = -1, \ |
46490b57 MC |
450 | .fp_abi = MIPS_ABI_FP_UNKNOWN, \ |
451 | .interp_fp_abi = MIPS_ABI_FP_UNKNOWN, \ | |
452 | .overall_fp_mode = -1, \ | |
90cee759 PB |
453 | } |
454 | ||
503943e0 MR |
455 | /* Whether to accept legacy-NaN and 2008-NaN user binaries. */ |
456 | extern bool mips_use_nan_legacy; | |
457 | extern bool mips_use_nan_2008; | |
458 | ||
90cee759 PB |
459 | extern int arch_elf_pt_proc(void *ehdr, void *phdr, struct file *elf, |
460 | bool is_interp, struct arch_elf_state *state); | |
461 | ||
eb4bc076 | 462 | extern int arch_check_elf(void *ehdr, bool has_interpreter, void *interp_ehdr, |
90cee759 PB |
463 | struct arch_elf_state *state); |
464 | ||
2b5e869e | 465 | extern void mips_set_personality_nan(struct arch_elf_state *state); |
90cee759 PB |
466 | extern void mips_set_personality_fp(struct arch_elf_state *state); |
467 | ||
1da177e4 | 468 | #endif /* _ASM_ELF_H */ |