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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
f039b5d3 RB |
5 | * |
6 | * Much of this is taken from binutils and GNU libc ... | |
1da177e4 LT |
7 | */ |
8 | #ifndef _ASM_ELF_H | |
9 | #define _ASM_ELF_H | |
10 | ||
1da177e4 LT |
11 | |
12 | /* ELF header e_flags defines. */ | |
13 | /* MIPS architecture level. */ | |
70342287 RB |
14 | #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ |
15 | #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ | |
16 | #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ | |
17 | #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ | |
18 | #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ | |
19 | #define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ | |
20 | #define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ | |
97fb5de1 RB |
21 | #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32 R2 code. */ |
22 | #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64 R2 code. */ | |
1da177e4 LT |
23 | |
24 | /* The ABI of a file. */ | |
25 | #define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */ | |
26 | #define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */ | |
27 | ||
28 | #define PT_MIPS_REGINFO 0x70000000 | |
29 | #define PT_MIPS_RTPROC 0x70000001 | |
30 | #define PT_MIPS_OPTIONS 0x70000002 | |
31 | ||
32 | /* Flags in the e_flags field of the header */ | |
33 | #define EF_MIPS_NOREORDER 0x00000001 | |
34 | #define EF_MIPS_PIC 0x00000002 | |
35 | #define EF_MIPS_CPIC 0x00000004 | |
36 | #define EF_MIPS_ABI2 0x00000020 | |
37 | #define EF_MIPS_OPTIONS_FIRST 0x00000080 | |
38 | #define EF_MIPS_32BITMODE 0x00000100 | |
597ce172 | 39 | #define EF_MIPS_FP64 0x00000200 |
1da177e4 LT |
40 | #define EF_MIPS_ABI 0x0000f000 |
41 | #define EF_MIPS_ARCH 0xf0000000 | |
42 | ||
43 | #define DT_MIPS_RLD_VERSION 0x70000001 | |
44 | #define DT_MIPS_TIME_STAMP 0x70000002 | |
45 | #define DT_MIPS_ICHECKSUM 0x70000003 | |
46 | #define DT_MIPS_IVERSION 0x70000004 | |
47 | #define DT_MIPS_FLAGS 0x70000005 | |
48 | #define RHF_NONE 0x00000000 | |
49 | #define RHF_HARDWAY 0x00000001 | |
50 | #define RHF_NOTPOT 0x00000002 | |
51 | #define RHF_SGI_ONLY 0x00000010 | |
52 | #define DT_MIPS_BASE_ADDRESS 0x70000006 | |
53 | #define DT_MIPS_CONFLICT 0x70000008 | |
54 | #define DT_MIPS_LIBLIST 0x70000009 | |
55 | #define DT_MIPS_LOCAL_GOTNO 0x7000000a | |
56 | #define DT_MIPS_CONFLICTNO 0x7000000b | |
57 | #define DT_MIPS_LIBLISTNO 0x70000010 | |
58 | #define DT_MIPS_SYMTABNO 0x70000011 | |
59 | #define DT_MIPS_UNREFEXTNO 0x70000012 | |
60 | #define DT_MIPS_GOTSYM 0x70000013 | |
61 | #define DT_MIPS_HIPAGENO 0x70000014 | |
62 | #define DT_MIPS_RLD_MAP 0x70000016 | |
63 | ||
64 | #define R_MIPS_NONE 0 | |
65 | #define R_MIPS_16 1 | |
66 | #define R_MIPS_32 2 | |
67 | #define R_MIPS_REL32 3 | |
68 | #define R_MIPS_26 4 | |
69 | #define R_MIPS_HI16 5 | |
70 | #define R_MIPS_LO16 6 | |
71 | #define R_MIPS_GPREL16 7 | |
72 | #define R_MIPS_LITERAL 8 | |
73 | #define R_MIPS_GOT16 9 | |
74 | #define R_MIPS_PC16 10 | |
75 | #define R_MIPS_CALL16 11 | |
76 | #define R_MIPS_GPREL32 12 | |
77 | /* The remaining relocs are defined on Irix, although they are not | |
70342287 | 78 | in the MIPS ELF ABI. */ |
1da177e4 LT |
79 | #define R_MIPS_UNUSED1 13 |
80 | #define R_MIPS_UNUSED2 14 | |
81 | #define R_MIPS_UNUSED3 15 | |
82 | #define R_MIPS_SHIFT5 16 | |
83 | #define R_MIPS_SHIFT6 17 | |
84 | #define R_MIPS_64 18 | |
85 | #define R_MIPS_GOT_DISP 19 | |
86 | #define R_MIPS_GOT_PAGE 20 | |
87 | #define R_MIPS_GOT_OFST 21 | |
88 | /* | |
89 | * The following two relocation types are specified in the MIPS ABI | |
90 | * conformance guide version 1.2 but not yet in the psABI. | |
91 | */ | |
92 | #define R_MIPS_GOTHI16 22 | |
93 | #define R_MIPS_GOTLO16 23 | |
94 | #define R_MIPS_SUB 24 | |
95 | #define R_MIPS_INSERT_A 25 | |
96 | #define R_MIPS_INSERT_B 26 | |
97 | #define R_MIPS_DELETE 27 | |
98 | #define R_MIPS_HIGHER 28 | |
99 | #define R_MIPS_HIGHEST 29 | |
100 | /* | |
101 | * The following two relocation types are specified in the MIPS ABI | |
102 | * conformance guide version 1.2 but not yet in the psABI. | |
103 | */ | |
104 | #define R_MIPS_CALLHI16 30 | |
105 | #define R_MIPS_CALLLO16 31 | |
106 | /* | |
107 | * This range is reserved for vendor specific relocations. | |
108 | */ | |
109 | #define R_MIPS_LOVENDOR 100 | |
110 | #define R_MIPS_HIVENDOR 127 | |
111 | ||
f039b5d3 RB |
112 | #define SHN_MIPS_ACCOMON 0xff00 /* Allocated common symbols */ |
113 | #define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ | |
114 | #define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ | |
115 | #define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ | |
116 | #define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ | |
1da177e4 LT |
117 | |
118 | #define SHT_MIPS_LIST 0x70000000 | |
119 | #define SHT_MIPS_CONFLICT 0x70000002 | |
120 | #define SHT_MIPS_GPTAB 0x70000003 | |
121 | #define SHT_MIPS_UCODE 0x70000004 | |
84ada9f8 RB |
122 | #define SHT_MIPS_DEBUG 0x70000005 |
123 | #define SHT_MIPS_REGINFO 0x70000006 | |
124 | #define SHT_MIPS_PACKAGE 0x70000007 | |
125 | #define SHT_MIPS_PACKSYM 0x70000008 | |
126 | #define SHT_MIPS_RELD 0x70000009 | |
127 | #define SHT_MIPS_IFACE 0x7000000b | |
128 | #define SHT_MIPS_CONTENT 0x7000000c | |
129 | #define SHT_MIPS_OPTIONS 0x7000000d | |
130 | #define SHT_MIPS_SHDR 0x70000010 | |
131 | #define SHT_MIPS_FDESC 0x70000011 | |
132 | #define SHT_MIPS_EXTSYM 0x70000012 | |
133 | #define SHT_MIPS_DENSE 0x70000013 | |
134 | #define SHT_MIPS_PDESC 0x70000014 | |
135 | #define SHT_MIPS_LOCSYM 0x70000015 | |
136 | #define SHT_MIPS_AUXSYM 0x70000016 | |
137 | #define SHT_MIPS_OPTSYM 0x70000017 | |
138 | #define SHT_MIPS_LOCSTR 0x70000018 | |
139 | #define SHT_MIPS_LINE 0x70000019 | |
140 | #define SHT_MIPS_RFDESC 0x7000001a | |
141 | #define SHT_MIPS_DELTASYM 0x7000001b | |
142 | #define SHT_MIPS_DELTAINST 0x7000001c | |
143 | #define SHT_MIPS_DELTACLASS 0x7000001d | |
144 | #define SHT_MIPS_DWARF 0x7000001e | |
145 | #define SHT_MIPS_DELTADECL 0x7000001f | |
146 | #define SHT_MIPS_SYMBOL_LIB 0x70000020 | |
147 | #define SHT_MIPS_EVENTS 0x70000021 | |
148 | #define SHT_MIPS_TRANSLATE 0x70000022 | |
149 | #define SHT_MIPS_PIXIE 0x70000023 | |
150 | #define SHT_MIPS_XLATE 0x70000024 | |
151 | #define SHT_MIPS_XLATE_DEBUG 0x70000025 | |
152 | #define SHT_MIPS_WHIRL 0x70000026 | |
153 | #define SHT_MIPS_EH_REGION 0x70000027 | |
154 | #define SHT_MIPS_XLATE_OLD 0x70000028 | |
155 | #define SHT_MIPS_PDR_EXCEPTION 0x70000029 | |
1da177e4 | 156 | |
84ada9f8 RB |
157 | #define SHF_MIPS_GPREL 0x10000000 |
158 | #define SHF_MIPS_MERGE 0x20000000 | |
159 | #define SHF_MIPS_ADDR 0x40000000 | |
160 | #define SHF_MIPS_STRING 0x80000000 | |
161 | #define SHF_MIPS_NOSTRIP 0x08000000 | |
162 | #define SHF_MIPS_LOCAL 0x04000000 | |
163 | #define SHF_MIPS_NAMES 0x02000000 | |
164 | #define SHF_MIPS_NODUPES 0x01000000 | |
1da177e4 LT |
165 | |
166 | #ifndef ELF_ARCH | |
167 | /* ELF register definitions */ | |
168 | #define ELF_NGREG 45 | |
169 | #define ELF_NFPREG 33 | |
170 | ||
171 | typedef unsigned long elf_greg_t; | |
172 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | |
173 | ||
174 | typedef double elf_fpreg_t; | |
175 | typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; | |
176 | ||
875d43e7 | 177 | #ifdef CONFIG_32BIT |
1da177e4 | 178 | |
597ce172 PB |
179 | /* |
180 | * In order to be sure that we don't attempt to execute an O32 binary which | |
181 | * requires 64 bit FP (FR=1) on a system which does not support it we refuse | |
182 | * to execute any binary which has bits specified by the following macro set | |
183 | * in its ELF header flags. | |
184 | */ | |
185 | #ifdef CONFIG_MIPS_O32_FP64_SUPPORT | |
186 | # define __MIPS_O32_FP64_MUST_BE_ZERO 0 | |
187 | #else | |
188 | # define __MIPS_O32_FP64_MUST_BE_ZERO EF_MIPS_FP64 | |
189 | #endif | |
190 | ||
1da177e4 LT |
191 | /* |
192 | * This is used to ensure we don't load something for the wrong architecture. | |
193 | */ | |
194 | #define elf_check_arch(hdr) \ | |
195 | ({ \ | |
196 | int __res = 1; \ | |
197 | struct elfhdr *__h = (hdr); \ | |
198 | \ | |
199 | if (__h->e_machine != EM_MIPS) \ | |
200 | __res = 0; \ | |
201 | if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ | |
202 | __res = 0; \ | |
203 | if ((__h->e_flags & EF_MIPS_ABI2) != 0) \ | |
204 | __res = 0; \ | |
205 | if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ | |
206 | ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ | |
597ce172 PB |
207 | __res = 0; \ |
208 | if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO) \ | |
1da177e4 LT |
209 | __res = 0; \ |
210 | \ | |
211 | __res; \ | |
212 | }) | |
213 | ||
214 | /* | |
215 | * These are used to set parameters in the core dumps. | |
216 | */ | |
217 | #define ELF_CLASS ELFCLASS32 | |
218 | ||
875d43e7 | 219 | #endif /* CONFIG_32BIT */ |
1da177e4 | 220 | |
875d43e7 | 221 | #ifdef CONFIG_64BIT |
1da177e4 LT |
222 | /* |
223 | * This is used to ensure we don't load something for the wrong architecture. | |
224 | */ | |
225 | #define elf_check_arch(hdr) \ | |
226 | ({ \ | |
227 | int __res = 1; \ | |
228 | struct elfhdr *__h = (hdr); \ | |
229 | \ | |
230 | if (__h->e_machine != EM_MIPS) \ | |
231 | __res = 0; \ | |
70342287 | 232 | if (__h->e_ident[EI_CLASS] != ELFCLASS64) \ |
1da177e4 LT |
233 | __res = 0; \ |
234 | \ | |
235 | __res; \ | |
236 | }) | |
237 | ||
238 | /* | |
239 | * These are used to set parameters in the core dumps. | |
240 | */ | |
241 | #define ELF_CLASS ELFCLASS64 | |
242 | ||
875d43e7 | 243 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
244 | |
245 | /* | |
246 | * These are used to set parameters in the core dumps. | |
247 | */ | |
248 | #ifdef __MIPSEB__ | |
249 | #define ELF_DATA ELFDATA2MSB | |
08d9d1c4 | 250 | #elif defined(__MIPSEL__) |
1da177e4 LT |
251 | #define ELF_DATA ELFDATA2LSB |
252 | #endif | |
253 | #define ELF_ARCH EM_MIPS | |
254 | ||
255 | #endif /* !defined(ELF_ARCH) */ | |
256 | ||
e50c0a8f RB |
257 | struct mips_abi; |
258 | ||
259 | extern struct mips_abi mips_abi; | |
260 | extern struct mips_abi mips_abi_32; | |
261 | extern struct mips_abi mips_abi_n32; | |
262 | ||
875d43e7 | 263 | #ifdef CONFIG_32BIT |
1da177e4 | 264 | |
0b592682 | 265 | #define SET_PERSONALITY(ex) \ |
e50c0a8f | 266 | do { \ |
597ce172 PB |
267 | if ((ex).e_flags & EF_MIPS_FP64) \ |
268 | clear_thread_flag(TIF_32BIT_FPREGS); \ | |
269 | else \ | |
270 | set_thread_flag(TIF_32BIT_FPREGS); \ | |
271 | \ | |
4227a2d4 PB |
272 | clear_thread_flag(TIF_HYBRID_FPREGS); \ |
273 | \ | |
1c0d52b9 DD |
274 | if (personality(current->personality) != PER_LINUX) \ |
275 | set_personality(PER_LINUX); \ | |
e50c0a8f RB |
276 | \ |
277 | current->thread.abi = &mips_abi; \ | |
1da177e4 LT |
278 | } while (0) |
279 | ||
875d43e7 | 280 | #endif /* CONFIG_32BIT */ |
1da177e4 | 281 | |
875d43e7 | 282 | #ifdef CONFIG_64BIT |
1da177e4 | 283 | |
e50c0a8f RB |
284 | #ifdef CONFIG_MIPS32_N32 |
285 | #define __SET_PERSONALITY32_N32() \ | |
286 | do { \ | |
293c5bd1 | 287 | set_thread_flag(TIF_32BIT_ADDR); \ |
e50c0a8f RB |
288 | current->thread.abi = &mips_abi_n32; \ |
289 | } while (0) | |
290 | #else | |
291 | #define __SET_PERSONALITY32_N32() \ | |
292 | do { } while (0) | |
293 | #endif | |
294 | ||
295 | #ifdef CONFIG_MIPS32_O32 | |
597ce172 | 296 | #define __SET_PERSONALITY32_O32(ex) \ |
e50c0a8f | 297 | do { \ |
293c5bd1 RB |
298 | set_thread_flag(TIF_32BIT_REGS); \ |
299 | set_thread_flag(TIF_32BIT_ADDR); \ | |
597ce172 PB |
300 | \ |
301 | if (!((ex).e_flags & EF_MIPS_FP64)) \ | |
302 | set_thread_flag(TIF_32BIT_FPREGS); \ | |
303 | \ | |
e50c0a8f RB |
304 | current->thread.abi = &mips_abi_32; \ |
305 | } while (0) | |
306 | #else | |
597ce172 | 307 | #define __SET_PERSONALITY32_O32(ex) \ |
e50c0a8f RB |
308 | do { } while (0) |
309 | #endif | |
310 | ||
311 | #ifdef CONFIG_MIPS32_COMPAT | |
312 | #define __SET_PERSONALITY32(ex) \ | |
313 | do { \ | |
314 | if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \ | |
315 | ((ex).e_flags & EF_MIPS_ABI) == 0) \ | |
316 | __SET_PERSONALITY32_N32(); \ | |
317 | else \ | |
597ce172 | 318 | __SET_PERSONALITY32_O32(ex); \ |
e50c0a8f RB |
319 | } while (0) |
320 | #else | |
70342287 | 321 | #define __SET_PERSONALITY32(ex) do { } while (0) |
e50c0a8f RB |
322 | #endif |
323 | ||
0b592682 | 324 | #define SET_PERSONALITY(ex) \ |
e50c0a8f | 325 | do { \ |
1c0d52b9 DD |
326 | unsigned int p; \ |
327 | \ | |
293c5bd1 | 328 | clear_thread_flag(TIF_32BIT_REGS); \ |
597ce172 | 329 | clear_thread_flag(TIF_32BIT_FPREGS); \ |
4227a2d4 | 330 | clear_thread_flag(TIF_HYBRID_FPREGS); \ |
293c5bd1 RB |
331 | clear_thread_flag(TIF_32BIT_ADDR); \ |
332 | \ | |
e50c0a8f RB |
333 | if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ |
334 | __SET_PERSONALITY32(ex); \ | |
293c5bd1 | 335 | else \ |
e50c0a8f | 336 | current->thread.abi = &mips_abi; \ |
e50c0a8f | 337 | \ |
1c0d52b9 DD |
338 | p = personality(current->personality); \ |
339 | if (p != PER_LINUX32 && p != PER_LINUX) \ | |
e50c0a8f | 340 | set_personality(PER_LINUX); \ |
1da177e4 LT |
341 | } while (0) |
342 | ||
875d43e7 | 343 | #endif /* CONFIG_64BIT */ |
1da177e4 | 344 | |
6a9c001b | 345 | #define CORE_DUMP_USE_REGSET |
1da177e4 LT |
346 | #define ELF_EXEC_PAGESIZE PAGE_SIZE |
347 | ||
348 | /* This yields a mask that user programs can use to figure out what | |
349 | instruction set this cpu supports. This could be done in userspace, | |
350 | but it's not easy, and we've already done it here. */ | |
351 | ||
70342287 | 352 | #define ELF_HWCAP (0) |
1da177e4 | 353 | |
874fd3b5 DD |
354 | /* |
355 | * This yields a string that ld.so will use to load implementation | |
70342287 | 356 | * specific libraries for optimization. This is more specific in |
874fd3b5 DD |
357 | * intent than poking at uname or /proc/cpuinfo. |
358 | */ | |
1da177e4 | 359 | |
874fd3b5 DD |
360 | #define ELF_PLATFORM __elf_platform |
361 | extern const char *__elf_platform; | |
1da177e4 LT |
362 | |
363 | /* | |
364 | * See comments in asm-alpha/elf.h, this is the same thing | |
365 | * on the MIPS. | |
366 | */ | |
367 | #define ELF_PLAT_INIT(_r, load_addr) do { \ | |
368 | _r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0; \ | |
369 | _r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0; \ | |
370 | _r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0; \ | |
371 | _r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0; \ | |
372 | _r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0; \ | |
373 | _r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0; \ | |
374 | _r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0; \ | |
375 | _r->regs[30] = _r->regs[31] = 0; \ | |
376 | } while (0) | |
377 | ||
378 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical | |
379 | use of this is to invoke "./ld.so someprog" to test out a new version of | |
70342287 RB |
380 | the loader. We need to make sure that it is out of the way of the program |
381 | that it will "exec", and that there is sufficient room for the brk. */ | |
1da177e4 LT |
382 | |
383 | #ifndef ELF_ET_DYN_BASE | |
70342287 | 384 | #define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) |
1da177e4 LT |
385 | #endif |
386 | ||
c52d0d30 DD |
387 | #define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1 |
388 | struct linux_binprm; | |
389 | extern int arch_setup_additional_pages(struct linux_binprm *bprm, | |
390 | int uses_interp); | |
652b14aa DD |
391 | |
392 | struct mm_struct; | |
393 | extern unsigned long arch_randomize_brk(struct mm_struct *mm); | |
394 | #define arch_randomize_brk arch_randomize_brk | |
395 | ||
1da177e4 | 396 | #endif /* _ASM_ELF_H */ |