[linux-2.6-block.git] / arch / mips / include / asm / cpu-info.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 Waldorf GMBH
 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 Paul M. Antoine
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2004  Maciej W. Rozycki
 */
#ifndef __ASM_CPU_INFO_H
#define __ASM_CPU_INFO_H

#include <linux/types.h>

#include <asm/cache.h>

/*
 * Descriptor for a cache
 */
struct cache_desc {
	unsigned int waysize;	/* Bytes per way */
	unsigned short sets;	/* Number of lines per set */
	unsigned char ways;	/* Number of ways */
	unsigned char linesz;	/* Size of line in bytes */
	unsigned char waybit;	/* Bits to select in a cache set */
	unsigned char flags;	/* Flags describing cache properties */
};

/*
 * Flag definitions
 */
#define MIPS_CACHE_NOT_PRESENT	0x00000001
#define MIPS_CACHE_VTAG		0x00000002	/* Virtually tagged cache */
#define MIPS_CACHE_ALIASES	0x00000004	/* Cache could have aliases */
#define MIPS_CACHE_IC_F_DC	0x00000008	/* Ic can refill from D-cache */
#define MIPS_IC_SNOOPS_REMOTE	0x00000010	/* Ic snoops remote stores */
#define MIPS_CACHE_PINDEX	0x00000020	/* Physically indexed cache */

struct cpuinfo_mips {
	unsigned int		udelay_val;
	unsigned int		asid_cache;

	/*
	 * Capability and feature descriptor structure for MIPS CPU
	 */
	unsigned long		options;
	unsigned long		ases;
	unsigned int		processor_id;
	unsigned int		fpu_id;
	unsigned int		cputype;
	int			isa_level;
	int			tlbsize;
	struct cache_desc	icache;	/* Primary I-cache */
	struct cache_desc	dcache;	/* Primary D or combined I/D cache */
	struct cache_desc	scache;	/* Secondary cache */
	struct cache_desc	tcache;	/* Tertiary/split secondary cache */
	int			srsets;	/* Shadow register sets */
	int			core;	/* physical core number */
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
	/*
	 * In the MIPS MT "SMTC" model, each TC is considered
	 * to be a "CPU" for the purposes of scheduling, but
	 * exception resources, ASID spaces, etc, are common
	 * to all TCs within the same VPE.
	 */
	int			vpe_id;  /* Virtual Processor number */
#endif
#ifdef CONFIG_MIPS_MT_SMTC
	int			tc_id;   /* Thread Context number */
#endif
	void 			*data;	/* Additional data */
	unsigned int		watch_reg_count;   /* Number that exist */
	unsigned int		watch_reg_use_cnt; /* Usable by ptrace */
#define NUM_WATCH_REGS 4
	u16			watch_reg_masks[NUM_WATCH_REGS];
} __attribute__((aligned(SMP_CACHE_BYTES)));

extern struct cpuinfo_mips cpu_data[];
#define current_cpu_data cpu_data[smp_processor_id()]
#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]

extern void cpu_probe(void);
extern void cpu_report(void);

extern const char *__cpu_name[];
#define cpu_name_string()	__cpu_name[smp_processor_id()]

#endif /* __ASM_CPU_INFO_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 Waldorf GMBH
	7	* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
	8	* Copyright (C) 1996 Paul M. Antoine
	9	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
4194318c	10	* Copyright (C) 2004 Maciej W. Rozycki
1da177e4 LT	11	*/
	12	#ifndef __ASM_CPU_INFO_H
	13	#define __ASM_CPU_INFO_H
	14
6aa3524c DD	15	#include <linux/types.h>
6aa3524c DD	16
1da177e4 LT	17	#include <asm/cache.h>
1da177e4 LT	18
1da177e4 LT	19	/*
	20	* Descriptor for a cache
	21	*/
	22	struct cache_desc {
1da177e4	23	unsigned int waysize; /* Bytes per way */
6f2c3fa0 RB	24	unsigned short sets; /* Number of lines per set */
	25	unsigned char ways; /* Number of ways */
	26	unsigned char linesz; /* Size of line in bytes */
	27	unsigned char waybit; /* Bits to select in a cache set */
	28	unsigned char flags; /* Flags describing cache properties */
1da177e4 LT	29	};
	30
	31	/*
	32	* Flag definitions
	33	*/
	34	#define MIPS_CACHE_NOT_PRESENT 0x00000001
	35	#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
	36	#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
	37	#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
	38	#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
de62893b	39	#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
1da177e4 LT	40
1da177e4 LT	41	struct cpuinfo_mips {
5636919b RB	42	unsigned int udelay_val;
5636919b RB	43	unsigned int asid_cache;
1da177e4 LT	44
	45	/*
	46	* Capability and feature descriptor structure for MIPS CPU
	47	*/
	48	unsigned long options;
4194318c	49	unsigned long ases;
1da177e4 LT	50	unsigned int processor_id;
	51	unsigned int fpu_id;
	52	unsigned int cputype;
	53	int isa_level;
	54	int tlbsize;
	55	struct cache_desc icache; /* Primary I-cache */
	56	struct cache_desc dcache; /* Primary D or combined I/D cache */
	57	struct cache_desc scache; /* Secondary cache */
	58	struct cache_desc tcache; /* Tertiary/split secondary cache */
f6771dbb	59	int srsets; /* Shadow register sets */
0ab7aefc	60	int core; /* physical core number */
d6c3048c	61	#if defined(CONFIG_MIPS_MT_SMP) \|\| defined(CONFIG_MIPS_MT_SMTC)
41c594ab RB	62	/*
	63	* In the MIPS MT "SMTC" model, each TC is considered
	64	* to be a "CPU" for the purposes of scheduling, but
	65	* exception resources, ASID spaces, etc, are common
	66	* to all TCs within the same VPE.
	67	*/
	68	int vpe_id; /* Virtual Processor number */
d6c3048c	69	#endif
0ab7aefc RB	70	#ifdef CONFIG_MIPS_MT_SMTC
	71	int tc_id; /* Thread Context number */
	72	#endif
1da177e4	73	void data; / Additional data */
6aa3524c DD	74	unsigned int watch_reg_count; /* Number that exist */
	75	unsigned int watch_reg_use_cnt; /* Usable by ptrace */
	76	#define NUM_WATCH_REGS 4
	77	u16 watch_reg_masks[NUM_WATCH_REGS];
1da177e4 LT	78	} __attribute__((aligned(SMP_CACHE_BYTES)));
	79
	80	extern struct cpuinfo_mips cpu_data[];
	81	#define current_cpu_data cpu_data[smp_processor_id()]
53dc8028	82	#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
1da177e4 LT	83
	84	extern void cpu_probe(void);
	85	extern void cpu_report(void);
	86
9966db25 RB	87	extern const char *__cpu_name[];
	88	#define cpu_name_string() __cpu_name[smp_processor_id()]
	89
1da177e4	90	#endif /* __ASM_CPU_INFO_H */