[linux-2.6-block.git] / arch / mips / include / asm / cpu-features.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003, 2004 Ralf Baechle
 * Copyright (C) 2004  Maciej W. Rozycki
 */
#ifndef __ASM_CPU_FEATURES_H
#define __ASM_CPU_FEATURES_H

#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <cpu-feature-overrides.h>

/*
 * SMP assumption: Options of CPU 0 are a superset of all processors.
 * This is true for all known MIPS systems.
 */
#ifndef cpu_has_tlb
#define cpu_has_tlb		(cpu_data[0].options & MIPS_CPU_TLB)
#endif
#ifndef cpu_has_ftlb
#define cpu_has_ftlb		(cpu_data[0].options & MIPS_CPU_FTLB)
#endif
#ifndef cpu_has_tlbinv
#define cpu_has_tlbinv		(cpu_data[0].options & MIPS_CPU_TLBINV)
#endif
#ifndef cpu_has_segments
#define cpu_has_segments	(cpu_data[0].options & MIPS_CPU_SEGMENTS)
#endif
#ifndef cpu_has_eva
#define cpu_has_eva		(cpu_data[0].options & MIPS_CPU_EVA)
#endif
#ifndef cpu_has_htw
#define cpu_has_htw		(cpu_data[0].options & MIPS_CPU_HTW)
#endif
#ifndef cpu_has_rixiex
#define cpu_has_rixiex		(cpu_data[0].options & MIPS_CPU_RIXIEX)
#endif
#ifndef cpu_has_maar
#define cpu_has_maar		(cpu_data[0].options & MIPS_CPU_MAAR)
#endif
#ifndef cpu_has_rw_llb
#define cpu_has_rw_llb		(cpu_data[0].options & MIPS_CPU_RW_LLB)
#endif

/*
 * For the moment we don't consider R6000 and R8000 so we can assume that
 * anything that doesn't support R4000-style exceptions and interrupts is
 * R3000-like.  Users should still treat these two macro definitions as
 * opaque.
 */
#ifndef cpu_has_3kex
#define cpu_has_3kex		(!cpu_has_4kex)
#endif
#ifndef cpu_has_4kex
#define cpu_has_4kex		(cpu_data[0].options & MIPS_CPU_4KEX)
#endif
#ifndef cpu_has_3k_cache
#define cpu_has_3k_cache	(cpu_data[0].options & MIPS_CPU_3K_CACHE)
#endif
#define cpu_has_6k_cache	0
#define cpu_has_8k_cache	0
#ifndef cpu_has_4k_cache
#define cpu_has_4k_cache	(cpu_data[0].options & MIPS_CPU_4K_CACHE)
#endif
#ifndef cpu_has_tx39_cache
#define cpu_has_tx39_cache	(cpu_data[0].options & MIPS_CPU_TX39_CACHE)
#endif
#ifndef cpu_has_octeon_cache
#define cpu_has_octeon_cache	0
#endif
/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
#ifndef cpu_has_fpu
#define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
#define raw_cpu_has_fpu		(raw_current_cpu_data.options & MIPS_CPU_FPU)
#else
#define raw_cpu_has_fpu		cpu_has_fpu
#endif
#ifndef cpu_has_32fpr
#define cpu_has_32fpr		(cpu_data[0].options & MIPS_CPU_32FPR)
#endif
#ifndef cpu_has_counter
#define cpu_has_counter		(cpu_data[0].options & MIPS_CPU_COUNTER)
#endif
#ifndef cpu_has_watch
#define cpu_has_watch		(cpu_data[0].options & MIPS_CPU_WATCH)
#endif
#ifndef cpu_has_divec
#define cpu_has_divec		(cpu_data[0].options & MIPS_CPU_DIVEC)
#endif
#ifndef cpu_has_vce
#define cpu_has_vce		(cpu_data[0].options & MIPS_CPU_VCE)
#endif
#ifndef cpu_has_cache_cdex_p
#define cpu_has_cache_cdex_p	(cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
#endif
#ifndef cpu_has_cache_cdex_s
#define cpu_has_cache_cdex_s	(cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
#endif
#ifndef cpu_has_prefetch
#define cpu_has_prefetch	(cpu_data[0].options & MIPS_CPU_PREFETCH)
#endif
#ifndef cpu_has_mcheck
#define cpu_has_mcheck		(cpu_data[0].options & MIPS_CPU_MCHECK)
#endif
#ifndef cpu_has_ejtag
#define cpu_has_ejtag		(cpu_data[0].options & MIPS_CPU_EJTAG)
#endif
#ifndef cpu_has_llsc
#define cpu_has_llsc		(cpu_data[0].options & MIPS_CPU_LLSC)
#endif
#ifndef cpu_has_bp_ghist
#define cpu_has_bp_ghist	(cpu_data[0].options & MIPS_CPU_BP_GHIST)
#endif
#ifndef kernel_uses_llsc
#define kernel_uses_llsc	cpu_has_llsc
#endif
#ifndef cpu_has_mips16
#define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
#endif
#ifndef cpu_has_mdmx
#define cpu_has_mdmx		(cpu_data[0].ases & MIPS_ASE_MDMX)
#endif
#ifndef cpu_has_mips3d
#define cpu_has_mips3d		(cpu_data[0].ases & MIPS_ASE_MIPS3D)
#endif
#ifndef cpu_has_smartmips
#define cpu_has_smartmips	(cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
#endif

#ifndef cpu_has_rixi
# ifdef CONFIG_64BIT
# define cpu_has_rixi		(cpu_data[0].options & MIPS_CPU_RIXI)
# else /* CONFIG_32BIT */
# define cpu_has_rixi		((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits)
# endif
#endif

#ifndef cpu_has_mmips
# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
#  define cpu_has_mmips		(cpu_data[0].options & MIPS_CPU_MICROMIPS)
# else
#  define cpu_has_mmips		0
# endif
#endif

#ifndef cpu_has_xpa
#define cpu_has_xpa		(cpu_data[0].options & MIPS_CPU_XPA)
#endif
#ifndef cpu_has_vtag_icache
#define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
#endif
#ifndef cpu_has_dc_aliases
#define cpu_has_dc_aliases	(cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
#endif
#ifndef cpu_has_ic_fills_f_dc
#define cpu_has_ic_fills_f_dc	(cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
#endif
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif
#ifndef cpu_has_local_ebase
#define cpu_has_local_ebase	1
#endif

/*
 * I-Cache snoops remote store.	 This only matters on SMP.  Some multiprocessors
 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
 * don't.  For maintaining I-cache coherency this means we need to flush the
 * D-cache all the way back to whever the I-cache does refills from, so the
 * I-cache has a chance to see the new data at all.  Then we have to flush the
 * I-cache also.
 * Note we may have been rescheduled and may no longer be running on the CPU
 * that did the store so we can't optimize this into only doing the flush on
 * the local CPU.
 */
#ifndef cpu_icache_snoops_remote_store
#ifdef CONFIG_SMP
#define cpu_icache_snoops_remote_store	(cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
#else
#define cpu_icache_snoops_remote_store	1
#endif
#endif

#ifndef cpu_has_mips_1
# define cpu_has_mips_1		(!cpu_has_mips_r6)
#endif
#ifndef cpu_has_mips_2
# define cpu_has_mips_2		(cpu_data[0].isa_level & MIPS_CPU_ISA_II)
#endif
#ifndef cpu_has_mips_3
# define cpu_has_mips_3		(cpu_data[0].isa_level & MIPS_CPU_ISA_III)
#endif
#ifndef cpu_has_mips_4
# define cpu_has_mips_4		(cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
#endif
#ifndef cpu_has_mips_5
# define cpu_has_mips_5		(cpu_data[0].isa_level & MIPS_CPU_ISA_V)
#endif
#ifndef cpu_has_mips32r1
# define cpu_has_mips32r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
#endif
#ifndef cpu_has_mips32r2
# define cpu_has_mips32r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
#endif
#ifndef cpu_has_mips32r6
# define cpu_has_mips32r6	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
#endif
#ifndef cpu_has_mips64r1
# define cpu_has_mips64r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
#endif
#ifndef cpu_has_mips64r2
# define cpu_has_mips64r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
#endif
#ifndef cpu_has_mips64r6
# define cpu_has_mips64r6	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
#endif

/*
 * Shortcuts ...
 */
#define cpu_has_mips_2_3_4_5	(cpu_has_mips_2 | cpu_has_mips_3_4_5)
#define cpu_has_mips_3_4_5	(cpu_has_mips_3 | cpu_has_mips_4_5)
#define cpu_has_mips_4_5	(cpu_has_mips_4 | cpu_has_mips_5)

#define cpu_has_mips_2_3_4_5_r	(cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
#define cpu_has_mips_3_4_5_r	(cpu_has_mips_3 | cpu_has_mips_4_5_r)
#define cpu_has_mips_4_5_r	(cpu_has_mips_4 | cpu_has_mips_5_r)
#define cpu_has_mips_5_r	(cpu_has_mips_5 | cpu_has_mips_r)

#define cpu_has_mips_3_4_5_64_r2_r6					\
				(cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
#define cpu_has_mips_4_5_64_r2_r6					\
				(cpu_has_mips_4_5 | cpu_has_mips64r1 |	\
				 cpu_has_mips_r2 | cpu_has_mips_r6)

#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
#define cpu_has_mips_r6	(cpu_has_mips32r6 | cpu_has_mips64r6)
#define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
			 cpu_has_mips32r6 | cpu_has_mips64r1 | \
			 cpu_has_mips64r2 | cpu_has_mips64r6)

/* MIPSR2 and MIPSR6 have a lot of similarities */
#define cpu_has_mips_r2_r6	(cpu_has_mips_r2 | cpu_has_mips_r6)

/*
 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
 *
 * Returns non-zero value if the current processor implementation requires
 * an IHB instruction to deal with an instruction hazard as per MIPS R2
 * architecture specification, zero otherwise.
 */
#ifndef cpu_has_mips_r2_exec_hazard
#define cpu_has_mips_r2_exec_hazard					\
({									\
	int __res;							\
									\
	switch (current_cpu_type()) {					\
	case CPU_M14KC:							\
	case CPU_74K:							\
	case CPU_1074K:							\
	case CPU_PROAPTIV:						\
	case CPU_P5600:							\
	case CPU_M5150:							\
	case CPU_QEMU_GENERIC:						\
	case CPU_CAVIUM_OCTEON:						\
	case CPU_CAVIUM_OCTEON_PLUS:					\
	case CPU_CAVIUM_OCTEON2:					\
	case CPU_CAVIUM_OCTEON3:					\
		__res = 0;						\
		break;							\
									\
	default:							\
		__res = 1;						\
	}								\
									\
	__res;								\
})
#endif

/*
 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
 * pre-MIPS32/MIPS64 processors have CLO, CLZ.	The IDT RC64574 is 64-bit and
 * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
 */
#ifndef cpu_has_clo_clz
#define cpu_has_clo_clz	cpu_has_mips_r
#endif

/*
 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
 * This indicates the availability of WSBH and in case of 64 bit CPUs also
 * DSBH and DSHD.
 */
#ifndef cpu_has_wsbh
#define cpu_has_wsbh		cpu_has_mips_r2
#endif

#ifndef cpu_has_dsp
#define cpu_has_dsp		(cpu_data[0].ases & MIPS_ASE_DSP)
#endif

#ifndef cpu_has_dsp2
#define cpu_has_dsp2		(cpu_data[0].ases & MIPS_ASE_DSP2P)
#endif

#ifndef cpu_has_mipsmt
#define cpu_has_mipsmt		(cpu_data[0].ases & MIPS_ASE_MIPSMT)
#endif

#ifndef cpu_has_userlocal
#define cpu_has_userlocal	(cpu_data[0].options & MIPS_CPU_ULRI)
#endif

#ifdef CONFIG_32BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex	(cpu_data[0].options & MIPS_CPU_NOFPUEX)
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits		(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg	(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs		0
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses	0
# endif
# ifndef cpu_vmbits
# define cpu_vmbits 31
# endif
#endif

#ifdef CONFIG_64BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex		0
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits			1
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg		1
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs		1
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses	1
# endif
# ifndef cpu_vmbits
# define cpu_vmbits cpu_data[0].vmbits
# define __NEED_VMBITS_PROBE
# endif
#endif

#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
# define cpu_has_vint		(cpu_data[0].options & MIPS_CPU_VINT)
#elif !defined(cpu_has_vint)
# define cpu_has_vint			0
#endif

#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
# define cpu_has_veic		(cpu_data[0].options & MIPS_CPU_VEIC)
#elif !defined(cpu_has_veic)
# define cpu_has_veic			0
#endif

#ifndef cpu_has_inclusive_pcaches
#define cpu_has_inclusive_pcaches	(cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
#endif

#ifndef cpu_dcache_line_size
#define cpu_dcache_line_size()	cpu_data[0].dcache.linesz
#endif
#ifndef cpu_icache_line_size
#define cpu_icache_line_size()	cpu_data[0].icache.linesz
#endif
#ifndef cpu_scache_line_size
#define cpu_scache_line_size()	cpu_data[0].scache.linesz
#endif

#ifndef cpu_hwrena_impl_bits
#define cpu_hwrena_impl_bits		0
#endif

#ifndef cpu_has_perf_cntr_intr_bit
#define cpu_has_perf_cntr_intr_bit	(cpu_data[0].options & MIPS_CPU_PCI)
#endif

#ifndef cpu_has_vz
#define cpu_has_vz		(cpu_data[0].ases & MIPS_ASE_VZ)
#endif

#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
# define cpu_has_msa		(cpu_data[0].ases & MIPS_ASE_MSA)
#elif !defined(cpu_has_msa)
# define cpu_has_msa		0
#endif

#ifndef cpu_has_fre
# define cpu_has_fre		(cpu_data[0].options & MIPS_CPU_FRE)
#endif

#ifndef cpu_has_cdmm
# define cpu_has_cdmm		(cpu_data[0].options & MIPS_CPU_CDMM)
#endif

#ifndef cpu_has_small_pages
# define cpu_has_small_pages	(cpu_data[0].options & MIPS_CPU_SP)
#endif

#endif /* __ASM_CPU_FEATURES_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003, 2004 Ralf Baechle
4194318c	7	* Copyright (C) 2004 Maciej W. Rozycki
1da177e4 LT	8	*/
	9	#ifndef __ASM_CPU_FEATURES_H
	10	#define __ASM_CPU_FEATURES_H
	11
1da177e4 LT	12	#include <asm/cpu.h>
	13	#include <asm/cpu-info.h>
	14	#include <cpu-feature-overrides.h>
	15
	16	/*
	17	* SMP assumption: Options of CPU 0 are a superset of all processors.
	18	* This is true for all known MIPS systems.
	19	*/
	20	#ifndef cpu_has_tlb
	21	#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
	22	#endif
2f6f3136 JH	23	#ifndef cpu_has_ftlb
	24	#define cpu_has_ftlb (cpu_data[0].options & MIPS_CPU_FTLB)
	25	#endif
1745c1ef LY	26	#ifndef cpu_has_tlbinv
	27	#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
	28	#endif
4a0156fb SH	29	#ifndef cpu_has_segments
	30	#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
	31	#endif
7ae66966 MC	32	#ifndef cpu_has_eva
	33	#define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
	34	#endif
e647e6b5 MC	35	#ifndef cpu_has_htw
	36	#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
	37	#endif
6ee729aa LY	38	#ifndef cpu_has_rixiex
	39	#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
	40	#endif
1f6c52ff PB	41	#ifndef cpu_has_maar
	42	#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
	43	#endif
5aed9da1 MC	44	#ifndef cpu_has_rw_llb
	45	#define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB)
	46	#endif
1990e542 RB	47
	48	/*
	49	* For the moment we don't consider R6000 and R8000 so we can assume that
	50	* anything that doesn't support R4000-style exceptions and interrupts is
	51	* R3000-like. Users should still treat these two macro definitions as
	52	* opaque.
	53	*/
	54	#ifndef cpu_has_3kex
	55	#define cpu_has_3kex (!cpu_has_4kex)
	56	#endif
1da177e4 LT	57	#ifndef cpu_has_4kex
	58	#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
	59	#endif
02cf2119 RB	60	#ifndef cpu_has_3k_cache
	61	#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
	62	#endif
	63	#define cpu_has_6k_cache 0
	64	#define cpu_has_8k_cache 0
	65	#ifndef cpu_has_4k_cache
	66	#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
	67	#endif
	68	#ifndef cpu_has_tx39_cache
	69	#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
	70	#endif
47d979ec DD	71	#ifndef cpu_has_octeon_cache
	72	#define cpu_has_octeon_cache 0
	73	#endif
18a2c2c6	74	/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */
1da177e4	75	#ifndef cpu_has_fpu
f088fc84	76	#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
53dc8028 AN	77	#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
	78	#else
	79	#define raw_cpu_has_fpu cpu_has_fpu
1da177e4 LT	80	#endif
	81	#ifndef cpu_has_32fpr
	82	#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
	83	#endif
	84	#ifndef cpu_has_counter
	85	#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
	86	#endif
	87	#ifndef cpu_has_watch
	88	#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
	89	#endif
1da177e4 LT	90	#ifndef cpu_has_divec
	91	#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
	92	#endif
	93	#ifndef cpu_has_vce
	94	#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
	95	#endif
	96	#ifndef cpu_has_cache_cdex_p
	97	#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
	98	#endif
	99	#ifndef cpu_has_cache_cdex_s
	100	#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
	101	#endif
	102	#ifndef cpu_has_prefetch
	103	#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
	104	#endif
	105	#ifndef cpu_has_mcheck
	106	#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
	107	#endif
	108	#ifndef cpu_has_ejtag
	109	#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
	110	#endif
	111	#ifndef cpu_has_llsc
	112	#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
	113	#endif
8d5ded16 JK	114	#ifndef cpu_has_bp_ghist
	115	#define cpu_has_bp_ghist (cpu_data[0].options & MIPS_CPU_BP_GHIST)
	116	#endif
b791d119 DD	117	#ifndef kernel_uses_llsc
	118	#define kernel_uses_llsc cpu_has_llsc
	119	#endif
4194318c RB	120	#ifndef cpu_has_mips16
	121	#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
	122	#endif
	123	#ifndef cpu_has_mdmx
fc192e50	124	#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
4194318c RB	125	#endif
4194318c RB	126	#ifndef cpu_has_mips3d
fc192e50	127	#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
4194318c RB	128	#endif
4194318c RB	129	#ifndef cpu_has_smartmips
fc192e50	130	#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
4194318c	131	#endif
a68d09a1	132
b2ab4f08	133	#ifndef cpu_has_rixi
a68d09a1 DD	134	# ifdef CONFIG_64BIT
	135	# define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
	136	# else /* CONFIG_32BIT */
	137	# define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits)
	138	# endif
b2ab4f08	139	#endif
a68d09a1	140
f8fa4811	141	#ifndef cpu_has_mmips
3ddc14ad DD	142	# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
	143	# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
	144	# else
	145	# define cpu_has_mmips 0
	146	# endif
f8fa4811	147	#endif
a68d09a1	148
c5b36783 SH	149	#ifndef cpu_has_xpa
	150	#define cpu_has_xpa (cpu_data[0].options & MIPS_CPU_XPA)
	151	#endif
1da177e4 LT	152	#ifndef cpu_has_vtag_icache
	153	#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
	154	#endif
	155	#ifndef cpu_has_dc_aliases
	156	#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
	157	#endif
	158	#ifndef cpu_has_ic_fills_f_dc
	159	#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
	160	#endif
de62893b	161	#ifndef cpu_has_pindexed_dcache
fc192e50	162	#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
de62893b	163	#endif
8759934e HC	164	#ifndef cpu_has_local_ebase
	165	#define cpu_has_local_ebase 1
	166	#endif
1da177e4 LT	167
1da177e4 LT	168	/*
70342287	169	* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
1da177e4 LT	170	* such as the R10000 have I-Caches that snoop local stores; the embedded ones
	171	* don't. For maintaining I-cache coherency this means we need to flush the
	172	* D-cache all the way back to whever the I-cache does refills from, so the
	173	* I-cache has a chance to see the new data at all. Then we have to flush the
	174	* I-cache also.
	175	* Note we may have been rescheduled and may no longer be running on the CPU
	176	* that did the store so we can't optimize this into only doing the flush on
	177	* the local CPU.
	178	*/
	179	#ifndef cpu_icache_snoops_remote_store
	180	#ifdef CONFIG_SMP
	181	#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
	182	#else
	183	#define cpu_icache_snoops_remote_store 1
	184	#endif
	185	#endif
	186
515a6393 MC	187	#ifndef cpu_has_mips_1
	188	# define cpu_has_mips_1 (!cpu_has_mips_r6)
	189	#endif
a96102be SH	190	#ifndef cpu_has_mips_2
	191	# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
	192	#endif
	193	#ifndef cpu_has_mips_3
	194	# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
	195	#endif
	196	#ifndef cpu_has_mips_4
	197	# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
	198	#endif
	199	#ifndef cpu_has_mips_5
	200	# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
	201	#endif
fc192e50	202	#ifndef cpu_has_mips32r1
0401572a	203	# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
fc192e50 TW	204	#endif
fc192e50 TW	205	#ifndef cpu_has_mips32r2
0401572a	206	# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
fc192e50	207	#endif
34c56fc1 LY	208	#ifndef cpu_has_mips32r6
	209	# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
	210	#endif
fc192e50	211	#ifndef cpu_has_mips64r1
0401572a	212	# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
fc192e50 TW	213	#endif
fc192e50 TW	214	#ifndef cpu_has_mips64r2
0401572a	215	# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
fc192e50	216	#endif
34c56fc1 LY	217	#ifndef cpu_has_mips64r6
	218	# define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
	219	#endif
0401572a RB	220
	221	/*
	222	* Shortcuts ...
	223	*/
08a07904 RB	224	#define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 \| cpu_has_mips_3_4_5)
	225	#define cpu_has_mips_3_4_5 (cpu_has_mips_3 \| cpu_has_mips_4_5)
	226	#define cpu_has_mips_4_5 (cpu_has_mips_4 \| cpu_has_mips_5)
	227
	228	#define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 \| cpu_has_mips_3_4_5_r)
	229	#define cpu_has_mips_3_4_5_r (cpu_has_mips_3 \| cpu_has_mips_4_5_r)
	230	#define cpu_has_mips_4_5_r (cpu_has_mips_4 \| cpu_has_mips_5_r)
	231	#define cpu_has_mips_5_r (cpu_has_mips_5 \| cpu_has_mips_r)
	232
2d83fea7 MR	233	#define cpu_has_mips_3_4_5_64_r2_r6 \
	234	(cpu_has_mips_3 \| cpu_has_mips_4_5_64_r2_r6)
	235	#define cpu_has_mips_4_5_64_r2_r6 \
	236	(cpu_has_mips_4_5 \| cpu_has_mips64r1 \| \
	237	cpu_has_mips_r2 \| cpu_has_mips_r6)
08a07904	238
34c56fc1 LY	239	#define cpu_has_mips32 (cpu_has_mips32r1 \| cpu_has_mips32r2 \| cpu_has_mips32r6)
34c56fc1 LY	240	#define cpu_has_mips64 (cpu_has_mips64r1 \| cpu_has_mips64r2 \| cpu_has_mips64r6)
70342287 RB	241	#define cpu_has_mips_r1 (cpu_has_mips32r1 \| cpu_has_mips64r1)
70342287 RB	242	#define cpu_has_mips_r2 (cpu_has_mips32r2 \| cpu_has_mips64r2)
34c56fc1	243	#define cpu_has_mips_r6 (cpu_has_mips32r6 \| cpu_has_mips64r6)
c46b302b	244	#define cpu_has_mips_r (cpu_has_mips32r1 \| cpu_has_mips32r2 \| \
34c56fc1 LY	245	cpu_has_mips32r6 \| cpu_has_mips64r1 \| \
	246	cpu_has_mips64r2 \| cpu_has_mips64r6)
	247
	248	/* MIPSR2 and MIPSR6 have a lot of similarities */
	249	#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 \| cpu_has_mips_r6)
0401572a	250
9cdf30bd RB	251	/*
	252	* cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
	253	*
	254	* Returns non-zero value if the current processor implementation requires
	255	* an IHB instruction to deal with an instruction hazard as per MIPS R2
	256	* architecture specification, zero otherwise.
	257	*/
41f0e4d0	258	#ifndef cpu_has_mips_r2_exec_hazard
9cdf30bd RB	259	#define cpu_has_mips_r2_exec_hazard \
	260	({ \
	261	int __res; \
	262	\
	263	switch (current_cpu_type()) { \
	264	case CPU_M14KC: \
	265	case CPU_74K: \
	266	case CPU_1074K: \
	267	case CPU_PROAPTIV: \
	268	case CPU_P5600: \
	269	case CPU_M5150: \
	270	case CPU_QEMU_GENERIC: \
	271	case CPU_CAVIUM_OCTEON: \
	272	case CPU_CAVIUM_OCTEON_PLUS: \
	273	case CPU_CAVIUM_OCTEON2: \
	274	case CPU_CAVIUM_OCTEON3: \
	275	__res = 0; \
	276	break; \
	277	\
	278	default: \
	279	__res = 1; \
	280	} \
	281	\
	282	__res; \
	283	})
41f0e4d0 DD	284	#endif
41f0e4d0 DD	285
47740eb8 RB	286	/*
47740eb8 RB	287	* MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
becee6b8	288	* pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
417a5eb0	289	* has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
47740eb8 RB	290	* cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
47740eb8 RB	291	*/
fc192e50 TW	292	#ifndef cpu_has_clo_clz
	293	#define cpu_has_clo_clz cpu_has_mips_r
	294	#endif
47740eb8	295
3c09bae4 CJ	296	/*
	297	* MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
	298	* MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
	299	* This indicates the availability of WSBH and in case of 64 bit CPUs also
	300	* DSBH and DSHD.
	301	*/
	302	#ifndef cpu_has_wsbh
	303	#define cpu_has_wsbh cpu_has_mips_r2
	304	#endif
	305
e50c0a8f RB	306	#ifndef cpu_has_dsp
	307	#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
	308	#endif
	309
ee80f7c7 SH	310	#ifndef cpu_has_dsp2
	311	#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
	312	#endif
	313
8f40611d	314	#ifndef cpu_has_mipsmt
2e128ded	315	#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
8f40611d RB	316	#endif
8f40611d RB	317
a3692020 RB	318	#ifndef cpu_has_userlocal
	319	#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
	320	#endif
	321
875d43e7	322	#ifdef CONFIG_32BIT
1da177e4 LT	323	# ifndef cpu_has_nofpuex
	324	# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
	325	# endif
	326	# ifndef cpu_has_64bits
	327	# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
	328	# endif
	329	# ifndef cpu_has_64bit_zero_reg
fc192e50	330	# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
1da177e4 LT	331	# endif
	332	# ifndef cpu_has_64bit_gp_regs
	333	# define cpu_has_64bit_gp_regs 0
	334	# endif
	335	# ifndef cpu_has_64bit_addresses
	336	# define cpu_has_64bit_addresses 0
	337	# endif
91dfc423 GR	338	# ifndef cpu_vmbits
	339	# define cpu_vmbits 31
	340	# endif
1da177e4 LT	341	#endif
1da177e4 LT	342
875d43e7	343	#ifdef CONFIG_64BIT
1da177e4 LT	344	# ifndef cpu_has_nofpuex
	345	# define cpu_has_nofpuex 0
	346	# endif
	347	# ifndef cpu_has_64bits
	348	# define cpu_has_64bits 1
	349	# endif
	350	# ifndef cpu_has_64bit_zero_reg
	351	# define cpu_has_64bit_zero_reg 1
	352	# endif
	353	# ifndef cpu_has_64bit_gp_regs
	354	# define cpu_has_64bit_gp_regs 1
	355	# endif
	356	# ifndef cpu_has_64bit_addresses
	357	# define cpu_has_64bit_addresses 1
	358	# endif
91dfc423 GR	359	# ifndef cpu_vmbits
	360	# define cpu_vmbits cpu_data[0].vmbits
	361	# define __NEED_VMBITS_PROBE
	362	# endif
1da177e4 LT	363	#endif
1da177e4 LT	364
f41ae0b2 RB	365	#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
	366	# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
	367	#elif !defined(cpu_has_vint)
8f40611d	368	# define cpu_has_vint 0
f41ae0b2 RB	369	#endif
	370
	371	#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
	372	# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
	373	#elif !defined(cpu_has_veic)
8f40611d RB	374	# define cpu_has_veic 0
	375	#endif
	376
fc5d2d27 RB	377	#ifndef cpu_has_inclusive_pcaches
fc5d2d27 RB	378	#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
1da177e4 LT	379	#endif
	380
	381	#ifndef cpu_dcache_line_size
54fd6441	382	#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
1da177e4 LT	383	#endif
1da177e4 LT	384	#ifndef cpu_icache_line_size
54fd6441	385	#define cpu_icache_line_size() cpu_data[0].icache.linesz
1da177e4 LT	386	#endif
1da177e4 LT	387	#ifndef cpu_scache_line_size
54fd6441	388	#define cpu_scache_line_size() cpu_data[0].scache.linesz
1da177e4 LT	389	#endif
1da177e4 LT	390
fbeda19f DD	391	#ifndef cpu_hwrena_impl_bits
	392	#define cpu_hwrena_impl_bits 0
	393	#endif
	394
da4b62cd AC	395	#ifndef cpu_has_perf_cntr_intr_bit
	396	#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
	397	#endif
	398
1e7decdb DD	399	#ifndef cpu_has_vz
	400	#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
	401	#endif
	402
a5e9a69e PB	403	#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
	404	# define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA)
	405	#elif !defined(cpu_has_msa)
	406	# define cpu_has_msa 0
	407	#endif
	408
adac5d53 PB	409	#ifndef cpu_has_fre
	410	# define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE)
	411	#endif
	412
9b3274bd JH	413	#ifndef cpu_has_cdmm
	414	# define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM)
	415	#endif
	416
aaa7be48 JH	417	#ifndef cpu_has_small_pages
	418	# define cpu_has_small_pages (cpu_data[0].options & MIPS_CPU_SP)
	419	#endif
	420
1da177e4	421	#endif /* __ASM_CPU_FEATURES_H */