Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2003 Ralf Baechle | |
7 | */ | |
8 | #ifndef _ASM_ASMMACRO_H | |
9 | #define _ASM_ASMMACRO_H | |
42a3b4f2 | 10 | |
1da177e4 | 11 | #include <asm/hazards.h> |
71ca7588 | 12 | #include <asm/asm-offsets.h> |
f7a46fa7 | 13 | #include <asm/msa.h> |
42a3b4f2 | 14 | |
875d43e7 | 15 | #ifdef CONFIG_32BIT |
1da177e4 LT |
16 | #include <asm/asmmacro-32.h> |
17 | #endif | |
875d43e7 | 18 | #ifdef CONFIG_64BIT |
1da177e4 LT |
19 | #include <asm/asmmacro-64.h> |
20 | #endif | |
41c594ab | 21 | |
6e1b29c3 JH |
22 | /* |
23 | * Helper macros for generating raw instruction encodings. | |
24 | */ | |
25 | #ifdef CONFIG_CPU_MICROMIPS | |
26 | .macro insn32_if_mm enc | |
27 | .insn | |
28 | .hword ((\enc) >> 16) | |
29 | .hword ((\enc) & 0xffff) | |
30 | .endm | |
31 | ||
32 | .macro insn_if_mips enc | |
33 | .endm | |
34 | #else | |
35 | .macro insn32_if_mm enc | |
36 | .endm | |
37 | ||
38 | .macro insn_if_mips enc | |
39 | .insn | |
40 | .word (\enc) | |
41 | .endm | |
42 | #endif | |
43 | ||
226da55f | 44 | #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) |
b6354db5 DD |
45 | .macro local_irq_enable reg=t0 |
46 | ei | |
47 | irq_enable_hazard | |
48 | .endm | |
49 | ||
50 | .macro local_irq_disable reg=t0 | |
51 | di | |
52 | irq_disable_hazard | |
53 | .endm | |
41c594ab | 54 | #else |
1da177e4 LT |
55 | .macro local_irq_enable reg=t0 |
56 | mfc0 \reg, CP0_STATUS | |
57 | ori \reg, \reg, 1 | |
58 | mtc0 \reg, CP0_STATUS | |
59 | irq_enable_hazard | |
60 | .endm | |
61 | ||
62 | .macro local_irq_disable reg=t0 | |
71ca7588 JQ |
63 | #ifdef CONFIG_PREEMPT |
64 | lw \reg, TI_PRE_COUNT($28) | |
65 | addi \reg, \reg, 1 | |
66 | sw \reg, TI_PRE_COUNT($28) | |
67 | #endif | |
1da177e4 LT |
68 | mfc0 \reg, CP0_STATUS |
69 | ori \reg, \reg, 1 | |
70 | xori \reg, \reg, 1 | |
71 | mtc0 \reg, CP0_STATUS | |
72 | irq_disable_hazard | |
71ca7588 JQ |
73 | #ifdef CONFIG_PREEMPT |
74 | lw \reg, TI_PRE_COUNT($28) | |
75 | addi \reg, \reg, -1 | |
76 | sw \reg, TI_PRE_COUNT($28) | |
77 | #endif | |
1da177e4 | 78 | .endm |
b633648c | 79 | #endif /* CONFIG_CPU_MIPSR2 */ |
1da177e4 | 80 | |
597ce172 | 81 | .macro fpu_save_16even thread tmp=t0 |
842dfc11 ML |
82 | .set push |
83 | SET_HARDFLOAT | |
597ce172 | 84 | cfc1 \tmp, fcr31 |
466aec5f JH |
85 | sdc1 $f0, THREAD_FPR0(\thread) |
86 | sdc1 $f2, THREAD_FPR2(\thread) | |
87 | sdc1 $f4, THREAD_FPR4(\thread) | |
88 | sdc1 $f6, THREAD_FPR6(\thread) | |
89 | sdc1 $f8, THREAD_FPR8(\thread) | |
90 | sdc1 $f10, THREAD_FPR10(\thread) | |
91 | sdc1 $f12, THREAD_FPR12(\thread) | |
92 | sdc1 $f14, THREAD_FPR14(\thread) | |
93 | sdc1 $f16, THREAD_FPR16(\thread) | |
94 | sdc1 $f18, THREAD_FPR18(\thread) | |
95 | sdc1 $f20, THREAD_FPR20(\thread) | |
96 | sdc1 $f22, THREAD_FPR22(\thread) | |
97 | sdc1 $f24, THREAD_FPR24(\thread) | |
98 | sdc1 $f26, THREAD_FPR26(\thread) | |
99 | sdc1 $f28, THREAD_FPR28(\thread) | |
100 | sdc1 $f30, THREAD_FPR30(\thread) | |
597ce172 | 101 | sw \tmp, THREAD_FCR31(\thread) |
842dfc11 | 102 | .set pop |
597ce172 PB |
103 | .endm |
104 | ||
105 | .macro fpu_save_16odd thread | |
106 | .set push | |
107 | .set mips64r2 | |
842dfc11 | 108 | SET_HARDFLOAT |
466aec5f JH |
109 | sdc1 $f1, THREAD_FPR1(\thread) |
110 | sdc1 $f3, THREAD_FPR3(\thread) | |
111 | sdc1 $f5, THREAD_FPR5(\thread) | |
112 | sdc1 $f7, THREAD_FPR7(\thread) | |
113 | sdc1 $f9, THREAD_FPR9(\thread) | |
114 | sdc1 $f11, THREAD_FPR11(\thread) | |
115 | sdc1 $f13, THREAD_FPR13(\thread) | |
116 | sdc1 $f15, THREAD_FPR15(\thread) | |
117 | sdc1 $f17, THREAD_FPR17(\thread) | |
118 | sdc1 $f19, THREAD_FPR19(\thread) | |
119 | sdc1 $f21, THREAD_FPR21(\thread) | |
120 | sdc1 $f23, THREAD_FPR23(\thread) | |
121 | sdc1 $f25, THREAD_FPR25(\thread) | |
122 | sdc1 $f27, THREAD_FPR27(\thread) | |
123 | sdc1 $f29, THREAD_FPR29(\thread) | |
124 | sdc1 $f31, THREAD_FPR31(\thread) | |
597ce172 PB |
125 | .set pop |
126 | .endm | |
127 | ||
128 | .macro fpu_save_double thread status tmp | |
207083b1 LY |
129 | #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \ |
130 | defined(CONFIG_CPU_MIPS32_R6) | |
597ce172 PB |
131 | sll \tmp, \status, 5 |
132 | bgez \tmp, 10f | |
133 | fpu_save_16odd \thread | |
134 | 10: | |
135 | #endif | |
136 | fpu_save_16even \thread \tmp | |
137 | .endm | |
138 | ||
139 | .macro fpu_restore_16even thread tmp=t0 | |
842dfc11 ML |
140 | .set push |
141 | SET_HARDFLOAT | |
597ce172 | 142 | lw \tmp, THREAD_FCR31(\thread) |
466aec5f JH |
143 | ldc1 $f0, THREAD_FPR0(\thread) |
144 | ldc1 $f2, THREAD_FPR2(\thread) | |
145 | ldc1 $f4, THREAD_FPR4(\thread) | |
146 | ldc1 $f6, THREAD_FPR6(\thread) | |
147 | ldc1 $f8, THREAD_FPR8(\thread) | |
148 | ldc1 $f10, THREAD_FPR10(\thread) | |
149 | ldc1 $f12, THREAD_FPR12(\thread) | |
150 | ldc1 $f14, THREAD_FPR14(\thread) | |
151 | ldc1 $f16, THREAD_FPR16(\thread) | |
152 | ldc1 $f18, THREAD_FPR18(\thread) | |
153 | ldc1 $f20, THREAD_FPR20(\thread) | |
154 | ldc1 $f22, THREAD_FPR22(\thread) | |
155 | ldc1 $f24, THREAD_FPR24(\thread) | |
156 | ldc1 $f26, THREAD_FPR26(\thread) | |
157 | ldc1 $f28, THREAD_FPR28(\thread) | |
158 | ldc1 $f30, THREAD_FPR30(\thread) | |
597ce172 | 159 | ctc1 \tmp, fcr31 |
3cbc6fc9 | 160 | .set pop |
597ce172 PB |
161 | .endm |
162 | ||
163 | .macro fpu_restore_16odd thread | |
164 | .set push | |
165 | .set mips64r2 | |
842dfc11 | 166 | SET_HARDFLOAT |
466aec5f JH |
167 | ldc1 $f1, THREAD_FPR1(\thread) |
168 | ldc1 $f3, THREAD_FPR3(\thread) | |
169 | ldc1 $f5, THREAD_FPR5(\thread) | |
170 | ldc1 $f7, THREAD_FPR7(\thread) | |
171 | ldc1 $f9, THREAD_FPR9(\thread) | |
172 | ldc1 $f11, THREAD_FPR11(\thread) | |
173 | ldc1 $f13, THREAD_FPR13(\thread) | |
174 | ldc1 $f15, THREAD_FPR15(\thread) | |
175 | ldc1 $f17, THREAD_FPR17(\thread) | |
176 | ldc1 $f19, THREAD_FPR19(\thread) | |
177 | ldc1 $f21, THREAD_FPR21(\thread) | |
178 | ldc1 $f23, THREAD_FPR23(\thread) | |
179 | ldc1 $f25, THREAD_FPR25(\thread) | |
180 | ldc1 $f27, THREAD_FPR27(\thread) | |
181 | ldc1 $f29, THREAD_FPR29(\thread) | |
182 | ldc1 $f31, THREAD_FPR31(\thread) | |
597ce172 PB |
183 | .set pop |
184 | .endm | |
185 | ||
186 | .macro fpu_restore_double thread status tmp | |
207083b1 LY |
187 | #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \ |
188 | defined(CONFIG_CPU_MIPS32_R6) | |
597ce172 PB |
189 | sll \tmp, \status, 5 |
190 | bgez \tmp, 10f # 16 register mode? | |
191 | ||
192 | fpu_restore_16odd \thread | |
193 | 10: | |
194 | #endif | |
195 | fpu_restore_16even \thread \tmp | |
196 | .endm | |
197 | ||
207083b1 | 198 | #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) |
1d688087 PB |
199 | .macro _EXT rd, rs, p, s |
200 | ext \rd, \rs, \p, \s | |
201 | .endm | |
207083b1 | 202 | #else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */ |
1d688087 PB |
203 | .macro _EXT rd, rs, p, s |
204 | srl \rd, \rs, \p | |
205 | andi \rd, \rd, (1 << \s) - 1 | |
206 | .endm | |
207083b1 | 207 | #endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */ |
1d688087 | 208 | |
41c594ab RB |
209 | /* |
210 | * Temporary until all gas have MT ASE support | |
211 | */ | |
212 | .macro DMT reg=0 | |
49a89efb | 213 | .word 0x41600bc1 | (\reg << 16) |
41c594ab RB |
214 | .endm |
215 | ||
216 | .macro EMT reg=0 | |
49a89efb | 217 | .word 0x41600be1 | (\reg << 16) |
41c594ab RB |
218 | .endm |
219 | ||
220 | .macro DVPE reg=0 | |
49a89efb | 221 | .word 0x41600001 | (\reg << 16) |
41c594ab RB |
222 | .endm |
223 | ||
224 | .macro EVPE reg=0 | |
49a89efb | 225 | .word 0x41600021 | (\reg << 16) |
41c594ab RB |
226 | .endm |
227 | ||
228 | .macro MFTR rt=0, rd=0, u=0, sel=0 | |
49a89efb | 229 | .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) |
41c594ab RB |
230 | .endm |
231 | ||
232 | .macro MTTR rt=0, rd=0, u=0, sel=0 | |
49a89efb | 233 | .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) |
41c594ab RB |
234 | .endm |
235 | ||
7f65afb9 | 236 | #ifdef TOOLCHAIN_SUPPORTS_MSA |
2bd7bc25 MC |
237 | /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ |
238 | #undef fp | |
239 | ||
e1bebbab PB |
240 | .macro _cfcmsa rd, cs |
241 | .set push | |
242 | .set mips32r2 | |
2bd7bc25 | 243 | .set fp=64 |
e1bebbab PB |
244 | .set msa |
245 | cfcmsa \rd, $\cs | |
246 | .set pop | |
247 | .endm | |
248 | ||
249 | .macro _ctcmsa cd, rs | |
250 | .set push | |
251 | .set mips32r2 | |
2bd7bc25 | 252 | .set fp=64 |
e1bebbab PB |
253 | .set msa |
254 | ctcmsa $\cd, \rs | |
255 | .set pop | |
256 | .endm | |
257 | ||
6b35e114 PB |
258 | .macro ld_b wd, off, base |
259 | .set push | |
260 | .set mips32r2 | |
92e9953c | 261 | .set fp=64 |
6b35e114 PB |
262 | .set msa |
263 | ld.b $w\wd, \off(\base) | |
264 | .set pop | |
265 | .endm | |
266 | ||
267 | .macro ld_h wd, off, base | |
268 | .set push | |
269 | .set mips32r2 | |
92e9953c | 270 | .set fp=64 |
6b35e114 PB |
271 | .set msa |
272 | ld.h $w\wd, \off(\base) | |
273 | .set pop | |
274 | .endm | |
275 | ||
276 | .macro ld_w wd, off, base | |
277 | .set push | |
278 | .set mips32r2 | |
92e9953c | 279 | .set fp=64 |
6b35e114 PB |
280 | .set msa |
281 | ld.w $w\wd, \off(\base) | |
282 | .set pop | |
283 | .endm | |
284 | ||
7f65afb9 PB |
285 | .macro ld_d wd, off, base |
286 | .set push | |
287 | .set mips32r2 | |
2bd7bc25 | 288 | .set fp=64 |
7f65afb9 PB |
289 | .set msa |
290 | ld.d $w\wd, \off(\base) | |
291 | .set pop | |
292 | .endm | |
293 | ||
6b35e114 PB |
294 | .macro st_b wd, off, base |
295 | .set push | |
296 | .set mips32r2 | |
92e9953c | 297 | .set fp=64 |
6b35e114 PB |
298 | .set msa |
299 | st.b $w\wd, \off(\base) | |
300 | .set pop | |
301 | .endm | |
302 | ||
303 | .macro st_h wd, off, base | |
304 | .set push | |
305 | .set mips32r2 | |
92e9953c | 306 | .set fp=64 |
6b35e114 PB |
307 | .set msa |
308 | st.h $w\wd, \off(\base) | |
309 | .set pop | |
310 | .endm | |
311 | ||
312 | .macro st_w wd, off, base | |
313 | .set push | |
314 | .set mips32r2 | |
92e9953c | 315 | .set fp=64 |
6b35e114 PB |
316 | .set msa |
317 | st.w $w\wd, \off(\base) | |
318 | .set pop | |
319 | .endm | |
320 | ||
7f65afb9 PB |
321 | .macro st_d wd, off, base |
322 | .set push | |
323 | .set mips32r2 | |
2bd7bc25 | 324 | .set fp=64 |
7f65afb9 PB |
325 | .set msa |
326 | st.d $w\wd, \off(\base) | |
327 | .set pop | |
328 | .endm | |
329 | ||
8a3c8b48 | 330 | .macro copy_s_w ws, n |
7f65afb9 PB |
331 | .set push |
332 | .set mips32r2 | |
2bd7bc25 | 333 | .set fp=64 |
7f65afb9 | 334 | .set msa |
8a3c8b48 | 335 | copy_s.w $1, $w\ws[\n] |
7f65afb9 PB |
336 | .set pop |
337 | .endm | |
338 | ||
8a3c8b48 | 339 | .macro copy_s_d ws, n |
7f65afb9 PB |
340 | .set push |
341 | .set mips64r2 | |
2bd7bc25 | 342 | .set fp=64 |
7f65afb9 | 343 | .set msa |
8a3c8b48 | 344 | copy_s.d $1, $w\ws[\n] |
7f65afb9 PB |
345 | .set pop |
346 | .endm | |
347 | ||
f23ce388 | 348 | .macro insert_w wd, n |
7f65afb9 PB |
349 | .set push |
350 | .set mips32r2 | |
2bd7bc25 | 351 | .set fp=64 |
7f65afb9 | 352 | .set msa |
f23ce388 | 353 | insert.w $w\wd[\n], $1 |
7f65afb9 PB |
354 | .set pop |
355 | .endm | |
356 | ||
f23ce388 | 357 | .macro insert_d wd, n |
7f65afb9 PB |
358 | .set push |
359 | .set mips64r2 | |
2bd7bc25 | 360 | .set fp=64 |
7f65afb9 | 361 | .set msa |
f23ce388 | 362 | insert.d $w\wd[\n], $1 |
7f65afb9 PB |
363 | .set pop |
364 | .endm | |
365 | #else | |
d96cc3d1 | 366 | |
7f65afb9 PB |
367 | /* |
368 | * Temporary until all toolchains in use include MSA support. | |
369 | */ | |
e1bebbab | 370 | .macro _cfcmsa rd, cs |
7f65afb9 PB |
371 | .set push |
372 | .set noat | |
842dfc11 | 373 | SET_HARDFLOAT |
6e1b29c3 JH |
374 | insn_if_mips 0x787e0059 | (\cs << 11) |
375 | insn32_if_mm 0x587e0056 | (\cs << 11) | |
7f65afb9 PB |
376 | move \rd, $1 |
377 | .set pop | |
378 | .endm | |
379 | ||
e1bebbab | 380 | .macro _ctcmsa cd, rs |
7f65afb9 PB |
381 | .set push |
382 | .set noat | |
842dfc11 | 383 | SET_HARDFLOAT |
7f65afb9 | 384 | move $1, \rs |
6e1b29c3 JH |
385 | insn_if_mips 0x783e0819 | (\cd << 6) |
386 | insn32_if_mm 0x583e0816 | (\cd << 6) | |
7f65afb9 PB |
387 | .set pop |
388 | .endm | |
389 | ||
6b35e114 PB |
390 | .macro ld_b wd, off, base |
391 | .set push | |
392 | .set noat | |
393 | SET_HARDFLOAT | |
ea168857 | 394 | PTR_ADDU $1, \base, \off |
6e1b29c3 JH |
395 | insn_if_mips 0x78000820 | (\wd << 6) |
396 | insn32_if_mm 0x58000807 | (\wd << 6) | |
6b35e114 PB |
397 | .set pop |
398 | .endm | |
399 | ||
400 | .macro ld_h wd, off, base | |
401 | .set push | |
402 | .set noat | |
403 | SET_HARDFLOAT | |
ea168857 | 404 | PTR_ADDU $1, \base, \off |
6e1b29c3 JH |
405 | insn_if_mips 0x78000821 | (\wd << 6) |
406 | insn32_if_mm 0x58000817 | (\wd << 6) | |
6b35e114 PB |
407 | .set pop |
408 | .endm | |
409 | ||
410 | .macro ld_w wd, off, base | |
411 | .set push | |
412 | .set noat | |
413 | SET_HARDFLOAT | |
ea168857 | 414 | PTR_ADDU $1, \base, \off |
6e1b29c3 JH |
415 | insn_if_mips 0x78000822 | (\wd << 6) |
416 | insn32_if_mm 0x58000827 | (\wd << 6) | |
6b35e114 PB |
417 | .set pop |
418 | .endm | |
419 | ||
7f65afb9 PB |
420 | .macro ld_d wd, off, base |
421 | .set push | |
422 | .set noat | |
842dfc11 | 423 | SET_HARDFLOAT |
ea168857 | 424 | PTR_ADDU $1, \base, \off |
6e1b29c3 JH |
425 | insn_if_mips 0x78000823 | (\wd << 6) |
426 | insn32_if_mm 0x58000837 | (\wd << 6) | |
7f65afb9 PB |
427 | .set pop |
428 | .endm | |
429 | ||
6b35e114 PB |
430 | .macro st_b wd, off, base |
431 | .set push | |
432 | .set noat | |
433 | SET_HARDFLOAT | |
ea168857 | 434 | PTR_ADDU $1, \base, \off |
6e1b29c3 JH |
435 | insn_if_mips 0x78000824 | (\wd << 6) |
436 | insn32_if_mm 0x5800080f | (\wd << 6) | |
6b35e114 PB |
437 | .set pop |
438 | .endm | |
439 | ||
440 | .macro st_h wd, off, base | |
441 | .set push | |
442 | .set noat | |
443 | SET_HARDFLOAT | |
ea168857 | 444 | PTR_ADDU $1, \base, \off |
6e1b29c3 JH |
445 | insn_if_mips 0x78000825 | (\wd << 6) |
446 | insn32_if_mm 0x5800081f | (\wd << 6) | |
6b35e114 PB |
447 | .set pop |
448 | .endm | |
449 | ||
450 | .macro st_w wd, off, base | |
451 | .set push | |
452 | .set noat | |
453 | SET_HARDFLOAT | |
ea168857 | 454 | PTR_ADDU $1, \base, \off |
6e1b29c3 JH |
455 | insn_if_mips 0x78000826 | (\wd << 6) |
456 | insn32_if_mm 0x5800082f | (\wd << 6) | |
6b35e114 PB |
457 | .set pop |
458 | .endm | |
459 | ||
7f65afb9 PB |
460 | .macro st_d wd, off, base |
461 | .set push | |
462 | .set noat | |
842dfc11 | 463 | SET_HARDFLOAT |
ea168857 | 464 | PTR_ADDU $1, \base, \off |
6e1b29c3 JH |
465 | insn_if_mips 0x78000827 | (\wd << 6) |
466 | insn32_if_mm 0x5800083f | (\wd << 6) | |
7f65afb9 PB |
467 | .set pop |
468 | .endm | |
469 | ||
8a3c8b48 | 470 | .macro copy_s_w ws, n |
7f65afb9 PB |
471 | .set push |
472 | .set noat | |
842dfc11 | 473 | SET_HARDFLOAT |
6e1b29c3 JH |
474 | insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11) |
475 | insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11) | |
7f65afb9 PB |
476 | .set pop |
477 | .endm | |
478 | ||
8a3c8b48 | 479 | .macro copy_s_d ws, n |
7f65afb9 PB |
480 | .set push |
481 | .set noat | |
842dfc11 | 482 | SET_HARDFLOAT |
6e1b29c3 JH |
483 | insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11) |
484 | insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11) | |
7f65afb9 PB |
485 | .set pop |
486 | .endm | |
487 | ||
f23ce388 | 488 | .macro insert_w wd, n |
7f65afb9 PB |
489 | .set push |
490 | .set noat | |
842dfc11 | 491 | SET_HARDFLOAT |
6e1b29c3 JH |
492 | insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6) |
493 | insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6) | |
7f65afb9 PB |
494 | .set pop |
495 | .endm | |
496 | ||
f23ce388 | 497 | .macro insert_d wd, n |
7f65afb9 PB |
498 | .set push |
499 | .set noat | |
842dfc11 | 500 | SET_HARDFLOAT |
6e1b29c3 JH |
501 | insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6) |
502 | insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6) | |
7f65afb9 PB |
503 | .set pop |
504 | .endm | |
505 | #endif | |
506 | ||
143e93d7 JH |
507 | #ifdef TOOLCHAIN_SUPPORTS_MSA |
508 | #define FPR_BASE_OFFS THREAD_FPR0 | |
509 | #define FPR_BASE $1 | |
510 | #else | |
511 | #define FPR_BASE_OFFS 0 | |
512 | #define FPR_BASE \thread | |
513 | #endif | |
514 | ||
1db1af84 | 515 | .macro msa_save_all thread |
f7a46fa7 PB |
516 | .set push |
517 | .set noat | |
143e93d7 JH |
518 | #ifdef TOOLCHAIN_SUPPORTS_MSA |
519 | PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS | |
520 | #endif | |
521 | st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE | |
522 | st_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE | |
523 | st_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE | |
524 | st_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE | |
525 | st_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE | |
526 | st_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE | |
527 | st_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE | |
528 | st_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE | |
529 | st_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE | |
530 | st_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE | |
531 | st_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE | |
532 | st_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE | |
533 | st_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE | |
534 | st_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE | |
535 | st_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE | |
536 | st_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE | |
537 | st_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE | |
538 | st_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE | |
539 | st_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE | |
540 | st_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE | |
541 | st_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE | |
542 | st_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE | |
543 | st_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE | |
544 | st_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE | |
545 | st_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE | |
546 | st_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE | |
547 | st_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE | |
548 | st_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE | |
549 | st_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE | |
550 | st_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE | |
551 | st_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE | |
552 | st_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE | |
842dfc11 | 553 | SET_HARDFLOAT |
e1bebbab | 554 | _cfcmsa $1, MSA_CSR |
f7a46fa7 PB |
555 | sw $1, THREAD_MSA_CSR(\thread) |
556 | .set pop | |
1db1af84 PB |
557 | .endm |
558 | ||
559 | .macro msa_restore_all thread | |
f7a46fa7 PB |
560 | .set push |
561 | .set noat | |
842dfc11 | 562 | SET_HARDFLOAT |
f7a46fa7 | 563 | lw $1, THREAD_MSA_CSR(\thread) |
e1bebbab | 564 | _ctcmsa MSA_CSR, $1 |
143e93d7 JH |
565 | #ifdef TOOLCHAIN_SUPPORTS_MSA |
566 | PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS | |
567 | #endif | |
568 | ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE | |
569 | ld_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE | |
570 | ld_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE | |
571 | ld_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE | |
572 | ld_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE | |
573 | ld_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE | |
574 | ld_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE | |
575 | ld_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE | |
576 | ld_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE | |
577 | ld_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE | |
578 | ld_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE | |
579 | ld_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE | |
580 | ld_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE | |
581 | ld_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE | |
582 | ld_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE | |
583 | ld_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE | |
584 | ld_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE | |
585 | ld_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE | |
586 | ld_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE | |
587 | ld_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE | |
588 | ld_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE | |
589 | ld_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE | |
590 | ld_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE | |
591 | ld_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE | |
592 | ld_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE | |
593 | ld_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE | |
594 | ld_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE | |
595 | ld_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE | |
596 | ld_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE | |
597 | ld_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE | |
598 | ld_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE | |
599 | ld_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE | |
600 | .set pop | |
601 | .endm | |
602 | ||
603 | #undef FPR_BASE_OFFS | |
604 | #undef FPR_BASE | |
1db1af84 | 605 | |
c9017757 PB |
606 | .macro msa_init_upper wd |
607 | #ifdef CONFIG_64BIT | |
608 | insert_d \wd, 1 | |
609 | #else | |
610 | insert_w \wd, 2 | |
611 | insert_w \wd, 3 | |
612 | #endif | |
c9017757 PB |
613 | .endm |
614 | ||
615 | .macro msa_init_all_upper | |
616 | .set push | |
617 | .set noat | |
842dfc11 | 618 | SET_HARDFLOAT |
c9017757 PB |
619 | not $1, zero |
620 | msa_init_upper 0 | |
a3a49810 PB |
621 | msa_init_upper 1 |
622 | msa_init_upper 2 | |
623 | msa_init_upper 3 | |
624 | msa_init_upper 4 | |
625 | msa_init_upper 5 | |
626 | msa_init_upper 6 | |
627 | msa_init_upper 7 | |
628 | msa_init_upper 8 | |
629 | msa_init_upper 9 | |
630 | msa_init_upper 10 | |
631 | msa_init_upper 11 | |
632 | msa_init_upper 12 | |
633 | msa_init_upper 13 | |
634 | msa_init_upper 14 | |
635 | msa_init_upper 15 | |
636 | msa_init_upper 16 | |
637 | msa_init_upper 17 | |
638 | msa_init_upper 18 | |
639 | msa_init_upper 19 | |
640 | msa_init_upper 20 | |
641 | msa_init_upper 21 | |
642 | msa_init_upper 22 | |
643 | msa_init_upper 23 | |
644 | msa_init_upper 24 | |
645 | msa_init_upper 25 | |
646 | msa_init_upper 26 | |
647 | msa_init_upper 27 | |
648 | msa_init_upper 28 | |
649 | msa_init_upper 29 | |
650 | msa_init_upper 30 | |
651 | msa_init_upper 31 | |
c9017757 PB |
652 | .set pop |
653 | .endm | |
654 | ||
1da177e4 | 655 | #endif /* _ASM_ASMMACRO_H */ |