Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
902d21d5 | 2 | * System-specific setup, especially interrupts. |
1da177e4 LT |
3 | * |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 1998 Harald Koerfgen | |
902d21d5 | 9 | * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki |
1da177e4 | 10 | */ |
1da177e4 LT |
11 | #include <linux/console.h> |
12 | #include <linux/init.h> | |
902d21d5 MR |
13 | #include <linux/interrupt.h> |
14 | #include <linux/ioport.h> | |
f02cf469 MR |
15 | #include <linux/irq.h> |
16 | #include <linux/irqnr.h> | |
1da177e4 | 17 | #include <linux/module.h> |
902d21d5 | 18 | #include <linux/param.h> |
f02cf469 | 19 | #include <linux/percpu-defs.h> |
902d21d5 | 20 | #include <linux/sched.h> |
1da177e4 LT |
21 | #include <linux/spinlock.h> |
22 | #include <linux/types.h> | |
fcdb27ad | 23 | #include <linux/pm.h> |
1da177e4 LT |
24 | |
25 | #include <asm/bootinfo.h> | |
26 | #include <asm/cpu.h> | |
27 | #include <asm/cpu-features.h> | |
76ad023b | 28 | #include <asm/cpu-type.h> |
1da177e4 LT |
29 | #include <asm/irq.h> |
30 | #include <asm/irq_cpu.h> | |
31 | #include <asm/mipsregs.h> | |
32 | #include <asm/reboot.h> | |
33 | #include <asm/time.h> | |
34 | #include <asm/traps.h> | |
35 | #include <asm/wbflush.h> | |
36 | ||
37 | #include <asm/dec/interrupts.h> | |
38 | #include <asm/dec/ioasic.h> | |
39 | #include <asm/dec/ioasic_addrs.h> | |
40 | #include <asm/dec/ioasic_ints.h> | |
41 | #include <asm/dec/kn01.h> | |
42 | #include <asm/dec/kn02.h> | |
43 | #include <asm/dec/kn02ba.h> | |
44 | #include <asm/dec/kn02ca.h> | |
45 | #include <asm/dec/kn03.h> | |
46 | #include <asm/dec/kn230.h> | |
a5fc9c0b | 47 | #include <asm/dec/system.h> |
1da177e4 LT |
48 | |
49 | ||
50 | extern void dec_machine_restart(char *command); | |
51 | extern void dec_machine_halt(void); | |
52 | extern void dec_machine_power_off(void); | |
d62801e9 | 53 | extern irqreturn_t dec_intr_halt(int irq, void *dev_id); |
1da177e4 | 54 | |
a5fc9c0b MR |
55 | unsigned long dec_kn_slot_base, dec_kn_slot_size; |
56 | ||
57 | EXPORT_SYMBOL(dec_kn_slot_base); | |
58 | EXPORT_SYMBOL(dec_kn_slot_size); | |
59 | ||
33cf45b9 MR |
60 | int dec_tc_bus; |
61 | ||
68835999 | 62 | DEFINE_SPINLOCK(ioasic_ssr_lock); |
1da177e4 LT |
63 | |
64 | volatile u32 *ioasic_base; | |
a5fc9c0b MR |
65 | |
66 | EXPORT_SYMBOL(ioasic_base); | |
1da177e4 LT |
67 | |
68 | /* | |
69 | * IRQ routing and priority tables. Priorites are set as follows: | |
70 | * | |
07217d75 | 71 | * KN01 KN230 KN02 KN02-BA KN02-CA KN03 |
1da177e4 LT |
72 | * |
73 | * MEMORY CPU CPU CPU ASIC CPU CPU | |
74 | * RTC CPU CPU CPU ASIC CPU CPU | |
75 | * DMA - - - ASIC ASIC ASIC | |
76 | * SERIAL0 CPU CPU CSR ASIC ASIC ASIC | |
77 | * SERIAL1 - - - ASIC - ASIC | |
78 | * SCSI CPU CPU CSR ASIC ASIC ASIC | |
79 | * ETHERNET CPU * CSR ASIC ASIC ASIC | |
80 | * other - - - ASIC - - | |
81 | * TC2 - - CSR CPU ASIC ASIC | |
82 | * TC1 - - CSR CPU ASIC ASIC | |
83 | * TC0 - - CSR CPU ASIC ASIC | |
84 | * other - CPU - CPU ASIC ASIC | |
85 | * other - - - - CPU CPU | |
86 | * | |
87 | * * -- shared with SCSI | |
88 | */ | |
89 | ||
90 | int dec_interrupt[DEC_NR_INTS] = { | |
91 | [0 ... DEC_NR_INTS - 1] = -1 | |
92 | }; | |
a5fc9c0b MR |
93 | |
94 | EXPORT_SYMBOL(dec_interrupt); | |
95 | ||
1da177e4 LT |
96 | int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { |
97 | { { .i = ~0 }, { .p = dec_intr_unimplemented } }, | |
98 | }; | |
99 | int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = { | |
100 | { { .i = ~0 }, { .p = asic_intr_unimplemented } }, | |
101 | }; | |
102 | int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU); | |
f02cf469 | 103 | int *fpu_kstat_irq; |
1da177e4 LT |
104 | |
105 | static struct irqaction ioirq = { | |
106 | .handler = no_action, | |
107 | .name = "cascade", | |
5a4a4ad8 | 108 | .flags = IRQF_NO_THREAD, |
1da177e4 LT |
109 | }; |
110 | static struct irqaction fpuirq = { | |
111 | .handler = no_action, | |
112 | .name = "fpu", | |
5a4a4ad8 | 113 | .flags = IRQF_NO_THREAD, |
1da177e4 LT |
114 | }; |
115 | ||
116 | static struct irqaction busirq = { | |
1da177e4 | 117 | .name = "bus error", |
5a4a4ad8 | 118 | .flags = IRQF_NO_THREAD, |
1da177e4 LT |
119 | }; |
120 | ||
121 | static struct irqaction haltirq = { | |
122 | .handler = dec_intr_halt, | |
123 | .name = "halt", | |
5a4a4ad8 | 124 | .flags = IRQF_NO_THREAD, |
1da177e4 LT |
125 | }; |
126 | ||
127 | ||
128 | /* | |
129 | * Bus error (DBE/IBE exceptions and bus interrupts) handling setup. | |
130 | */ | |
23bbbaf8 | 131 | static void __init dec_be_init(void) |
1da177e4 LT |
132 | { |
133 | switch (mips_machtype) { | |
134 | case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ | |
64dac503 MR |
135 | board_be_handler = dec_kn01_be_handler; |
136 | busirq.handler = dec_kn01_be_interrupt; | |
f40298fd | 137 | busirq.flags |= IRQF_SHARED; |
64dac503 MR |
138 | dec_kn01_be_init(); |
139 | break; | |
140 | case MACH_DS5000_1XX: /* DS5000/1xx 3min */ | |
141 | case MACH_DS5000_XX: /* DS5000/xx Maxine */ | |
142 | board_be_handler = dec_kn02xa_be_handler; | |
143 | busirq.handler = dec_kn02xa_be_interrupt; | |
144 | dec_kn02xa_be_init(); | |
1da177e4 LT |
145 | break; |
146 | case MACH_DS5000_200: /* DS5000/200 3max */ | |
147 | case MACH_DS5000_2X0: /* DS5000/240 3max+ */ | |
148 | case MACH_DS5900: /* DS5900 bigmax */ | |
149 | board_be_handler = dec_ecc_be_handler; | |
150 | busirq.handler = dec_ecc_be_interrupt; | |
151 | dec_ecc_be_init(); | |
152 | break; | |
153 | } | |
154 | } | |
155 | ||
2925aba4 | 156 | void __init plat_mem_setup(void) |
1da177e4 LT |
157 | { |
158 | board_be_init = dec_be_init; | |
1da177e4 LT |
159 | |
160 | wbflush_setup(); | |
161 | ||
162 | _machine_restart = dec_machine_restart; | |
163 | _machine_halt = dec_machine_halt; | |
fcdb27ad | 164 | pm_power_off = dec_machine_power_off; |
902d21d5 MR |
165 | |
166 | ioport_resource.start = ~0UL; | |
167 | ioport_resource.end = 0UL; | |
1da177e4 LT |
168 | } |
169 | ||
1da177e4 LT |
170 | /* |
171 | * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin) | |
172 | * or DS3100 (aka Pmax). | |
173 | */ | |
174 | static int kn01_interrupt[DEC_NR_INTS] __initdata = { | |
175 | [DEC_IRQ_CASCADE] = -1, | |
176 | [DEC_IRQ_AB_RECV] = -1, | |
177 | [DEC_IRQ_AB_XMIT] = -1, | |
178 | [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11), | |
179 | [DEC_IRQ_ASC] = -1, | |
180 | [DEC_IRQ_FLOPPY] = -1, | |
181 | [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), | |
182 | [DEC_IRQ_HALT] = -1, | |
183 | [DEC_IRQ_ISDN] = -1, | |
184 | [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE), | |
185 | [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS), | |
186 | [DEC_IRQ_PSU] = -1, | |
187 | [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC), | |
188 | [DEC_IRQ_SCC0] = -1, | |
189 | [DEC_IRQ_SCC1] = -1, | |
190 | [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII), | |
191 | [DEC_IRQ_TC0] = -1, | |
192 | [DEC_IRQ_TC1] = -1, | |
193 | [DEC_IRQ_TC2] = -1, | |
194 | [DEC_IRQ_TIMER] = -1, | |
195 | [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO), | |
196 | [DEC_IRQ_ASC_MERR] = -1, | |
197 | [DEC_IRQ_ASC_ERR] = -1, | |
198 | [DEC_IRQ_ASC_DMA] = -1, | |
199 | [DEC_IRQ_FLOPPY_ERR] = -1, | |
200 | [DEC_IRQ_ISDN_ERR] = -1, | |
201 | [DEC_IRQ_ISDN_RXDMA] = -1, | |
202 | [DEC_IRQ_ISDN_TXDMA] = -1, | |
203 | [DEC_IRQ_LANCE_MERR] = -1, | |
204 | [DEC_IRQ_SCC0A_RXERR] = -1, | |
205 | [DEC_IRQ_SCC0A_RXDMA] = -1, | |
206 | [DEC_IRQ_SCC0A_TXERR] = -1, | |
207 | [DEC_IRQ_SCC0A_TXDMA] = -1, | |
208 | [DEC_IRQ_AB_RXERR] = -1, | |
209 | [DEC_IRQ_AB_RXDMA] = -1, | |
210 | [DEC_IRQ_AB_TXERR] = -1, | |
211 | [DEC_IRQ_AB_TXDMA] = -1, | |
212 | [DEC_IRQ_SCC1A_RXERR] = -1, | |
213 | [DEC_IRQ_SCC1A_RXDMA] = -1, | |
214 | [DEC_IRQ_SCC1A_TXERR] = -1, | |
215 | [DEC_IRQ_SCC1A_TXDMA] = -1, | |
216 | }; | |
217 | ||
218 | static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = { | |
219 | { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) }, | |
220 | { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } }, | |
221 | { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) }, | |
222 | { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } }, | |
223 | { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) }, | |
224 | { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } }, | |
225 | { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) }, | |
226 | { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } }, | |
227 | { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) }, | |
228 | { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } }, | |
229 | { { .i = DEC_CPU_IRQ_ALL }, | |
230 | { .p = cpu_all_int } }, | |
231 | }; | |
232 | ||
23bbbaf8 | 233 | static void __init dec_init_kn01(void) |
1da177e4 LT |
234 | { |
235 | /* IRQ routing. */ | |
236 | memcpy(&dec_interrupt, &kn01_interrupt, | |
237 | sizeof(kn01_interrupt)); | |
238 | ||
239 | /* CPU IRQ priorities. */ | |
240 | memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl, | |
241 | sizeof(kn01_cpu_mask_nr_tbl)); | |
242 | ||
97dcb82d | 243 | mips_cpu_irq_init(); |
1da177e4 LT |
244 | |
245 | } /* dec_init_kn01 */ | |
246 | ||
247 | ||
248 | /* | |
249 | * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate. | |
250 | */ | |
251 | static int kn230_interrupt[DEC_NR_INTS] __initdata = { | |
252 | [DEC_IRQ_CASCADE] = -1, | |
253 | [DEC_IRQ_AB_RECV] = -1, | |
254 | [DEC_IRQ_AB_XMIT] = -1, | |
255 | [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11), | |
256 | [DEC_IRQ_ASC] = -1, | |
257 | [DEC_IRQ_FLOPPY] = -1, | |
258 | [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), | |
259 | [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT), | |
260 | [DEC_IRQ_ISDN] = -1, | |
261 | [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE), | |
262 | [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS), | |
263 | [DEC_IRQ_PSU] = -1, | |
264 | [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC), | |
265 | [DEC_IRQ_SCC0] = -1, | |
266 | [DEC_IRQ_SCC1] = -1, | |
267 | [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII), | |
268 | [DEC_IRQ_TC0] = -1, | |
269 | [DEC_IRQ_TC1] = -1, | |
270 | [DEC_IRQ_TC2] = -1, | |
271 | [DEC_IRQ_TIMER] = -1, | |
272 | [DEC_IRQ_VIDEO] = -1, | |
273 | [DEC_IRQ_ASC_MERR] = -1, | |
274 | [DEC_IRQ_ASC_ERR] = -1, | |
275 | [DEC_IRQ_ASC_DMA] = -1, | |
276 | [DEC_IRQ_FLOPPY_ERR] = -1, | |
277 | [DEC_IRQ_ISDN_ERR] = -1, | |
278 | [DEC_IRQ_ISDN_RXDMA] = -1, | |
279 | [DEC_IRQ_ISDN_TXDMA] = -1, | |
280 | [DEC_IRQ_LANCE_MERR] = -1, | |
281 | [DEC_IRQ_SCC0A_RXERR] = -1, | |
282 | [DEC_IRQ_SCC0A_RXDMA] = -1, | |
283 | [DEC_IRQ_SCC0A_TXERR] = -1, | |
284 | [DEC_IRQ_SCC0A_TXDMA] = -1, | |
285 | [DEC_IRQ_AB_RXERR] = -1, | |
286 | [DEC_IRQ_AB_RXDMA] = -1, | |
287 | [DEC_IRQ_AB_TXERR] = -1, | |
288 | [DEC_IRQ_AB_TXDMA] = -1, | |
289 | [DEC_IRQ_SCC1A_RXERR] = -1, | |
290 | [DEC_IRQ_SCC1A_RXDMA] = -1, | |
291 | [DEC_IRQ_SCC1A_TXERR] = -1, | |
292 | [DEC_IRQ_SCC1A_TXDMA] = -1, | |
293 | }; | |
294 | ||
295 | static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = { | |
296 | { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) }, | |
297 | { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } }, | |
298 | { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) }, | |
299 | { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } }, | |
300 | { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) }, | |
301 | { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } }, | |
302 | { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) }, | |
303 | { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } }, | |
304 | { { .i = DEC_CPU_IRQ_ALL }, | |
305 | { .p = cpu_all_int } }, | |
306 | }; | |
307 | ||
23bbbaf8 | 308 | static void __init dec_init_kn230(void) |
1da177e4 LT |
309 | { |
310 | /* IRQ routing. */ | |
311 | memcpy(&dec_interrupt, &kn230_interrupt, | |
312 | sizeof(kn230_interrupt)); | |
313 | ||
314 | /* CPU IRQ priorities. */ | |
315 | memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl, | |
316 | sizeof(kn230_cpu_mask_nr_tbl)); | |
317 | ||
97dcb82d | 318 | mips_cpu_irq_init(); |
1da177e4 LT |
319 | |
320 | } /* dec_init_kn230 */ | |
321 | ||
322 | ||
323 | /* | |
324 | * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max. | |
325 | */ | |
326 | static int kn02_interrupt[DEC_NR_INTS] __initdata = { | |
327 | [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE), | |
328 | [DEC_IRQ_AB_RECV] = -1, | |
329 | [DEC_IRQ_AB_XMIT] = -1, | |
330 | [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11), | |
331 | [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC), | |
332 | [DEC_IRQ_FLOPPY] = -1, | |
333 | [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), | |
334 | [DEC_IRQ_HALT] = -1, | |
335 | [DEC_IRQ_ISDN] = -1, | |
336 | [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE), | |
337 | [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS), | |
338 | [DEC_IRQ_PSU] = -1, | |
339 | [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC), | |
340 | [DEC_IRQ_SCC0] = -1, | |
341 | [DEC_IRQ_SCC1] = -1, | |
342 | [DEC_IRQ_SII] = -1, | |
343 | [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0), | |
344 | [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1), | |
345 | [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2), | |
346 | [DEC_IRQ_TIMER] = -1, | |
347 | [DEC_IRQ_VIDEO] = -1, | |
348 | [DEC_IRQ_ASC_MERR] = -1, | |
349 | [DEC_IRQ_ASC_ERR] = -1, | |
350 | [DEC_IRQ_ASC_DMA] = -1, | |
351 | [DEC_IRQ_FLOPPY_ERR] = -1, | |
352 | [DEC_IRQ_ISDN_ERR] = -1, | |
353 | [DEC_IRQ_ISDN_RXDMA] = -1, | |
354 | [DEC_IRQ_ISDN_TXDMA] = -1, | |
355 | [DEC_IRQ_LANCE_MERR] = -1, | |
356 | [DEC_IRQ_SCC0A_RXERR] = -1, | |
357 | [DEC_IRQ_SCC0A_RXDMA] = -1, | |
358 | [DEC_IRQ_SCC0A_TXERR] = -1, | |
359 | [DEC_IRQ_SCC0A_TXDMA] = -1, | |
360 | [DEC_IRQ_AB_RXERR] = -1, | |
361 | [DEC_IRQ_AB_RXDMA] = -1, | |
362 | [DEC_IRQ_AB_TXERR] = -1, | |
363 | [DEC_IRQ_AB_TXDMA] = -1, | |
364 | [DEC_IRQ_SCC1A_RXERR] = -1, | |
365 | [DEC_IRQ_SCC1A_RXDMA] = -1, | |
366 | [DEC_IRQ_SCC1A_TXERR] = -1, | |
367 | [DEC_IRQ_SCC1A_TXDMA] = -1, | |
368 | }; | |
369 | ||
370 | static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = { | |
371 | { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) }, | |
372 | { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } }, | |
373 | { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) }, | |
374 | { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } }, | |
375 | { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) }, | |
376 | { .p = kn02_io_int } }, | |
377 | { { .i = DEC_CPU_IRQ_ALL }, | |
378 | { .p = cpu_all_int } }, | |
379 | }; | |
380 | ||
381 | static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = { | |
382 | { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) }, | |
383 | { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } }, | |
384 | { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) }, | |
385 | { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } }, | |
386 | { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) }, | |
387 | { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } }, | |
388 | { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) }, | |
389 | { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } }, | |
390 | { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) }, | |
391 | { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } }, | |
392 | { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) }, | |
393 | { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } }, | |
394 | { { .i = KN02_IRQ_ALL }, | |
395 | { .p = kn02_all_int } }, | |
396 | }; | |
397 | ||
23bbbaf8 | 398 | static void __init dec_init_kn02(void) |
1da177e4 LT |
399 | { |
400 | /* IRQ routing. */ | |
401 | memcpy(&dec_interrupt, &kn02_interrupt, | |
402 | sizeof(kn02_interrupt)); | |
403 | ||
404 | /* CPU IRQ priorities. */ | |
405 | memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl, | |
406 | sizeof(kn02_cpu_mask_nr_tbl)); | |
407 | ||
408 | /* KN02 CSR IRQ priorities. */ | |
409 | memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl, | |
410 | sizeof(kn02_asic_mask_nr_tbl)); | |
411 | ||
97dcb82d | 412 | mips_cpu_irq_init(); |
1da177e4 LT |
413 | init_kn02_irqs(KN02_IRQ_BASE); |
414 | ||
415 | } /* dec_init_kn02 */ | |
416 | ||
417 | ||
418 | /* | |
419 | * Machine-specific initialisation for KN02-BA, aka DS5000/1xx | |
07217d75 | 420 | * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka |
1da177e4 LT |
421 | * DS5000/150, aka 4min. |
422 | */ | |
423 | static int kn02ba_interrupt[DEC_NR_INTS] __initdata = { | |
424 | [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE), | |
425 | [DEC_IRQ_AB_RECV] = -1, | |
426 | [DEC_IRQ_AB_XMIT] = -1, | |
427 | [DEC_IRQ_DZ11] = -1, | |
428 | [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC), | |
429 | [DEC_IRQ_FLOPPY] = -1, | |
430 | [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), | |
431 | [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT), | |
432 | [DEC_IRQ_ISDN] = -1, | |
433 | [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE), | |
434 | [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS), | |
435 | [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU), | |
436 | [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC), | |
437 | [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0), | |
438 | [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1), | |
439 | [DEC_IRQ_SII] = -1, | |
440 | [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0), | |
441 | [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1), | |
442 | [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2), | |
443 | [DEC_IRQ_TIMER] = -1, | |
444 | [DEC_IRQ_VIDEO] = -1, | |
445 | [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), | |
446 | [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), | |
447 | [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), | |
448 | [DEC_IRQ_FLOPPY_ERR] = -1, | |
449 | [DEC_IRQ_ISDN_ERR] = -1, | |
450 | [DEC_IRQ_ISDN_RXDMA] = -1, | |
451 | [DEC_IRQ_ISDN_TXDMA] = -1, | |
452 | [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), | |
453 | [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), | |
454 | [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), | |
455 | [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), | |
456 | [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), | |
457 | [DEC_IRQ_AB_RXERR] = -1, | |
458 | [DEC_IRQ_AB_RXDMA] = -1, | |
459 | [DEC_IRQ_AB_TXERR] = -1, | |
460 | [DEC_IRQ_AB_TXDMA] = -1, | |
461 | [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), | |
462 | [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), | |
463 | [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), | |
464 | [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), | |
465 | }; | |
466 | ||
467 | static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = { | |
468 | { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) }, | |
469 | { .p = kn02xa_io_int } }, | |
470 | { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) }, | |
471 | { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } }, | |
472 | { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) }, | |
473 | { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } }, | |
474 | { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) }, | |
475 | { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } }, | |
476 | { { .i = DEC_CPU_IRQ_ALL }, | |
477 | { .p = cpu_all_int } }, | |
478 | }; | |
479 | ||
480 | static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = { | |
481 | { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) }, | |
482 | { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } }, | |
483 | { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) }, | |
484 | { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } }, | |
485 | { { .i = IO_IRQ_DMA }, | |
486 | { .p = asic_dma_int } }, | |
487 | { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) }, | |
488 | { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } }, | |
489 | { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) }, | |
490 | { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } }, | |
491 | { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) }, | |
492 | { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } }, | |
493 | { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) }, | |
494 | { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } }, | |
495 | { { .i = IO_IRQ_ALL }, | |
496 | { .p = asic_all_int } }, | |
497 | }; | |
498 | ||
23bbbaf8 | 499 | static void __init dec_init_kn02ba(void) |
1da177e4 LT |
500 | { |
501 | /* IRQ routing. */ | |
502 | memcpy(&dec_interrupt, &kn02ba_interrupt, | |
503 | sizeof(kn02ba_interrupt)); | |
504 | ||
505 | /* CPU IRQ priorities. */ | |
506 | memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl, | |
507 | sizeof(kn02ba_cpu_mask_nr_tbl)); | |
508 | ||
509 | /* I/O ASIC IRQ priorities. */ | |
510 | memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl, | |
511 | sizeof(kn02ba_asic_mask_nr_tbl)); | |
512 | ||
97dcb82d | 513 | mips_cpu_irq_init(); |
1da177e4 LT |
514 | init_ioasic_irqs(IO_IRQ_BASE); |
515 | ||
516 | } /* dec_init_kn02ba */ | |
517 | ||
518 | ||
519 | /* | |
520 | * Machine-specific initialisation for KN02-CA, aka DS5000/xx, | |
521 | * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka | |
522 | * DS5000/50, aka 4MAXine. | |
523 | */ | |
524 | static int kn02ca_interrupt[DEC_NR_INTS] __initdata = { | |
525 | [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE), | |
526 | [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV), | |
527 | [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT), | |
528 | [DEC_IRQ_DZ11] = -1, | |
529 | [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC), | |
530 | [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY), | |
531 | [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), | |
532 | [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT), | |
533 | [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN), | |
534 | [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE), | |
535 | [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS), | |
536 | [DEC_IRQ_PSU] = -1, | |
537 | [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC), | |
538 | [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0), | |
539 | [DEC_IRQ_SCC1] = -1, | |
540 | [DEC_IRQ_SII] = -1, | |
541 | [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0), | |
542 | [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1), | |
543 | [DEC_IRQ_TC2] = -1, | |
544 | [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER), | |
545 | [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO), | |
546 | [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), | |
547 | [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), | |
548 | [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), | |
549 | [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR), | |
550 | [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR), | |
551 | [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA), | |
552 | [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA), | |
553 | [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), | |
554 | [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), | |
555 | [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), | |
556 | [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), | |
557 | [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), | |
558 | [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR), | |
559 | [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA), | |
560 | [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR), | |
561 | [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA), | |
562 | [DEC_IRQ_SCC1A_RXERR] = -1, | |
563 | [DEC_IRQ_SCC1A_RXDMA] = -1, | |
564 | [DEC_IRQ_SCC1A_TXERR] = -1, | |
565 | [DEC_IRQ_SCC1A_TXDMA] = -1, | |
566 | }; | |
567 | ||
568 | static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = { | |
569 | { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) }, | |
570 | { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } }, | |
571 | { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) }, | |
572 | { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } }, | |
573 | { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) }, | |
574 | { .p = kn02xa_io_int } }, | |
575 | { { .i = DEC_CPU_IRQ_ALL }, | |
576 | { .p = cpu_all_int } }, | |
577 | }; | |
578 | ||
579 | static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = { | |
580 | { { .i = IO_IRQ_DMA }, | |
581 | { .p = asic_dma_int } }, | |
582 | { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) }, | |
583 | { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } }, | |
584 | { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) }, | |
585 | { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } }, | |
586 | { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) }, | |
587 | { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } }, | |
588 | { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) }, | |
589 | { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } }, | |
590 | { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) }, | |
591 | { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } }, | |
592 | { { .i = IO_IRQ_ALL }, | |
593 | { .p = asic_all_int } }, | |
594 | }; | |
595 | ||
23bbbaf8 | 596 | static void __init dec_init_kn02ca(void) |
1da177e4 LT |
597 | { |
598 | /* IRQ routing. */ | |
599 | memcpy(&dec_interrupt, &kn02ca_interrupt, | |
600 | sizeof(kn02ca_interrupt)); | |
601 | ||
602 | /* CPU IRQ priorities. */ | |
603 | memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl, | |
604 | sizeof(kn02ca_cpu_mask_nr_tbl)); | |
605 | ||
606 | /* I/O ASIC IRQ priorities. */ | |
607 | memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl, | |
608 | sizeof(kn02ca_asic_mask_nr_tbl)); | |
609 | ||
97dcb82d | 610 | mips_cpu_irq_init(); |
1da177e4 LT |
611 | init_ioasic_irqs(IO_IRQ_BASE); |
612 | ||
613 | } /* dec_init_kn02ca */ | |
614 | ||
615 | ||
616 | /* | |
617 | * Machine-specific initialisation for KN03, aka DS5000/240, | |
618 | * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka | |
619 | * DS5000/260, aka 4max+ and DS5900/260. | |
620 | */ | |
621 | static int kn03_interrupt[DEC_NR_INTS] __initdata = { | |
622 | [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE), | |
623 | [DEC_IRQ_AB_RECV] = -1, | |
624 | [DEC_IRQ_AB_XMIT] = -1, | |
625 | [DEC_IRQ_DZ11] = -1, | |
626 | [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC), | |
627 | [DEC_IRQ_FLOPPY] = -1, | |
628 | [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), | |
629 | [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT), | |
630 | [DEC_IRQ_ISDN] = -1, | |
631 | [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE), | |
632 | [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS), | |
633 | [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU), | |
634 | [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC), | |
635 | [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0), | |
636 | [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1), | |
637 | [DEC_IRQ_SII] = -1, | |
638 | [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0), | |
639 | [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1), | |
640 | [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2), | |
641 | [DEC_IRQ_TIMER] = -1, | |
642 | [DEC_IRQ_VIDEO] = -1, | |
643 | [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), | |
644 | [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), | |
645 | [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), | |
646 | [DEC_IRQ_FLOPPY_ERR] = -1, | |
647 | [DEC_IRQ_ISDN_ERR] = -1, | |
648 | [DEC_IRQ_ISDN_RXDMA] = -1, | |
649 | [DEC_IRQ_ISDN_TXDMA] = -1, | |
650 | [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), | |
651 | [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), | |
652 | [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), | |
653 | [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), | |
654 | [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), | |
655 | [DEC_IRQ_AB_RXERR] = -1, | |
656 | [DEC_IRQ_AB_RXDMA] = -1, | |
657 | [DEC_IRQ_AB_TXERR] = -1, | |
658 | [DEC_IRQ_AB_TXDMA] = -1, | |
659 | [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), | |
660 | [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), | |
661 | [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), | |
662 | [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), | |
663 | }; | |
664 | ||
665 | static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = { | |
666 | { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) }, | |
667 | { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } }, | |
668 | { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) }, | |
669 | { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } }, | |
670 | { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) }, | |
671 | { .p = kn03_io_int } }, | |
672 | { { .i = DEC_CPU_IRQ_ALL }, | |
673 | { .p = cpu_all_int } }, | |
674 | }; | |
675 | ||
676 | static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = { | |
677 | { { .i = IO_IRQ_DMA }, | |
678 | { .p = asic_dma_int } }, | |
679 | { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) }, | |
680 | { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } }, | |
681 | { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) }, | |
682 | { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } }, | |
683 | { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) }, | |
684 | { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } }, | |
685 | { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) }, | |
686 | { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } }, | |
687 | { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) }, | |
688 | { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } }, | |
689 | { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) }, | |
690 | { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } }, | |
691 | { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) }, | |
692 | { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } }, | |
693 | { { .i = IO_IRQ_ALL }, | |
694 | { .p = asic_all_int } }, | |
695 | }; | |
696 | ||
23bbbaf8 | 697 | static void __init dec_init_kn03(void) |
1da177e4 LT |
698 | { |
699 | /* IRQ routing. */ | |
700 | memcpy(&dec_interrupt, &kn03_interrupt, | |
701 | sizeof(kn03_interrupt)); | |
702 | ||
703 | /* CPU IRQ priorities. */ | |
704 | memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl, | |
705 | sizeof(kn03_cpu_mask_nr_tbl)); | |
706 | ||
707 | /* I/O ASIC IRQ priorities. */ | |
708 | memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl, | |
709 | sizeof(kn03_asic_mask_nr_tbl)); | |
710 | ||
97dcb82d | 711 | mips_cpu_irq_init(); |
1da177e4 LT |
712 | init_ioasic_irqs(IO_IRQ_BASE); |
713 | ||
714 | } /* dec_init_kn03 */ | |
715 | ||
716 | ||
717 | void __init arch_init_irq(void) | |
718 | { | |
719 | switch (mips_machtype) { | |
720 | case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ | |
721 | dec_init_kn01(); | |
722 | break; | |
723 | case MACH_DS5100: /* DS5100 MIPSmate */ | |
724 | dec_init_kn230(); | |
725 | break; | |
726 | case MACH_DS5000_200: /* DS5000/200 3max */ | |
727 | dec_init_kn02(); | |
728 | break; | |
729 | case MACH_DS5000_1XX: /* DS5000/1xx 3min */ | |
730 | dec_init_kn02ba(); | |
731 | break; | |
732 | case MACH_DS5000_2X0: /* DS5000/240 3max+ */ | |
733 | case MACH_DS5900: /* DS5900 bigmax */ | |
734 | dec_init_kn03(); | |
735 | break; | |
736 | case MACH_DS5000_XX: /* Personal DS5000/xx */ | |
737 | dec_init_kn02ca(); | |
738 | break; | |
739 | case MACH_DS5800: /* DS5800 Isis */ | |
740 | panic("Don't know how to set this up!"); | |
741 | break; | |
742 | case MACH_DS5400: /* DS5400 MIPSfair */ | |
743 | panic("Don't know how to set this up!"); | |
744 | break; | |
745 | case MACH_DS5500: /* DS5500 MIPSfair-2 */ | |
746 | panic("Don't know how to set this up!"); | |
747 | break; | |
748 | } | |
1da177e4 LT |
749 | |
750 | /* Free the FPU interrupt if the exception is present. */ | |
751 | if (!cpu_has_nofpuex) { | |
752 | cpu_fpu_mask = 0; | |
753 | dec_interrupt[DEC_IRQ_FPU] = -1; | |
754 | } | |
76ad023b MR |
755 | /* Free the halt interrupt unused on R4k systems. */ |
756 | if (current_cpu_type() == CPU_R4000SC || | |
757 | current_cpu_type() == CPU_R4400SC) | |
758 | dec_interrupt[DEC_IRQ_HALT] = -1; | |
1da177e4 LT |
759 | |
760 | /* Register board interrupts: FPU and cascade. */ | |
5ffd7c8b | 761 | if (dec_interrupt[DEC_IRQ_FPU] >= 0 && cpu_has_fpu) { |
f02cf469 MR |
762 | struct irq_desc *desc_fpu; |
763 | int irq_fpu; | |
764 | ||
765 | irq_fpu = dec_interrupt[DEC_IRQ_FPU]; | |
766 | setup_irq(irq_fpu, &fpuirq); | |
767 | desc_fpu = irq_to_desc(irq_fpu); | |
768 | fpu_kstat_irq = this_cpu_ptr(desc_fpu->kstat_irqs); | |
769 | } | |
1da177e4 LT |
770 | if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) |
771 | setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq); | |
772 | ||
773 | /* Register the bus error interrupt. */ | |
774 | if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler) | |
775 | setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq); | |
776 | ||
777 | /* Register the HALT interrupt. */ | |
778 | if (dec_interrupt[DEC_IRQ_HALT] >= 0) | |
779 | setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); | |
780 | } | |
187933f2 AN |
781 | |
782 | asmlinkage unsigned int dec_irq_dispatch(unsigned int irq) | |
783 | { | |
784 | do_IRQ(irq); | |
785 | return 0; | |
786 | } |