[linux-2.6-block.git] / arch / mips / dec / kn02-irq.c

/*
 *	DECstation 5000/200 (KN02) Control and Status Register
 *	interrupts.
 *
 *	Copyright (c) 2002, 2003, 2005  Maciej W. Rozycki
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 */

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/types.h>

#include <asm/dec/kn02.h>


/*
 * Bits 7:0 of the Control Register are write-only -- the
 * corresponding bits of the Status Register have a different
 * meaning.  Hence we use a cache.  It speeds up things a bit
 * as well.
 *
 * There is no default value -- it has to be initialized.
 */
u32 cached_kn02_csr;

static int kn02_irq_base;

static void unmask_kn02_irq(struct irq_data *d)
{
	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
						       KN02_CSR);

	cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16));
	*csr = cached_kn02_csr;
}

static void mask_kn02_irq(struct irq_data *d)
{
	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
						       KN02_CSR);

	cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16));
	*csr = cached_kn02_csr;
}

static void ack_kn02_irq(struct irq_data *d)
{
	mask_kn02_irq(d);
	iob();
}

static struct irq_chip kn02_irq_type = {
	.name = "KN02-CSR",
	.irq_ack = ack_kn02_irq,
	.irq_mask = mask_kn02_irq,
	.irq_mask_ack = ack_kn02_irq,
	.irq_unmask = unmask_kn02_irq,
};

void __init init_kn02_irqs(int base)
{
	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
						       KN02_CSR);
	int i;

	/* Mask interrupts. */
	cached_kn02_csr &= ~KN02_CSR_IOINTEN;
	*csr = cached_kn02_csr;
	iob();

	for (i = base; i < base + KN02_IRQ_LINES; i++)
		irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq);

	kn02_irq_base = base;
}
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* DECstation 5000/200 (KN02) Control and Status Register
	3	* interrupts.
	4	*
64dac503	5	* Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki
1da177e4 LT	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/irq.h>
1da177e4 LT	15	#include <linux/types.h>
	16
	17	#include <asm/dec/kn02.h>
	18
	19
	20	/*
	21	* Bits 7:0 of the Control Register are write-only -- the
	22	* corresponding bits of the Status Register have a different
	23	* meaning. Hence we use a cache. It speeds up things a bit
	24	* as well.
	25	*
	26	* There is no default value -- it has to be initialized.
	27	*/
	28	u32 cached_kn02_csr;
1da177e4	29
1da177e4 LT	30	static int kn02_irq_base;
1da177e4 LT	31
009c200a	32	static void unmask_kn02_irq(struct irq_data *d)
1da177e4	33	{
a5fc9c0b MR	34	volatile u32 csr = (volatile u32 )CKSEG1ADDR(KN02_SLOT_BASE +
a5fc9c0b MR	35	KN02_CSR);
1da177e4	36
009c200a	37	cached_kn02_csr \|= (1 << (d->irq - kn02_irq_base + 16));
1da177e4 LT	38	*csr = cached_kn02_csr;
	39	}
	40
009c200a	41	static void mask_kn02_irq(struct irq_data *d)
1da177e4	42	{
a5fc9c0b MR	43	volatile u32 csr = (volatile u32 )CKSEG1ADDR(KN02_SLOT_BASE +
a5fc9c0b MR	44	KN02_CSR);
1da177e4	45
009c200a	46	cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16));
1da177e4 LT	47	*csr = cached_kn02_csr;
	48	}
	49
009c200a	50	static void ack_kn02_irq(struct irq_data *d)
1da177e4	51	{
009c200a	52	mask_kn02_irq(d);
1da177e4 LT	53	iob();
	54	}
	55
94dee171	56	static struct irq_chip kn02_irq_type = {
70d21cde	57	.name = "KN02-CSR",
009c200a TG	58	.irq_ack = ack_kn02_irq,
	59	.irq_mask = mask_kn02_irq,
	60	.irq_mask_ack = ack_kn02_irq,
	61	.irq_unmask = unmask_kn02_irq,
1da177e4 LT	62	};
1da177e4 LT	63
1da177e4 LT	64	void __init init_kn02_irqs(int base)
1da177e4 LT	65	{
a5fc9c0b MR	66	volatile u32 csr = (volatile u32 )CKSEG1ADDR(KN02_SLOT_BASE +
a5fc9c0b MR	67	KN02_CSR);
1da177e4 LT	68	int i;
	69
	70	/* Mask interrupts. */
64dac503	71	cached_kn02_csr &= ~KN02_CSR_IOINTEN;
1da177e4 LT	72	*csr = cached_kn02_csr;
1da177e4 LT	73	iob();
1603b5ac AN	74
1603b5ac AN	75	for (i = base; i < base + KN02_IRQ_LINES; i++)
e4ec7989	76	irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
1da177e4 LT	77
	78	kn02_irq_base = base;
	79	}