[linux-2.6-block.git] / arch / mips / dec / ioasic-irq.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *	DEC I/O ASIC interrupts.
 *
 *	Copyright (c) 2002, 2003, 2013  Maciej W. Rozycki
 */

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/types.h>

#include <asm/dec/ioasic.h>
#include <asm/dec/ioasic_addrs.h>
#include <asm/dec/ioasic_ints.h>

static int ioasic_irq_base;

static void unmask_ioasic_irq(struct irq_data *d)
{
	u32 simr;

	simr = ioasic_read(IO_REG_SIMR);
	simr |= (1 << (d->irq - ioasic_irq_base));
	ioasic_write(IO_REG_SIMR, simr);
}

static void mask_ioasic_irq(struct irq_data *d)
{
	u32 simr;

	simr = ioasic_read(IO_REG_SIMR);
	simr &= ~(1 << (d->irq - ioasic_irq_base));
	ioasic_write(IO_REG_SIMR, simr);
}

static void ack_ioasic_irq(struct irq_data *d)
{
	mask_ioasic_irq(d);
	fast_iob();
}

static struct irq_chip ioasic_irq_type = {
	.name = "IO-ASIC",
	.irq_ack = ack_ioasic_irq,
	.irq_mask = mask_ioasic_irq,
	.irq_mask_ack = ack_ioasic_irq,
	.irq_unmask = unmask_ioasic_irq,
};

static void clear_ioasic_dma_irq(struct irq_data *d)
{
	u32 sir;

	sir = ~(1 << (d->irq - ioasic_irq_base));
	ioasic_write(IO_REG_SIR, sir);
	fast_iob();
}

static struct irq_chip ioasic_dma_irq_type = {
	.name = "IO-ASIC-DMA",
	.irq_ack = clear_ioasic_dma_irq,
	.irq_mask = mask_ioasic_irq,
	.irq_unmask = unmask_ioasic_irq,
	.irq_eoi = clear_ioasic_dma_irq,
};

/*
 * I/O ASIC implements two kinds of DMA interrupts, informational and
 * error interrupts.
 *
 * The formers do not stop DMA and should be cleared as soon as possible
 * so that if they retrigger before the handler has completed, usually as
 * a side effect of actions taken by the handler, then they are reissued.
 * These use the `handle_edge_irq' handler that clears the request right
 * away.
 *
 * The latters stop DMA and do not resume it until the interrupt has been
 * cleared.  This cannot be done until after a corrective action has been
 * taken and this also means they will not retrigger.  Therefore they use
 * the `handle_fasteoi_irq' handler that only clears the request on the
 * way out.  Because MIPS processor interrupt inputs, one of which the I/O
 * ASIC is cascaded to, are level-triggered it is recommended that error
 * DMA interrupt action handlers are registered with the IRQF_ONESHOT flag
 * set so that they are run with the interrupt line masked.
 *
 * This mask has `1' bits in the positions of informational interrupts.
 */
#define IO_IRQ_DMA_INFO							\
	(IO_IRQ_MASK(IO_INR_SCC0A_RXDMA) |				\
	 IO_IRQ_MASK(IO_INR_SCC1A_RXDMA) |				\
	 IO_IRQ_MASK(IO_INR_ISDN_TXDMA) |				\
	 IO_IRQ_MASK(IO_INR_ISDN_RXDMA) |				\
	 IO_IRQ_MASK(IO_INR_ASC_DMA))

void __init init_ioasic_irqs(int base)
{
	int i;

	/* Mask interrupts. */
	ioasic_write(IO_REG_SIMR, 0);
	fast_iob();

	for (i = base; i < base + IO_INR_DMA; i++)
		irq_set_chip_and_handler(i, &ioasic_irq_type,
					 handle_level_irq);
	for (; i < base + IO_IRQ_LINES; i++)
		irq_set_chip_and_handler(i, &ioasic_dma_irq_type,
					 1 << (i - base) & IO_IRQ_DMA_INFO ?
					 handle_edge_irq : handle_fasteoi_irq);

	ioasic_irq_base = base;
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4	2	/*
1da177e4 LT	3	* DEC I/O ASIC interrupts.
1da177e4 LT	4	*
0fabe102	5	* Copyright (c) 2002, 2003, 2013 Maciej W. Rozycki
1da177e4 LT	6	*/
	7
	8	#include <linux/init.h>
	9	#include <linux/irq.h>
1da177e4 LT	10	#include <linux/types.h>
	11
	12	#include <asm/dec/ioasic.h>
	13	#include <asm/dec/ioasic_addrs.h>
	14	#include <asm/dec/ioasic_ints.h>
	15
1da177e4 LT	16	static int ioasic_irq_base;
1da177e4 LT	17
009c200a	18	static void unmask_ioasic_irq(struct irq_data *d)
1da177e4 LT	19	{
	20	u32 simr;
	21
	22	simr = ioasic_read(IO_REG_SIMR);
009c200a	23	simr \|= (1 << (d->irq - ioasic_irq_base));
1da177e4 LT	24	ioasic_write(IO_REG_SIMR, simr);
	25	}
	26
009c200a	27	static void mask_ioasic_irq(struct irq_data *d)
1da177e4 LT	28	{
	29	u32 simr;
	30
	31	simr = ioasic_read(IO_REG_SIMR);
009c200a	32	simr &= ~(1 << (d->irq - ioasic_irq_base));
1da177e4 LT	33	ioasic_write(IO_REG_SIMR, simr);
	34	}
	35
009c200a	36	static void ack_ioasic_irq(struct irq_data *d)
1da177e4	37	{
009c200a	38	mask_ioasic_irq(d);
1da177e4 LT	39	fast_iob();
	40	}
	41
94dee171	42	static struct irq_chip ioasic_irq_type = {
70d21cde	43	.name = "IO-ASIC",
009c200a TG	44	.irq_ack = ack_ioasic_irq,
	45	.irq_mask = mask_ioasic_irq,
	46	.irq_mask_ack = ack_ioasic_irq,
	47	.irq_unmask = unmask_ioasic_irq,
1da177e4 LT	48	};
1da177e4 LT	49
0fabe102	50	static void clear_ioasic_dma_irq(struct irq_data *d)
5359b938 MR	51	{
	52	u32 sir;
	53
0fabe102	54	sir = ~(1 << (d->irq - ioasic_irq_base));
5359b938	55	ioasic_write(IO_REG_SIR, sir);
0fabe102	56	fast_iob();
5359b938 MR	57	}
5359b938 MR	58
94dee171	59	static struct irq_chip ioasic_dma_irq_type = {
70d21cde	60	.name = "IO-ASIC-DMA",
0fabe102	61	.irq_ack = clear_ioasic_dma_irq,
009c200a	62	.irq_mask = mask_ioasic_irq,
009c200a	63	.irq_unmask = unmask_ioasic_irq,
0fabe102	64	.irq_eoi = clear_ioasic_dma_irq,
1da177e4 LT	65	};
1da177e4 LT	66
0fabe102 MR	67	/*
	68	* I/O ASIC implements two kinds of DMA interrupts, informational and
	69	* error interrupts.
	70	*
	71	* The formers do not stop DMA and should be cleared as soon as possible
	72	* so that if they retrigger before the handler has completed, usually as
	73	* a side effect of actions taken by the handler, then they are reissued.
	74	* These use the `handle_edge_irq' handler that clears the request right
	75	* away.
	76	*
	77	* The latters stop DMA and do not resume it until the interrupt has been
	78	* cleared. This cannot be done until after a corrective action has been
	79	* taken and this also means they will not retrigger. Therefore they use
	80	* the `handle_fasteoi_irq' handler that only clears the request on the
	81	* way out. Because MIPS processor interrupt inputs, one of which the I/O
	82	* ASIC is cascaded to, are level-triggered it is recommended that error
	83	* DMA interrupt action handlers are registered with the IRQF_ONESHOT flag
	84	* set so that they are run with the interrupt line masked.
	85	*
	86	* This mask has `1' bits in the positions of informational interrupts.
	87	*/
	88	#define IO_IRQ_DMA_INFO \
	89	(IO_IRQ_MASK(IO_INR_SCC0A_RXDMA) \| \
	90	IO_IRQ_MASK(IO_INR_SCC1A_RXDMA) \| \
	91	IO_IRQ_MASK(IO_INR_ISDN_TXDMA) \| \
	92	IO_IRQ_MASK(IO_INR_ISDN_RXDMA) \| \
	93	IO_IRQ_MASK(IO_INR_ASC_DMA))
	94
1da177e4 LT	95	void __init init_ioasic_irqs(int base)
	96	{
	97	int i;
	98
	99	/* Mask interrupts. */
	100	ioasic_write(IO_REG_SIMR, 0);
	101	fast_iob();
	102
1603b5ac	103	for (i = base; i < base + IO_INR_DMA; i++)
e4ec7989	104	irq_set_chip_and_handler(i, &ioasic_irq_type,
1417836e	105	handle_level_irq);
1603b5ac	106	for (; i < base + IO_IRQ_LINES; i++)
0fabe102 MR	107	irq_set_chip_and_handler(i, &ioasic_dma_irq_type,
	108	1 << (i - base) & IO_IRQ_DMA_INFO ?
	109	handle_edge_irq : handle_fasteoi_irq);
1da177e4 LT	110
	111	ioasic_irq_base = base;
	112	}