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1da177e4 LT |
1 | /* |
2 | * arch/mips/dec/int-handler.S | |
3 | * | |
4 | * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen | |
5 | * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki | |
6 | * | |
7 | * Written by Ralf Baechle and Andreas Busse, modified for DECStation | |
8 | * support by Paul Antoine and Harald Koerfgen. | |
9 | * | |
10 | * completly rewritten: | |
11 | * Copyright (C) 1998 Harald Koerfgen | |
12 | * | |
13 | * Rewritten extensively for controller-driven IRQ support | |
14 | * by Maciej W. Rozycki. | |
15 | */ | |
16 | #include <linux/config.h> | |
17 | #include <asm/asm.h> | |
18 | #include <asm/regdef.h> | |
19 | #include <asm/mipsregs.h> | |
20 | #include <asm/stackframe.h> | |
21 | #include <asm/addrspace.h> | |
22 | ||
23 | #include <asm/dec/interrupts.h> | |
24 | #include <asm/dec/ioasic_addrs.h> | |
25 | #include <asm/dec/ioasic_ints.h> | |
26 | #include <asm/dec/kn01.h> | |
27 | #include <asm/dec/kn02.h> | |
28 | #include <asm/dec/kn02xa.h> | |
29 | #include <asm/dec/kn03.h> | |
30 | ||
31 | ||
32 | .text | |
33 | .set noreorder | |
34 | /* | |
35 | * decstation_handle_int: Interrupt handler for DECStations | |
36 | * | |
37 | * We follow the model in the Indy interrupt code by David Miller, where he | |
38 | * says: a lot of complication here is taken away because: | |
39 | * | |
40 | * 1) We handle one interrupt and return, sitting in a loop | |
41 | * and moving across all the pending IRQ bits in the cause | |
42 | * register is _NOT_ the answer, the common case is one | |
43 | * pending IRQ so optimize in that direction. | |
44 | * | |
45 | * 2) We need not check against bits in the status register | |
46 | * IRQ mask, that would make this routine slow as hell. | |
47 | * | |
48 | * 3) Linux only thinks in terms of all IRQs on or all IRQs | |
49 | * off, nothing in between like BSD spl() brain-damage. | |
50 | * | |
51 | * Furthermore, the IRQs on the DECStations look basically (barring | |
52 | * software IRQs which we don't use at all) like... | |
53 | * | |
54 | * DS2100/3100's, aka kn01, aka Pmax: | |
55 | * | |
56 | * MIPS IRQ Source | |
57 | * -------- ------ | |
58 | * 0 Software (ignored) | |
59 | * 1 Software (ignored) | |
60 | * 2 SCSI | |
61 | * 3 Lance Ethernet | |
62 | * 4 DZ11 serial | |
63 | * 5 RTC | |
64 | * 6 Memory Controller | |
65 | * 7 FPU | |
66 | * | |
67 | * DS5000/200, aka kn02, aka 3max: | |
68 | * | |
69 | * MIPS IRQ Source | |
70 | * -------- ------ | |
71 | * 0 Software (ignored) | |
72 | * 1 Software (ignored) | |
73 | * 2 TurboChannel | |
74 | * 3 RTC | |
75 | * 4 Reserved | |
76 | * 5 Memory Controller | |
77 | * 6 Reserved | |
78 | * 7 FPU | |
79 | * | |
80 | * DS5000/1xx's, aka kn02ba, aka 3min: | |
81 | * | |
82 | * MIPS IRQ Source | |
83 | * -------- ------ | |
84 | * 0 Software (ignored) | |
85 | * 1 Software (ignored) | |
86 | * 2 TurboChannel Slot 0 | |
87 | * 3 TurboChannel Slot 1 | |
88 | * 4 TurboChannel Slot 2 | |
89 | * 5 TurboChannel Slot 3 (ASIC) | |
90 | * 6 Halt button | |
91 | * 7 FPU/R4k timer | |
92 | * | |
93 | * DS5000/2x's, aka kn02ca, aka maxine: | |
94 | * | |
95 | * MIPS IRQ Source | |
96 | * -------- ------ | |
97 | * 0 Software (ignored) | |
98 | * 1 Software (ignored) | |
99 | * 2 Periodic Interrupt (100usec) | |
100 | * 3 RTC | |
101 | * 4 I/O write timeout | |
102 | * 5 TurboChannel (ASIC) | |
103 | * 6 Halt Keycode from Access.Bus keyboard (CTRL-ALT-ENTER) | |
104 | * 7 FPU/R4k timer | |
105 | * | |
106 | * DS5000/2xx's, aka kn03, aka 3maxplus: | |
107 | * | |
108 | * MIPS IRQ Source | |
109 | * -------- ------ | |
110 | * 0 Software (ignored) | |
111 | * 1 Software (ignored) | |
112 | * 2 System Board (ASIC) | |
113 | * 3 RTC | |
114 | * 4 Reserved | |
115 | * 5 Memory | |
116 | * 6 Halt Button | |
117 | * 7 FPU/R4k timer | |
118 | * | |
119 | * We handle the IRQ according to _our_ priority (see setup.c), | |
120 | * then we just return. If multiple IRQs are pending then we will | |
121 | * just take another exception, big deal. | |
122 | */ | |
123 | .align 5 | |
124 | NESTED(decstation_handle_int, PT_SIZE, ra) | |
125 | .set noat | |
126 | SAVE_ALL | |
127 | CLI # TEST: interrupts should be off | |
128 | .set at | |
129 | .set noreorder | |
130 | ||
131 | /* | |
132 | * Get pending Interrupts | |
133 | */ | |
134 | mfc0 t0,CP0_CAUSE # get pending interrupts | |
135 | mfc0 t1,CP0_STATUS | |
136 | #ifdef CONFIG_MIPS32 | |
137 | lw t2,cpu_fpu_mask | |
138 | #endif | |
139 | andi t0,ST0_IM # CAUSE.CE may be non-zero! | |
140 | and t0,t1 # isolate allowed ones | |
141 | ||
142 | beqz t0,spurious | |
143 | ||
144 | #ifdef CONFIG_MIPS32 | |
145 | and t2,t0 | |
146 | bnez t2,fpu # handle FPU immediately | |
147 | #endif | |
148 | ||
149 | /* | |
150 | * Find irq with highest priority | |
151 | */ | |
152 | PTR_LA t1,cpu_mask_nr_tbl | |
153 | 1: lw t2,(t1) | |
154 | nop | |
155 | and t2,t0 | |
156 | beqz t2,1b | |
157 | addu t1,2*PTRSIZE # delay slot | |
158 | ||
159 | /* | |
160 | * Do the low-level stuff | |
161 | */ | |
162 | lw a0,(-PTRSIZE)(t1) | |
163 | nop | |
164 | bgez a0,handle_it # irq_nr >= 0? | |
165 | # irq_nr < 0: it is an address | |
166 | nop | |
167 | jr a0 | |
168 | # a trick to save a branch: | |
169 | lui t2,(KN03_IOASIC_BASE>>16)&0xffff | |
170 | # upper part of IOASIC Address | |
171 | ||
172 | /* | |
173 | * Handle "IRQ Controller" Interrupts | |
174 | * Masked Interrupts are still visible and have to be masked "by hand". | |
175 | */ | |
176 | FEXPORT(kn02_io_int) # 3max | |
177 | lui t0,(KN02_CSR_BASE>>16)&0xffff | |
178 | # get interrupt status and mask | |
179 | lw t0,(t0) | |
180 | nop | |
181 | andi t1,t0,KN02_IRQ_ALL | |
182 | b 1f | |
183 | srl t0,16 # shift interrupt mask | |
184 | ||
185 | FEXPORT(kn02xa_io_int) # 3min/maxine | |
186 | lui t2,(KN02XA_IOASIC_BASE>>16)&0xffff | |
187 | # upper part of IOASIC Address | |
188 | ||
189 | FEXPORT(kn03_io_int) # 3max+ (t2 loaded earlier) | |
190 | lw t0,IO_REG_SIR(t2) # get status: IOASIC sir | |
191 | lw t1,IO_REG_SIMR(t2) # get mask: IOASIC simr | |
192 | nop | |
193 | ||
194 | 1: and t0,t1 # mask out allowed ones | |
195 | ||
196 | beqz t0,spurious | |
197 | ||
198 | /* | |
199 | * Find irq with highest priority | |
200 | */ | |
201 | PTR_LA t1,asic_mask_nr_tbl | |
202 | 2: lw t2,(t1) | |
203 | nop | |
204 | and t2,t0 | |
205 | beq zero,t2,2b | |
206 | addu t1,2*PTRSIZE # delay slot | |
207 | ||
208 | /* | |
209 | * Do the low-level stuff | |
210 | */ | |
211 | lw a0,%lo(-PTRSIZE)(t1) | |
212 | nop | |
213 | bgez a0,handle_it # irq_nr >= 0? | |
214 | # irq_nr < 0: it is an address | |
215 | nop | |
216 | jr a0 | |
217 | nop # delay slot | |
218 | ||
219 | /* | |
220 | * Dispatch low-priority interrupts. We reconsider all status | |
221 | * bits again, which looks like a lose, but it makes the code | |
222 | * simple and O(log n), so it gets compensated. | |
223 | */ | |
224 | FEXPORT(cpu_all_int) # HALT, timers, software junk | |
225 | li a0,DEC_CPU_IRQ_BASE | |
226 | srl t0,CAUSEB_IP | |
227 | li t1,CAUSEF_IP>>CAUSEB_IP # mask | |
228 | b 1f | |
229 | li t2,4 # nr of bits / 2 | |
230 | ||
231 | FEXPORT(kn02_all_int) # impossible ? | |
232 | li a0,KN02_IRQ_BASE | |
233 | li t1,KN02_IRQ_ALL # mask | |
234 | b 1f | |
235 | li t2,4 # nr of bits / 2 | |
236 | ||
237 | FEXPORT(asic_all_int) # various I/O ASIC junk | |
238 | li a0,IO_IRQ_BASE | |
239 | li t1,IO_IRQ_ALL # mask | |
240 | b 1f | |
241 | li t2,8 # nr of bits / 2 | |
242 | ||
243 | /* | |
244 | * Dispatch DMA interrupts -- O(log n). | |
245 | */ | |
246 | FEXPORT(asic_dma_int) # I/O ASIC DMA events | |
247 | li a0,IO_IRQ_BASE+IO_INR_DMA | |
248 | srl t0,IO_INR_DMA | |
249 | li t1,IO_IRQ_DMA>>IO_INR_DMA # mask | |
250 | li t2,8 # nr of bits / 2 | |
251 | ||
252 | /* | |
253 | * Find irq with highest priority. | |
254 | * Highest irq number takes precedence. | |
255 | */ | |
256 | 1: srlv t3,t1,t2 | |
257 | 2: xor t1,t3 | |
258 | and t3,t0,t1 | |
259 | beqz t3,3f | |
260 | nop | |
261 | move t0,t3 | |
262 | addu a0,t2 | |
263 | 3: srl t2,1 | |
264 | bnez t2,2b | |
265 | srlv t3,t1,t2 | |
266 | ||
267 | handle_it: | |
268 | jal do_IRQ | |
269 | move a1,sp | |
270 | ||
271 | j ret_from_irq | |
272 | nop | |
273 | ||
274 | #ifdef CONFIG_MIPS32 | |
275 | fpu: | |
276 | j handle_fpe_int | |
277 | nop | |
278 | #endif | |
279 | ||
280 | spurious: | |
281 | j spurious_interrupt | |
282 | nop | |
283 | END(decstation_handle_int) | |
284 | ||
285 | /* | |
286 | * Generic unimplemented interrupt routines -- cpu_mask_nr_tbl | |
287 | * and asic_mask_nr_tbl are initialized to point all interrupts here. | |
288 | * The tables are then filled in by machine-specific initialisation | |
289 | * in dec_setup(). | |
290 | */ | |
291 | FEXPORT(dec_intr_unimplemented) | |
292 | move a1,t0 # cheats way of printing an arg! | |
293 | PANIC("Unimplemented cpu interrupt! CP0_CAUSE: 0x%08x"); | |
294 | ||
295 | FEXPORT(asic_intr_unimplemented) | |
296 | move a1,t0 # cheats way of printing an arg! | |
297 | PANIC("Unimplemented asic interrupt! ASIC ISR: 0x%08x"); |