projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 23a271ec | 2 | if CPU_CAVIUM_OCTEON |
| 5b3b1688 | 3 | |
| c9941158 | 4 | config CAVIUM_CN63XXP1 |
| f54619f2 | 5 | bool "Enable CN63XXP1 errata workarounds" |
| c9941158 DD |
6 | default "n" |
| 7 | help | |
| 8 | The CN63XXP1 chip requires build time workarounds to | |
| 9 | function reliably, select this option to enable them. These | |
| 10 | workarounds will cause a slight decrease in performance on | |
| 11 | non-CN63XXP1 hardware, so it is recommended to select "n" | |
| 12 | unless it is known the workarounds are needed. | |
| 13 | ||
| 8a837cdb DD |
14 | config CAVIUM_OCTEON_CVMSEG_SIZE |
| 15 | int "Number of L1 cache lines reserved for CVMSEG memory" | |
| 16 | range 0 54 | |
| 17 | default 1 | |
| 18 | help | |
| 19 | CVMSEG LM is a segment that accesses portions of the dcache as a | |
| 20 | local memory; the larger CVMSEG is, the smaller the cache is. | |
| 21 | This selects the size of CVMSEG LM, which is in cache blocks. The | |
| 22 | legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is | |
| 23 | between zero and 6192 bytes). | |
| 24 | ||
| 9ddebc46 DD |
25 | endif # CPU_CAVIUM_OCTEON |
| 26 | ||
| 27 | if CAVIUM_OCTEON_SOC | |
| 28 | ||
| 5b3b1688 DD |
29 | config CAVIUM_OCTEON_LOCK_L2 |
| 30 | bool "Lock often used kernel code in the L2" | |
| 5b3b1688 DD |
31 | default "y" |
| 32 | help | |
| 33 | Enable locking parts of the kernel into the L2 cache. | |
| 34 | ||
| 35 | config CAVIUM_OCTEON_LOCK_L2_TLB | |
| 36 | bool "Lock the TLB handler in L2" | |
| 37 | depends on CAVIUM_OCTEON_LOCK_L2 | |
| 38 | default "y" | |
| 39 | help | |
| 40 | Lock the low level TLB fast path into L2. | |
| 41 | ||
| 42 | config CAVIUM_OCTEON_LOCK_L2_EXCEPTION | |
| 43 | bool "Lock the exception handler in L2" | |
| 44 | depends on CAVIUM_OCTEON_LOCK_L2 | |
| 45 | default "y" | |
| 46 | help | |
| 47 | Lock the low level exception handler into L2. | |
| 48 | ||
| 49 | config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT | |
| 50 | bool "Lock the interrupt handler in L2" | |
| 51 | depends on CAVIUM_OCTEON_LOCK_L2 | |
| 52 | default "y" | |
| 53 | help | |
| 54 | Lock the low level interrupt handler into L2. | |
| 55 | ||
| 56 | config CAVIUM_OCTEON_LOCK_L2_INTERRUPT | |
| 57 | bool "Lock the 2nd level interrupt handler in L2" | |
| 58 | depends on CAVIUM_OCTEON_LOCK_L2 | |
| 59 | default "y" | |
| 60 | help | |
| 61 | Lock the 2nd level interrupt handler in L2. | |
| 62 | ||
| 63 | config CAVIUM_OCTEON_LOCK_L2_MEMCPY | |
| 64 | bool "Lock memcpy() in L2" | |
| 65 | depends on CAVIUM_OCTEON_LOCK_L2 | |
| 66 | default "y" | |
| 67 | help | |
| 68 | Lock the kernel's implementation of memcpy() into L2. | |
| 69 | ||
| b93b2abc DD |
70 | config IOMMU_HELPER |
| 71 | bool | |
| 72 | ||
| 73 | config NEED_SG_DMA_LENGTH | |
| 74 | bool | |
| 75 | ||
| 76 | config SWIOTLB | |
| 77 | def_bool y | |
| b93b2abc DD |
78 | select IOMMU_HELPER |
| 79 | select NEED_SG_DMA_LENGTH | |
| 23a271ec | 80 | |
| 0e49caf6 VS |
81 | config OCTEON_ILM |
| 82 | tristate "Module to measure interrupt latency using Octeon CIU Timer" | |
| 83 | help | |
| 84 | This driver is a module to measure interrupt latency using the | |
| 85 | the CIU Timers on Octeon. | |
| 86 | ||
| 87 | To compile this driver as a module, choose M here. The module | |
| 88 | will be called octeon-ilm | |
| 89 | ||
| 9ddebc46 | 90 | endif # CAVIUM_OCTEON_SOC |