[linux-2.6-block.git] / arch / mips / boot / dts / ingenic / x1830.dtsi

// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/ingenic,tcu.h>
#include <dt-bindings/clock/x1830-cgu.h>
#include <dt-bindings/dma/x1830-dma.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "ingenic,x1830";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "ingenic,xburst-fpu2.0-mxu2.0";
			reg = <0>;

			clocks = <&cgu X1830_CLK_CPU>;
			clock-names = "cpu";
		};
	};

	cpuintc: interrupt-controller {
		#address-cells = <0>;
		#interrupt-cells = <1>;
		interrupt-controller;
		compatible = "mti,cpu-interrupt-controller";
	};

	intc: interrupt-controller@10001000 {
		compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
		reg = <0x10001000 0x50>;

		interrupt-controller;
		#interrupt-cells = <1>;

		interrupt-parent = <&cpuintc>;
		interrupts = <2>;
	};

	exclk: ext {
		compatible = "fixed-clock";
		#clock-cells = <0>;
	};

	rtclk: rtc {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
	};

	cgu: x1830-cgu@10000000 {
		compatible = "ingenic,x1830-cgu", "simple-mfd";
		reg = <0x10000000 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x10000000 0x100>;

		#clock-cells = <1>;

		clocks = <&exclk>, <&rtclk>;
		clock-names = "ext", "rtc";

		otg_phy: usb-phy@3c {
			compatible = "ingenic,x1830-phy";
			reg = <0x3c 0x10>;

			clocks = <&cgu X1830_CLK_OTGPHY>;

			#phy-cells = <0>;

			status = "disabled";
		};
	};

	ost: timer@12000000 {
		compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
		reg = <0x12000000 0x3c>;

		#clock-cells = <1>;

		clocks = <&cgu X1830_CLK_OST>;
		clock-names = "ost";

		interrupt-parent = <&cpuintc>;
		interrupts = <4>;
	};

	tcu: timer@10002000 {
		compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd";
		reg = <0x10002000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x10002000 0x1000>;

		#clock-cells = <1>;

		clocks = <&cgu X1830_CLK_RTCLK>,
			 <&cgu X1830_CLK_EXCLK>,
			 <&cgu X1830_CLK_PCLK>;
		clock-names = "rtc", "ext", "pclk";

		interrupt-controller;
		#interrupt-cells = <1>;

		interrupt-parent = <&intc>;
		interrupts = <27 26 25>;

		wdt: watchdog@0 {
			compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog";
			reg = <0x0 0x10>;

			clocks = <&tcu TCU_CLK_WDT>;
			clock-names = "wdt";
		};
	};

	rtc: rtc@10003000 {
		compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc";
		reg = <0x10003000 0x4c>;

		interrupt-parent = <&intc>;
		interrupts = <32>;

		clocks = <&cgu X1830_CLK_RTCLK>;
		clock-names = "rtc";
	};

	pinctrl: pin-controller@10010000 {
		compatible = "ingenic,x1830-pinctrl";
		reg = <0x10010000 0x800>;
		#address-cells = <1>;
		#size-cells = <0>;

		gpa: gpio@0 {
			compatible = "ingenic,x1830-gpio";
			reg = <0>;

			gpio-controller;
			gpio-ranges = <&pinctrl 0 0 32>;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;

			interrupt-parent = <&intc>;
			interrupts = <17>;
		};

		gpb: gpio@1 {
			compatible = "ingenic,x1830-gpio";
			reg = <1>;

			gpio-controller;
			gpio-ranges = <&pinctrl 0 32 32>;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;

			interrupt-parent = <&intc>;
			interrupts = <16>;
		};

		gpc: gpio@2 {
			compatible = "ingenic,x1830-gpio";
			reg = <2>;

			gpio-controller;
			gpio-ranges = <&pinctrl 0 64 32>;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;

			interrupt-parent = <&intc>;
			interrupts = <15>;
		};

		gpd: gpio@3 {
			compatible = "ingenic,x1830-gpio";
			reg = <3>;

			gpio-controller;
			gpio-ranges = <&pinctrl 0 96 32>;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;

			interrupt-parent = <&intc>;
			interrupts = <14>;
		};
	};

	uart0: serial@10030000 {
		compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
		reg = <0x10030000 0x100>;

		interrupt-parent = <&intc>;
		interrupts = <51>;

		clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
		clock-names = "baud", "module";

		status = "disabled";
	};

	uart1: serial@10031000 {
		compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
		reg = <0x10031000 0x100>;

		interrupt-parent = <&intc>;
		interrupts = <50>;

		clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
		clock-names = "baud", "module";

		status = "disabled";
	};

	i2c0: i2c-controller@10050000 {
		compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
		reg = <0x10050000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;

		interrupt-parent = <&intc>;
		interrupts = <60>;

		clocks = <&cgu X1830_CLK_SMB0>;

		status = "disabled";
	};

	i2c1: i2c-controller@10051000 {
		compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
		reg = <0x10051000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;

		interrupt-parent = <&intc>;
		interrupts = <59>;

		clocks = <&cgu X1830_CLK_SMB1>;

		status = "disabled";
	};

	i2c2: i2c-controller@10052000 {
		compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
		reg = <0x10052000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;

		interrupt-parent = <&intc>;
		interrupts = <58>;

		clocks = <&cgu X1830_CLK_SMB2>;

		status = "disabled";
	};

	dtrng: trng@10072000 {
		compatible = "ingenic,x1830-dtrng";
		reg = <0x10072000 0xc>;

		clocks = <&cgu X1830_CLK_DTRNG>;

		status = "disabled";
	};

	pdma: dma-controller@13420000 {
		compatible = "ingenic,x1830-dma";
		reg = <0x13420000 0x400>, <0x13421000 0x40>;
		#dma-cells = <2>;

		interrupt-parent = <&intc>;
		interrupts = <10>;

		clocks = <&cgu X1830_CLK_PDMA>;
	};

	msc0: mmc@13450000 {
		compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
		reg = <0x13450000 0x1000>;

		interrupt-parent = <&intc>;
		interrupts = <37>;

		clocks = <&cgu X1830_CLK_MSC0>;
		clock-names = "mmc";

		cap-sd-highspeed;
		cap-mmc-highspeed;
		cap-sdio-irq;

		dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>,
			   <&pdma X1830_DMA_MSC0_TX 0xffffffff>;
		dma-names = "rx", "tx";

		status = "disabled";
	};

	msc1: mmc@13460000 {
		compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
		reg = <0x13460000 0x1000>;

		interrupt-parent = <&intc>;
		interrupts = <36>;

		clocks = <&cgu X1830_CLK_MSC1>;
		clock-names = "mmc";

		cap-sd-highspeed;
		cap-mmc-highspeed;
		cap-sdio-irq;

		dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>,
			   <&pdma X1830_DMA_MSC1_TX 0xffffffff>;
		dma-names = "rx", "tx";

		status = "disabled";
	};

	mac: ethernet@134b0000 {
		compatible = "ingenic,x1830-mac", "snps,dwmac";
		reg = <0x134b0000 0x2000>;

		interrupt-parent = <&intc>;
		interrupts = <55>;
		interrupt-names = "macirq";

		clocks = <&cgu X1830_CLK_MAC>;
		clock-names = "stmmaceth";

		status = "disabled";

		mdio: mdio {
			compatible = "snps,dwmac-mdio";
			#address-cells = <1>;
			#size-cells = <0>;

			status = "disabled";
		};
	};

	otg: usb@13500000 {
		compatible = "ingenic,x1830-otg", "snps,dwc2";
		reg = <0x13500000 0x40000>;

		interrupt-parent = <&intc>;
		interrupts = <21>;

		clocks = <&cgu X1830_CLK_OTG>;
		clock-names = "otg";

		phys = <&otg_phy>;
		phy-names = "usb2-phy";

		g-rx-fifo-size = <768>;
		g-np-tx-fifo-size = <256>;
		g-tx-fifo-size = <256 256 256 256 256 256 256 512>;

		status = "disabled";
	};
};
Commit	Line	Data
63970c29 ZY	1	// SPDX-License-Identifier: GPL-2.0
	2	#include <dt-bindings/clock/ingenic,tcu.h>
	3	#include <dt-bindings/clock/x1830-cgu.h>
	4	#include <dt-bindings/dma/x1830-dma.h>
	5
	6	/ {
	7	#address-cells = <1>;
	8	#size-cells = <1>;
	9	compatible = "ingenic,x1830";
	10
c1f6b45e ZY	11	cpus {
	12	#address-cells = <1>;
	13	#size-cells = <0>;
	14
	15	cpu0: cpu@0 {
	16	device_type = "cpu";
	17	compatible = "ingenic,xburst-fpu2.0-mxu2.0";
	18	reg = <0>;
	19
	20	clocks = <&cgu X1830_CLK_CPU>;
	21	clock-names = "cpu";
	22	};
	23	};
	24
63970c29 ZY	25	cpuintc: interrupt-controller {
	26	#address-cells = <0>;
	27	#interrupt-cells = <1>;
	28	interrupt-controller;
	29	compatible = "mti,cpu-interrupt-controller";
	30	};
	31
	32	intc: interrupt-controller@10001000 {
	33	compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
	34	reg = <0x10001000 0x50>;
	35
	36	interrupt-controller;
	37	#interrupt-cells = <1>;
	38
	39	interrupt-parent = <&cpuintc>;
	40	interrupts = <2>;
	41	};
	42
	43	exclk: ext {
	44	compatible = "fixed-clock";
	45	#clock-cells = <0>;
	46	};
	47
	48	rtclk: rtc {
	49	compatible = "fixed-clock";
	50	#clock-cells = <0>;
	51	clock-frequency = <32768>;
	52	};
	53
	54	cgu: x1830-cgu@10000000 {
158c774d	55	compatible = "ingenic,x1830-cgu", "simple-mfd";
63970c29	56	reg = <0x10000000 0x100>;
158c774d ZY	57	#address-cells = <1>;
	58	#size-cells = <1>;
	59	ranges = <0x0 0x10000000 0x100>;
63970c29 ZY	60
	61	#clock-cells = <1>;
	62
	63	clocks = <&exclk>, <&rtclk>;
	64	clock-names = "ext", "rtc";
158c774d ZY	65
	66	otg_phy: usb-phy@3c {
	67	compatible = "ingenic,x1830-phy";
	68	reg = <0x3c 0x10>;
	69
	70	clocks = <&cgu X1830_CLK_OTGPHY>;
	71
	72	#phy-cells = <0>;
	73
	74	status = "disabled";
	75	};
	76	};
	77
	78	ost: timer@12000000 {
	79	compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
	80	reg = <0x12000000 0x3c>;
	81
	82	#clock-cells = <1>;
	83
	84	clocks = <&cgu X1830_CLK_OST>;
	85	clock-names = "ost";
	86
	87	interrupt-parent = <&cpuintc>;
	88	interrupts = <4>;
63970c29 ZY	89	};
	90
	91	tcu: timer@10002000 {
	92	compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd";
	93	reg = <0x10002000 0x1000>;
	94	#address-cells = <1>;
	95	#size-cells = <1>;
	96	ranges = <0x0 0x10002000 0x1000>;
	97
	98	#clock-cells = <1>;
	99
579f73cf ZY	100	clocks = <&cgu X1830_CLK_RTCLK>,
	101	<&cgu X1830_CLK_EXCLK>,
	102	<&cgu X1830_CLK_PCLK>;
63970c29 ZY	103	clock-names = "rtc", "ext", "pclk";
	104
	105	interrupt-controller;
	106	#interrupt-cells = <1>;
	107
	108	interrupt-parent = <&intc>;
	109	interrupts = <27 26 25>;
	110
	111	wdt: watchdog@0 {
	112	compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog";
	113	reg = <0x0 0x10>;
	114
	115	clocks = <&tcu TCU_CLK_WDT>;
	116	clock-names = "wdt";
	117	};
	118	};
	119
	120	rtc: rtc@10003000 {
	121	compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc";
	122	reg = <0x10003000 0x4c>;
	123
	124	interrupt-parent = <&intc>;
	125	interrupts = <32>;
	126
	127	clocks = <&cgu X1830_CLK_RTCLK>;
	128	clock-names = "rtc";
	129	};
	130
	131	pinctrl: pin-controller@10010000 {
	132	compatible = "ingenic,x1830-pinctrl";
	133	reg = <0x10010000 0x800>;
	134	#address-cells = <1>;
	135	#size-cells = <0>;
	136
	137	gpa: gpio@0 {
	138	compatible = "ingenic,x1830-gpio";
	139	reg = <0>;
	140
	141	gpio-controller;
	142	gpio-ranges = <&pinctrl 0 0 32>;
	143	#gpio-cells = <2>;
	144
	145	interrupt-controller;
	146	#interrupt-cells = <2>;
	147
	148	interrupt-parent = <&intc>;
	149	interrupts = <17>;
	150	};
	151
	152	gpb: gpio@1 {
	153	compatible = "ingenic,x1830-gpio";
	154	reg = <1>;
	155
	156	gpio-controller;
	157	gpio-ranges = <&pinctrl 0 32 32>;
	158	#gpio-cells = <2>;
	159
	160	interrupt-controller;
	161	#interrupt-cells = <2>;
	162
	163	interrupt-parent = <&intc>;
	164	interrupts = <16>;
	165	};
	166
167	gpc: gpio@2 {
168	compatible = "ingenic,x1830-gpio";
169	reg = <2>;
170
171	gpio-controller;
172	gpio-ranges = <&pinctrl 0 64 32>;
173	#gpio-cells = <2>;
174
175	interrupt-controller;
176	#interrupt-cells = <2>;
177
178	interrupt-parent = <&intc>;
179	interrupts = <15>;
180	};
181
182	gpd: gpio@3 {
183	compatible = "ingenic,x1830-gpio";
184	reg = <3>;
185
186	gpio-controller;
187	gpio-ranges = <&pinctrl 0 96 32>;
188	#gpio-cells = <2>;
189
190	interrupt-controller;
191	#interrupt-cells = <2>;
192
193	interrupt-parent = <&intc>;
194	interrupts = <14>;
195	};
196	};
197
198	uart0: serial@10030000 {
199	compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
200	reg = <0x10030000 0x100>;
201
202	interrupt-parent = <&intc>;
203	interrupts = <51>;
204
205	clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
206	clock-names = "baud", "module";
207
208	status = "disabled";
209	};
210
211	uart1: serial@10031000 {
212	compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
213	reg = <0x10031000 0x100>;
214
215	interrupt-parent = <&intc>;
216	interrupts = <50>;
217
218	clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
219	clock-names = "baud", "module";
220
221	status = "disabled";
222	};
223
224	i2c0: i2c-controller@10050000 {
225	compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
226	reg = <0x10050000 0x1000>;
227	#address-cells = <1>;
228	#size-cells = <0>;
229
230	interrupt-parent = <&intc>;
231	interrupts = <60>;
232
233	clocks = <&cgu X1830_CLK_SMB0>;
234
235	status = "disabled";
236	};
237
238	i2c1: i2c-controller@10051000 {
239	compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
240	reg = <0x10051000 0x1000>;
241	#address-cells = <1>;
242	#size-cells = <0>;
243
244	interrupt-parent = <&intc>;
245	interrupts = <59>;
246
247	clocks = <&cgu X1830_CLK_SMB1>;
248
249	status = "disabled";
250	};
251
252	i2c2: i2c-controller@10052000 {
253	compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
254	reg = <0x10052000 0x1000>;
255	#address-cells = <1>;
256	#size-cells = <0>;
257
258	interrupt-parent = <&intc>;
259	interrupts = <58>;
260
261	clocks = <&cgu X1830_CLK_SMB2>;
262
263	status = "disabled";
264	};
265
158c774d ZY	266	dtrng: trng@10072000 {
	267	compatible = "ingenic,x1830-dtrng";
	268	reg = <0x10072000 0xc>;
	269
	270	clocks = <&cgu X1830_CLK_DTRNG>;
	271
	272	status = "disabled";
	273	};
	274
63970c29 ZY	275	pdma: dma-controller@13420000 {
63970c29 ZY	276	compatible = "ingenic,x1830-dma";
579f73cf	277	reg = <0x13420000 0x400>, <0x13421000 0x40>;
63970c29 ZY	278	#dma-cells = <2>;
	279
	280	interrupt-parent = <&intc>;
	281	interrupts = <10>;
	282
	283	clocks = <&cgu X1830_CLK_PDMA>;
	284	};
	285
	286	msc0: mmc@13450000 {
	287	compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
	288	reg = <0x13450000 0x1000>;
	289
	290	interrupt-parent = <&intc>;
	291	interrupts = <37>;
	292
	293	clocks = <&cgu X1830_CLK_MSC0>;
	294	clock-names = "mmc";
	295
	296	cap-sd-highspeed;
	297	cap-mmc-highspeed;
	298	cap-sdio-irq;
	299
	300	dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>,
	301	<&pdma X1830_DMA_MSC0_TX 0xffffffff>;
	302	dma-names = "rx", "tx";
	303
	304	status = "disabled";
	305	};
	306
	307	msc1: mmc@13460000 {
	308	compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
	309	reg = <0x13460000 0x1000>;
	310
	311	interrupt-parent = <&intc>;
	312	interrupts = <36>;
	313
	314	clocks = <&cgu X1830_CLK_MSC1>;
	315	clock-names = "mmc";
	316
	317	cap-sd-highspeed;
	318	cap-mmc-highspeed;
	319	cap-sdio-irq;
	320
	321	dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>,
	322	<&pdma X1830_DMA_MSC1_TX 0xffffffff>;
	323	dma-names = "rx", "tx";
	324
	325	status = "disabled";
	326	};
	327
	328	mac: ethernet@134b0000 {
	329	compatible = "ingenic,x1830-mac", "snps,dwmac";
	330	reg = <0x134b0000 0x2000>;
	331
	332	interrupt-parent = <&intc>;
	333	interrupts = <55>;
	334	interrupt-names = "macirq";
	335
	336	clocks = <&cgu X1830_CLK_MAC>;
	337	clock-names = "stmmaceth";
	338
	339	status = "disabled";
	340
	341	mdio: mdio {
342	compatible = "snps,dwmac-mdio";
343	#address-cells = <1>;
344	#size-cells = <0>;
345
346	status = "disabled";
347	};
348	};
158c774d ZY	349
	350	otg: usb@13500000 {
	351	compatible = "ingenic,x1830-otg", "snps,dwc2";
	352	reg = <0x13500000 0x40000>;
	353
	354	interrupt-parent = <&intc>;
	355	interrupts = <21>;
	356
	357	clocks = <&cgu X1830_CLK_OTG>;
	358	clock-names = "otg";
	359
	360	phys = <&otg_phy>;
	361	phy-names = "usb2-phy";
	362
	363	g-rx-fifo-size = <768>;
	364	g-np-tx-fifo-size = <256>;
	365	g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
	366
	367	status = "disabled";
	368	};
63970c29	369	};