[linux-2.6-block.git] / arch / mips / boot / dts / brcm / bcm7420.dtsi

// SPDX-License-Identifier: GPL-2.0
/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "brcm,bcm7420";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		mips-hpt-frequency = <93750000>;

		cpu@0 {
			compatible = "brcm,bmips5000";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "brcm,bmips5000";
			device_type = "cpu";
			reg = <1>;
		};
	};

	aliases {
		uart0 = &uart0;
	};

	cpu_intc: interrupt-controller {
		#address-cells = <0>;
		compatible = "mti,cpu-interrupt-controller";

		interrupt-controller;
		#interrupt-cells = <1>;
	};

	clocks {
		uart_clk: uart_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <81000000>;
		};

		upg_clk: upg_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
		};
	};

	rdb {
		#address-cells = <1>;
		#size-cells = <1>;

		compatible = "simple-bus";
		ranges = <0 0x10000000 0x01000000>;

		periph_intc: interrupt-controller@441400 {
			compatible = "brcm,bcm7038-l1-intc";
			reg = <0x441400 0x30>, <0x441600 0x30>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&cpu_intc>;
			interrupts = <2>, <3>;
		};

		sun_l2_intc: interrupt-controller@401800 {
			compatible = "brcm,l2-intc";
			reg = <0x401800 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&periph_intc>;
			interrupts = <23>;
		};

		gisb-arb@400000 {
			compatible = "brcm,bcm7400-gisb-arb";
			reg = <0x400000 0xdc>;
			native-endian;
			interrupt-parent = <&sun_l2_intc>;
			interrupts = <0>, <2>;
			brcm,gisb-arb-master-mask = <0x3ff>;
			brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
						     "pcie_0", "bsp_0", "rdc_0",
						     "rptd_0", "avd_0", "avd_1",
						     "jtag_0";
		};

		upg_irq0_intc: interrupt-controller@406780 {
			compatible = "brcm,bcm7120-l2-intc";
			reg = <0x406780 0x8>;

			brcm,int-map-mask = <0x44>, <0x1f000000>, <0x100000>;
			brcm,int-fwd-mask = <0x70000>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&periph_intc>;
			interrupts = <18>, <19>, <20>;
			interrupt-names = "upg_main", "upg_bsc", "upg_spi";
		};

		sun_top_ctrl: syscon@404000 {
			compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
			reg = <0x404000 0x60c>;
			native-endian;
		};

		reboot {
			compatible = "brcm,bcm7038-reboot";
			syscon = <&sun_top_ctrl 0x8 0x14>;
		};

		uart0: serial@406b00 {
			compatible = "ns16550a";
			reg = <0x406b00 0x20>;
			reg-io-width = <0x4>;
			reg-shift = <0x2>;
			interrupt-parent = <&periph_intc>;
			interrupts = <21>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart1: serial@406b40 {
			compatible = "ns16550a";
			reg = <0x406b40 0x20>;
			reg-io-width = <0x4>;
			reg-shift = <0x2>;
			interrupt-parent = <&periph_intc>;
			interrupts = <64>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart2: serial@406b80 {
			compatible = "ns16550a";
			reg = <0x406b80 0x20>;
			reg-io-width = <0x4>;
			reg-shift = <0x2>;
			interrupt-parent = <&periph_intc>;
			interrupts = <65>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		bsca: i2c@406200 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406200 0x58>;
		      interrupts = <24>;
		      interrupt-names = "upg_bsca";
		      status = "disabled";
		};

		bscb: i2c@406280 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406280 0x58>;
		      interrupts = <25>;
		      interrupt-names = "upg_bscb";
		      status = "disabled";
		};

		bscc: i2c@406300 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406300 0x58>;
		      interrupts = <26>;
		      interrupt-names = "upg_bscc";
		      status = "disabled";
		};

		bscd: i2c@406380 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406380 0x58>;
		      interrupts = <27>;
		      interrupt-names = "upg_bscd";
		      status = "disabled";
		};

		bsce: i2c@406800 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406800 0x58>;
		      interrupts = <28>;
		      interrupt-names = "upg_bsce";
		      status = "disabled";
		};

		pwma: pwm@406580 {
			compatible = "brcm,bcm7038-pwm";
			reg = <0x406580 0x28>;
			#pwm-cells = <2>;
			clocks = <&upg_clk>;
			status = "disabled";
		};

		pwmb: pwm@406880 {
			compatible = "brcm,bcm7038-pwm";
			reg = <0x406880 0x28>;
			#pwm-cells = <2>;
			clocks = <&upg_clk>;
			status = "disabled";
		};

		watchdog: watchdog@4067e8 {
			clocks = <&upg_clk>;
			compatible = "brcm,bcm7038-wdt";
			reg = <0x4067e8 0x14>;
			status = "disabled";
		};

		upg_gio: gpio@406700 {
			compatible = "brcm,brcmstb-gpio";
			reg = <0x406700 0x80>;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupt-parent = <&upg_irq0_intc>;
			interrupts = <6>;
			brcm,gpio-bank-widths = <32 32 32 27>;
		};

		enet0: ethernet@468000 {
			phy-mode = "internal";
			phy-handle = <&phy1>;
			mac-address = [ 00 10 18 36 23 1a ];
			compatible = "brcm,genet-v1";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			reg = <0x468000 0x3c8c>;
			interrupts = <69>, <79>;
			interrupt-parent = <&periph_intc>;
			status = "disabled";

			mdio@e14 {
				compatible = "brcm,genet-mdio-v1";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0xe14 0x8>;

				phy1: ethernet-phy@1 {
					max-speed = <100>;
					reg = <0x1>;
					compatible = "brcm,65nm-ephy",
						"ethernet-phy-ieee802.3-c22";
				};
			};
		};

		ehci0: usb@488300 {
			compatible = "brcm,bcm7420-ehci", "generic-ehci";
			reg = <0x488300 0x100>;
			interrupt-parent = <&periph_intc>;
			interrupts = <60>;
			status = "disabled";
		};

		ohci0: usb@488400 {
			compatible = "brcm,bcm7420-ohci", "generic-ohci";
			reg = <0x488400 0x100>;
			native-endian;
			no-big-frame-no;
			interrupt-parent = <&periph_intc>;
			interrupts = <61>;
			status = "disabled";
		};

		ehci1: usb@488500 {
			compatible = "brcm,bcm7420-ehci", "generic-ehci";
			reg = <0x488500 0x100>;
			interrupt-parent = <&periph_intc>;
			interrupts = <55>;
			status = "disabled";
		};

		ohci1: usb@488600 {
			compatible = "brcm,bcm7420-ohci", "generic-ohci";
			reg = <0x488600 0x100>;
			native-endian;
			no-big-frame-no;
			interrupt-parent = <&periph_intc>;
			interrupts = <62>;
			status = "disabled";
		};

		spi_l2_intc: interrupt-controller@411d00 {
			compatible = "brcm,l2-intc";
			reg = <0x411d00 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&periph_intc>;
			interrupts = <78>;
		};

		qspi: spi@443000 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "brcm,spi-bcm-qspi",
				     "brcm,spi-brcmstb-qspi";
			clocks = <&upg_clk>;
			reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
			reg-names = "cs_reg", "hif_mspi", "bspi";
			interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
			interrupt-parent = <&spi_l2_intc>;
			interrupt-names = "spi_lr_fullness_reached",
					  "spi_lr_session_aborted",
					  "spi_lr_impatient",
					  "spi_lr_session_done",
					  "spi_lr_overread",
					  "mspi_done",
					  "mspi_halted";
			status = "disabled";
		};

		mspi: spi@406400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,spi-bcm-qspi",
				     "brcm,spi-brcmstb-mspi";
			clocks = <&upg_clk>;
			reg = <0x406400 0x180>;
			reg-names = "mspi";
			interrupts = <0x14>;
			interrupt-parent = <&upg_irq0_intc>;
			interrupt-names = "mspi_done";
			status = "disabled";
		};
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
8945e37e KC	2	/ {
	3	#address-cells = <1>;
	4	#size-cells = <1>;
	5	compatible = "brcm,bcm7420";
	6
	7	cpus {
	8	#address-cells = <1>;
	9	#size-cells = <0>;
	10
	11	mips-hpt-frequency = <93750000>;
	12
	13	cpu@0 {
	14	compatible = "brcm,bmips5000";
	15	device_type = "cpu";
	16	reg = <0>;
	17	};
	18
	19	cpu@1 {
	20	compatible = "brcm,bmips5000";
	21	device_type = "cpu";
	22	reg = <1>;
	23	};
	24	};
	25
	26	aliases {
	27	uart0 = &uart0;
	28	};
	29
a2c510a2	30	cpu_intc: interrupt-controller {
8945e37e KC	31	#address-cells = <0>;
	32	compatible = "mti,cpu-interrupt-controller";
	33
	34	interrupt-controller;
	35	#interrupt-cells = <1>;
	36	};
	37
	38	clocks {
	39	uart_clk: uart_clk {
	40	compatible = "fixed-clock";
	41	#clock-cells = <0>;
	42	clock-frequency = <81000000>;
	43	};
7bbe59dd JS	44
	45	upg_clk: upg_clk {
	46	compatible = "fixed-clock";
	47	#clock-cells = <0>;
	48	clock-frequency = <27000000>;
	49	};
8945e37e KC	50	};
	51
	52	rdb {
	53	#address-cells = <1>;
	54	#size-cells = <1>;
	55
	56	compatible = "simple-bus";
	57	ranges = <0 0x10000000 0x01000000>;
	58
a2c510a2	59	periph_intc: interrupt-controller@441400 {
8945e37e KC	60	compatible = "brcm,bcm7038-l1-intc";
	61	reg = <0x441400 0x30>, <0x441600 0x30>;
	62
	63	interrupt-controller;
	64	#interrupt-cells = <1>;
	65
	66	interrupt-parent = <&cpu_intc>;
	67	interrupts = <2>, <3>;
	68	};
	69
a2c510a2	70	sun_l2_intc: interrupt-controller@401800 {
8945e37e KC	71	compatible = "brcm,l2-intc";
	72	reg = <0x401800 0x30>;
	73	interrupt-controller;
	74	#interrupt-cells = <1>;
	75	interrupt-parent = <&periph_intc>;
	76	interrupts = <23>;
	77	};
	78
	79	gisb-arb@400000 {
	80	compatible = "brcm,bcm7400-gisb-arb";
	81	reg = <0x400000 0xdc>;
	82	native-endian;
	83	interrupt-parent = <&sun_l2_intc>;
	84	interrupts = <0>, <2>;
	85	brcm,gisb-arb-master-mask = <0x3ff>;
	86	brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
	87	"pcie_0", "bsp_0", "rdc_0",
	88	"rptd_0", "avd_0", "avd_1",
	89	"jtag_0";
	90	};
	91
a2c510a2	92	upg_irq0_intc: interrupt-controller@406780 {
8945e37e KC	93	compatible = "brcm,bcm7120-l2-intc";
	94	reg = <0x406780 0x8>;
	95
d783738c	96	brcm,int-map-mask = <0x44>, <0x1f000000>, <0x100000>;
8945e37e KC	97	brcm,int-fwd-mask = <0x70000>;
	98
	99	interrupt-controller;
	100	#interrupt-cells = <1>;
	101
	102	interrupt-parent = <&periph_intc>;
d783738c JS	103	interrupts = <18>, <19>, <20>;
d783738c JS	104	interrupt-names = "upg_main", "upg_bsc", "upg_spi";
8945e37e KC	105	};
	106
	107	sun_top_ctrl: syscon@404000 {
	108	compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
	109	reg = <0x404000 0x60c>;
25d6463e	110	native-endian;
8945e37e KC	111	};
	112
	113	reboot {
	114	compatible = "brcm,bcm7038-reboot";
	115	syscon = <&sun_top_ctrl 0x8 0x14>;
	116	};
	117
	118	uart0: serial@406b00 {
	119	compatible = "ns16550a";
	120	reg = <0x406b00 0x20>;
	121	reg-io-width = <0x4>;
	122	reg-shift = <0x2>;
	123	interrupt-parent = <&periph_intc>;
	124	interrupts = <21>;
	125	clocks = <&uart_clk>;
	126	status = "disabled";
	127	};
	128
5c40d493 JS	129	uart1: serial@406b40 {
	130	compatible = "ns16550a";
	131	reg = <0x406b40 0x20>;
	132	reg-io-width = <0x4>;
	133	reg-shift = <0x2>;
	134	interrupt-parent = <&periph_intc>;
	135	interrupts = <64>;
	136	clocks = <&uart_clk>;
	137	status = "disabled";
	138	};
	139
	140	uart2: serial@406b80 {
	141	compatible = "ns16550a";
	142	reg = <0x406b80 0x20>;
	143	reg-io-width = <0x4>;
	144	reg-shift = <0x2>;
	145	interrupt-parent = <&periph_intc>;
	146	interrupts = <65>;
	147	clocks = <&uart_clk>;
	148	status = "disabled";
	149	};
	150
	151	bsca: i2c@406200 {
	152	clock-frequency = <390000>;
	153	compatible = "brcm,brcmstb-i2c";
	154	interrupt-parent = <&upg_irq0_intc>;
	155	reg = <0x406200 0x58>;
	156	interrupts = <24>;
	157	interrupt-names = "upg_bsca";
	158	status = "disabled";
	159	};
	160
	161	bscb: i2c@406280 {
	162	clock-frequency = <390000>;
	163	compatible = "brcm,brcmstb-i2c";
	164	interrupt-parent = <&upg_irq0_intc>;
	165	reg = <0x406280 0x58>;
	166	interrupts = <25>;
	167	interrupt-names = "upg_bscb";
	168	status = "disabled";
	169	};
	170
	171	bscc: i2c@406300 {
	172	clock-frequency = <390000>;
	173	compatible = "brcm,brcmstb-i2c";
	174	interrupt-parent = <&upg_irq0_intc>;
	175	reg = <0x406300 0x58>;
	176	interrupts = <26>;
	177	interrupt-names = "upg_bscc";
	178	status = "disabled";
	179	};
	180
	181	bscd: i2c@406380 {
	182	clock-frequency = <390000>;
	183	compatible = "brcm,brcmstb-i2c";
	184	interrupt-parent = <&upg_irq0_intc>;
	185	reg = <0x406380 0x58>;
	186	interrupts = <27>;
	187	interrupt-names = "upg_bscd";
	188	status = "disabled";
	189	};
	190
	191	bsce: i2c@406800 {
	192	clock-frequency = <390000>;
193	compatible = "brcm,brcmstb-i2c";
194	interrupt-parent = <&upg_irq0_intc>;
195	reg = <0x406800 0x58>;
196	interrupts = <28>;
197	interrupt-names = "upg_bsce";
198	status = "disabled";
199	};
200
7bbe59dd JS	201	pwma: pwm@406580 {
	202	compatible = "brcm,bcm7038-pwm";
	203	reg = <0x406580 0x28>;
	204	#pwm-cells = <2>;
	205	clocks = <&upg_clk>;
	206	status = "disabled";
	207	};
	208
	209	pwmb: pwm@406880 {
	210	compatible = "brcm,bcm7038-pwm";
	211	reg = <0x406880 0x28>;
	212	#pwm-cells = <2>;
	213	clocks = <&upg_clk>;
	214	status = "disabled";
	215	};
	216
b68c2575 JS	217	watchdog: watchdog@4067e8 {
	218	clocks = <&upg_clk>;
	219	compatible = "brcm,bcm7038-wdt";
	220	reg = <0x4067e8 0x14>;
	221	status = "disabled";
	222	};
	223
c707844d JS	224	upg_gio: gpio@406700 {
	225	compatible = "brcm,brcmstb-gpio";
	226	reg = <0x406700 0x80>;
	227	#gpio-cells = <2>;
	228	#interrupt-cells = <2>;
	229	gpio-controller;
	230	interrupt-controller;
	231	interrupt-parent = <&upg_irq0_intc>;
	232	interrupts = <6>;
	233	brcm,gpio-bank-widths = <32 32 32 27>;
	234	};
	235
8945e37e KC	236	enet0: ethernet@468000 {
	237	phy-mode = "internal";
	238	phy-handle = <&phy1>;
	239	mac-address = [ 00 10 18 36 23 1a ];
	240	compatible = "brcm,genet-v1";
	241	#address-cells = <0x1>;
	242	#size-cells = <0x1>;
	243	reg = <0x468000 0x3c8c>;
	244	interrupts = <69>, <79>;
	245	interrupt-parent = <&periph_intc>;
	246	status = "disabled";
	247
	248	mdio@e14 {
	249	compatible = "brcm,genet-mdio-v1";
	250	#address-cells = <0x1>;
	251	#size-cells = <0x0>;
	252	reg = <0xe14 0x8>;
	253
	254	phy1: ethernet-phy@1 {
	255	max-speed = <100>;
	256	reg = <0x1>;
	257	compatible = "brcm,65nm-ephy",
	258	"ethernet-phy-ieee802.3-c22";
	259	};
	260	};
	261	};
	262
	263	ehci0: usb@488300 {
	264	compatible = "brcm,bcm7420-ehci", "generic-ehci";
	265	reg = <0x488300 0x100>;
	266	interrupt-parent = <&periph_intc>;
	267	interrupts = <60>;
	268	status = "disabled";
	269	};
	270
	271	ohci0: usb@488400 {
	272	compatible = "brcm,bcm7420-ohci", "generic-ohci";
	273	reg = <0x488400 0x100>;
	274	native-endian;
	275	no-big-frame-no;
	276	interrupt-parent = <&periph_intc>;
	277	interrupts = <61>;
	278	status = "disabled";
	279	};
	280
	281	ehci1: usb@488500 {
	282	compatible = "brcm,bcm7420-ehci", "generic-ehci";
	283	reg = <0x488500 0x100>;
	284	interrupt-parent = <&periph_intc>;
	285	interrupts = <55>;
	286	status = "disabled";
	287	};
	288
	289	ohci1: usb@488600 {
	290	compatible = "brcm,bcm7420-ohci", "generic-ohci";
	291	reg = <0x488600 0x100>;
	292	native-endian;
	293	no-big-frame-no;
	294	interrupt-parent = <&periph_intc>;
	295	interrupts = <62>;
	296	status = "disabled";
	297	};
d783738c JS	298
	299	spi_l2_intc: interrupt-controller@411d00 {
	300	compatible = "brcm,l2-intc";
	301	reg = <0x411d00 0x30>;
	302	interrupt-controller;
	303	#interrupt-cells = <1>;
	304	interrupt-parent = <&periph_intc>;
	305	interrupts = <78>;
	306	};
	307
	308	qspi: spi@443000 {
	309	#address-cells = <0x1>;
	310	#size-cells = <0x0>;
	311	compatible = "brcm,spi-bcm-qspi",
	312	"brcm,spi-brcmstb-qspi";
	313	clocks = <&upg_clk>;
	314	reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
	315	reg-names = "cs_reg", "hif_mspi", "bspi";
	316	interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
	317	interrupt-parent = <&spi_l2_intc>;
	318	interrupt-names = "spi_lr_fullness_reached",
	319	"spi_lr_session_aborted",
	320	"spi_lr_impatient",
	321	"spi_lr_session_done",
	322	"spi_lr_overread",
	323	"mspi_done",
	324	"mspi_halted";
	325	status = "disabled";
	326	};
	327
	328	mspi: spi@406400 {
	329	#address-cells = <1>;
	330	#size-cells = <0>;
	331	compatible = "brcm,spi-bcm-qspi",
	332	"brcm,spi-brcmstb-mspi";
	333	clocks = <&upg_clk>;
	334	reg = <0x406400 0x180>;
	335	reg-names = "mspi";
	336	interrupts = <0x14>;
	337	interrupt-parent = <&upg_irq0_intc>;
	338	interrupt-names = "mspi_done";
	339	status = "disabled";
	340	};
8945e37e KC	341	};
8945e37e KC	342	};