Commit | Line | Data |
---|---|---|
8945e37e KC |
1 | / { |
2 | #address-cells = <1>; | |
3 | #size-cells = <1>; | |
4 | compatible = "brcm,bcm7125"; | |
5 | ||
6 | cpus { | |
7 | #address-cells = <1>; | |
8 | #size-cells = <0>; | |
9 | ||
10 | mips-hpt-frequency = <202500000>; | |
11 | ||
12 | cpu@0 { | |
13 | compatible = "brcm,bmips4380"; | |
14 | device_type = "cpu"; | |
15 | reg = <0>; | |
16 | }; | |
17 | ||
18 | cpu@1 { | |
19 | compatible = "brcm,bmips4380"; | |
20 | device_type = "cpu"; | |
21 | reg = <1>; | |
22 | }; | |
23 | }; | |
24 | ||
25 | aliases { | |
26 | uart0 = &uart0; | |
27 | }; | |
28 | ||
29 | cpu_intc: cpu_intc { | |
30 | #address-cells = <0>; | |
31 | compatible = "mti,cpu-interrupt-controller"; | |
32 | ||
33 | interrupt-controller; | |
34 | #interrupt-cells = <1>; | |
35 | }; | |
36 | ||
37 | clocks { | |
38 | uart_clk: uart_clk { | |
39 | compatible = "fixed-clock"; | |
40 | #clock-cells = <0>; | |
41 | clock-frequency = <81000000>; | |
42 | }; | |
43 | }; | |
44 | ||
45 | rdb { | |
46 | #address-cells = <1>; | |
47 | #size-cells = <1>; | |
48 | ||
49 | compatible = "simple-bus"; | |
50 | ranges = <0 0x10000000 0x01000000>; | |
51 | ||
52 | periph_intc: periph_intc@441400 { | |
53 | compatible = "brcm,bcm7038-l1-intc"; | |
54 | reg = <0x441400 0x30>, <0x441600 0x30>; | |
55 | ||
56 | interrupt-controller; | |
57 | #interrupt-cells = <1>; | |
58 | ||
59 | interrupt-parent = <&cpu_intc>; | |
60 | interrupts = <2>, <3>; | |
61 | }; | |
62 | ||
63 | sun_l2_intc: sun_l2_intc@401800 { | |
64 | compatible = "brcm,l2-intc"; | |
65 | reg = <0x401800 0x30>; | |
66 | interrupt-controller; | |
67 | #interrupt-cells = <1>; | |
68 | interrupt-parent = <&periph_intc>; | |
69 | interrupts = <23>; | |
70 | }; | |
71 | ||
72 | gisb-arb@400000 { | |
73 | compatible = "brcm,bcm7400-gisb-arb"; | |
74 | reg = <0x400000 0xdc>; | |
75 | native-endian; | |
76 | interrupt-parent = <&sun_l2_intc>; | |
77 | interrupts = <0>, <2>; | |
78 | brcm,gisb-arb-master-mask = <0x2f7>; | |
79 | brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0", | |
80 | "bsp_0", "rdc_0", "rptd_0", | |
81 | "avd_0", "jtag_0"; | |
82 | }; | |
83 | ||
84 | upg_irq0_intc: upg_irq0_intc@406780 { | |
85 | compatible = "brcm,bcm7120-l2-intc"; | |
86 | reg = <0x406780 0x8>; | |
87 | ||
88 | brcm,int-map-mask = <0x44>; | |
89 | brcm,int-fwd-mask = <0x70000>; | |
90 | ||
91 | interrupt-controller; | |
92 | #interrupt-cells = <1>; | |
93 | ||
94 | interrupt-parent = <&periph_intc>; | |
95 | interrupts = <18>; | |
96 | }; | |
97 | ||
98 | sun_top_ctrl: syscon@404000 { | |
99 | compatible = "brcm,bcm7125-sun-top-ctrl", "syscon"; | |
100 | reg = <0x404000 0x60c>; | |
320549a2 | 101 | little-endian; |
8945e37e KC |
102 | }; |
103 | ||
104 | reboot { | |
105 | compatible = "brcm,bcm7038-reboot"; | |
106 | syscon = <&sun_top_ctrl 0x8 0x14>; | |
107 | }; | |
108 | ||
109 | uart0: serial@406b00 { | |
110 | compatible = "ns16550a"; | |
111 | reg = <0x406b00 0x20>; | |
112 | reg-io-width = <0x4>; | |
113 | reg-shift = <0x2>; | |
114 | native-endian; | |
115 | interrupt-parent = <&periph_intc>; | |
116 | interrupts = <21>; | |
117 | clocks = <&uart_clk>; | |
118 | status = "disabled"; | |
119 | }; | |
120 | ||
121 | ehci0: usb@488300 { | |
122 | compatible = "brcm,bcm7125-ehci", "generic-ehci"; | |
123 | reg = <0x488300 0x100>; | |
124 | native-endian; | |
125 | interrupt-parent = <&periph_intc>; | |
126 | interrupts = <60>; | |
127 | status = "disabled"; | |
128 | }; | |
129 | ||
130 | ohci0: usb@488400 { | |
131 | compatible = "brcm,bcm7125-ohci", "generic-ohci"; | |
132 | reg = <0x488400 0x100>; | |
133 | native-endian; | |
134 | interrupt-parent = <&periph_intc>; | |
135 | interrupts = <61>; | |
136 | status = "disabled"; | |
137 | }; | |
138 | }; | |
139 | }; |