[linux-2.6-block.git] / arch / mips / bmips / setup.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
 */

#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/bootmem.h>
#include <linux/clk-provider.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <linux/smp.h>
#include <asm/addrspace.h>
#include <asm/bmips.h>
#include <asm/bootinfo.h>
#include <asm/cpu-type.h>
#include <asm/mipsregs.h>
#include <asm/prom.h>
#include <asm/smp-ops.h>
#include <asm/time.h>
#include <asm/traps.h>

#define RELO_NORMAL_VEC		BIT(18)

#define REG_BCM6328_OTP		((void __iomem *)CKSEG1ADDR(0x1000062c))
#define BCM6328_TP1_DISABLED	BIT(9)

static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;

struct bmips_quirk {
	const char		*compatible;
	void			(*quirk_fn)(void);
};

static void kbase_setup(void)
{
	__raw_writel(kbase | RELO_NORMAL_VEC,
		     BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
	ebase = kbase;
}

static void bcm3384_viper_quirks(void)
{
	/*
	 * Some experimental CM boxes are set up to let CM own the Viper TP0
	 * and let Linux own TP1.  This requires moving the kernel
	 * load address to a non-conflicting region (e.g. via
	 * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
	 * If we detect this condition, we need to move the MIPS exception
	 * vectors up to an area that we own.
	 *
	 * This is distinct from the OTHER special case mentioned in
	 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
	 * logical CPU#1).  For the Viper TP1 case, SMP is off limits.
	 *
	 * Also note that many BMIPS435x CPUs do not have a
	 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
	 * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
	 */
	board_ebase_setup = &kbase_setup;
	bmips_smp_enabled = 0;
}

static void bcm63xx_fixup_cpu1(void)
{
	/*
	 * The bootloader has set up the CPU1 reset vector at
	 * 0xa000_0200.
	 * This conflicts with the special interrupt vector (IV).
	 * The bootloader has also set up CPU1 to respond to the wrong
	 * IPI interrupt.
	 * Here we will start up CPU1 in the background and ask it to
	 * reconfigure itself then go back to sleep.
	 */
	memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
	__sync();
	set_c0_cause(C_SW0);
	cpumask_set_cpu(1, &bmips_booted_mask);
}

static void bcm6328_quirks(void)
{
	/* Check CPU1 status in OTP (it is usually disabled) */
	if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
		bmips_smp_enabled = 0;
	else
		bcm63xx_fixup_cpu1();
}

static void bcm6368_quirks(void)
{
	bcm63xx_fixup_cpu1();
}

static const struct bmips_quirk bmips_quirk_list[] = {
	{ "brcm,bcm3384-viper",		&bcm3384_viper_quirks		},
	{ "brcm,bcm33843-viper",	&bcm3384_viper_quirks		},
	{ "brcm,bcm6328",		&bcm6328_quirks			},
	{ "brcm,bcm6368",		&bcm6368_quirks			},
	{ "brcm,bcm63168",		&bcm6368_quirks			},
	{ },
};

void __init prom_init(void)
{
	register_bmips_smp_ops();
}

void __init prom_free_prom_memory(void)
{
}

const char *get_system_type(void)
{
	return "Generic BMIPS kernel";
}

void __init plat_time_init(void)
{
	struct device_node *np;
	u32 freq;

	np = of_find_node_by_name(NULL, "cpus");
	if (!np)
		panic("missing 'cpus' DT node");
	if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
		panic("missing 'mips-hpt-frequency' property");
	of_node_put(np);

	mips_hpt_frequency = freq;
}

void __init plat_mem_setup(void)
{
	void *dtb;
	const struct bmips_quirk *q;

	set_io_port_base(0);
	ioport_resource.start = 0;
	ioport_resource.end = ~0;

	/* intended to somewhat resemble ARM; see Documentation/arm/Booting */
	if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
		dtb = phys_to_virt(fw_arg2);
	else if (fw_arg0 == -2) /* UHI interface */
		dtb = (void *)fw_arg1;
	else if (__dtb_start != __dtb_end)
		dtb = (void *)__dtb_start;
	else
		panic("no dtb found");

	__dt_setup_arch(dtb);

	for (q = bmips_quirk_list; q->quirk_fn; q++) {
		if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
					     q->compatible)) {
			q->quirk_fn();
		}
	}
}

void __init device_tree_init(void)
{
	struct device_node *np;

	unflatten_and_copy_device_tree();

	/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
	np = of_find_node_by_name(NULL, "cpus");
	if (np && of_get_available_child_count(np) <= 1)
		bmips_smp_enabled = 0;
	of_node_put(np);
}

int __init plat_of_setup(void)
{
	return __dt_register_buses("simple-bus", NULL);
}

arch_initcall(plat_of_setup);

static int __init plat_dev_init(void)
{
	of_clk_init(NULL);
	return 0;
}

device_initcall(plat_dev_init);
Commit	Line	Data
d666cd02 KC	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
	7	* Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
	8	*/
	9
	10	#include <linux/init.h>
4b049a6b	11	#include <linux/bitops.h>
d666cd02 KC	12	#include <linux/bootmem.h>
	13	#include <linux/clk-provider.h>
	14	#include <linux/ioport.h>
4b049a6b KC	15	#include <linux/kernel.h>
4b049a6b KC	16	#include <linux/io.h>
d666cd02 KC	17	#include <linux/of.h>
	18	#include <linux/of_fdt.h>
	19	#include <linux/of_platform.h>
	20	#include <linux/smp.h>
	21	#include <asm/addrspace.h>
	22	#include <asm/bmips.h>
	23	#include <asm/bootinfo.h>
4b049a6b KC	24	#include <asm/cpu-type.h>
4b049a6b KC	25	#include <asm/mipsregs.h>
d666cd02 KC	26	#include <asm/prom.h>
	27	#include <asm/smp-ops.h>
	28	#include <asm/time.h>
4b049a6b KC	29	#include <asm/traps.h>
	30
	31	#define RELO_NORMAL_VEC BIT(18)
	32
	33	#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
	34	#define BCM6328_TP1_DISABLED BIT(9)
	35
	36	static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
	37
	38	struct bmips_quirk {
	39	const char *compatible;
	40	void (*quirk_fn)(void);
	41	};
	42
	43	static void kbase_setup(void)
	44	{
	45	__raw_writel(kbase \| RELO_NORMAL_VEC,
	46	BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
	47	ebase = kbase;
	48	}
	49
	50	static void bcm3384_viper_quirks(void)
	51	{
	52	/*
	53	* Some experimental CM boxes are set up to let CM own the Viper TP0
	54	* and let Linux own TP1. This requires moving the kernel
	55	* load address to a non-conflicting region (e.g. via
	56	* CONFIG_PHYSICAL_START) and supplying an alternate DTB.
	57	* If we detect this condition, we need to move the MIPS exception
	58	* vectors up to an area that we own.
	59	*
	60	* This is distinct from the OTHER special case mentioned in
	61	* smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
	62	* logical CPU#1). For the Viper TP1 case, SMP is off limits.
	63	*
	64	* Also note that many BMIPS435x CPUs do not have a
	65	* BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
	66	* write VMLINUX_LOAD_ADDRESS into that register on every SoC.
	67	*/
	68	board_ebase_setup = &kbase_setup;
	69	bmips_smp_enabled = 0;
	70	}
	71
	72	static void bcm63xx_fixup_cpu1(void)
	73	{
	74	/*
	75	* The bootloader has set up the CPU1 reset vector at
	76	* 0xa000_0200.
	77	* This conflicts with the special interrupt vector (IV).
	78	* The bootloader has also set up CPU1 to respond to the wrong
	79	* IPI interrupt.
	80	* Here we will start up CPU1 in the background and ask it to
	81	* reconfigure itself then go back to sleep.
	82	*/
	83	memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
	84	__sync();
	85	set_c0_cause(C_SW0);
	86	cpumask_set_cpu(1, &bmips_booted_mask);
	87	}
	88
	89	static void bcm6328_quirks(void)
	90	{
	91	/* Check CPU1 status in OTP (it is usually disabled) */
	92	if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
93	bmips_smp_enabled = 0;
94	else
95	bcm63xx_fixup_cpu1();
96	}
97
98	static void bcm6368_quirks(void)
99	{
100	bcm63xx_fixup_cpu1();
101	}
102
103	static const struct bmips_quirk bmips_quirk_list[] = {
104	{ "brcm,bcm3384-viper", &bcm3384_viper_quirks },
105	{ "brcm,bcm33843-viper", &bcm3384_viper_quirks },
106	{ "brcm,bcm6328", &bcm6328_quirks },
107	{ "brcm,bcm6368", &bcm6368_quirks },
16580796	108	{ "brcm,bcm63168", &bcm6368_quirks },
4b049a6b KC	109	{ },
4b049a6b KC	110	};
d666cd02 KC	111
	112	void __init prom_init(void)
	113	{
	114	register_bmips_smp_ops();
	115	}
	116
	117	void __init prom_free_prom_memory(void)
	118	{
	119	}
	120
	121	const char *get_system_type(void)
	122	{
5f2d4459	123	return "Generic BMIPS kernel";
d666cd02 KC	124	}
	125
	126	void __init plat_time_init(void)
	127	{
	128	struct device_node *np;
	129	u32 freq;
	130
	131	np = of_find_node_by_name(NULL, "cpus");
	132	if (!np)
	133	panic("missing 'cpus' DT node");
	134	if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
	135	panic("missing 'mips-hpt-frequency' property");
	136	of_node_put(np);
	137
	138	mips_hpt_frequency = freq;
	139	}
	140
	141	void __init plat_mem_setup(void)
	142	{
4b049a6b KC	143	void *dtb;
4b049a6b KC	144	const struct bmips_quirk *q;
d666cd02 KC	145
	146	set_io_port_base(0);
	147	ioport_resource.start = 0;
	148	ioport_resource.end = ~0;
	149
	150	/* intended to somewhat resemble ARM; see Documentation/arm/Booting */
	151	if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
	152	dtb = phys_to_virt(fw_arg2);
ca668a2d JG	153	else if (fw_arg0 == -2) /* UHI interface */
ca668a2d JG	154	dtb = (void *)fw_arg1;
4b049a6b KC	155	else if (__dtb_start != __dtb_end)
	156	dtb = (void *)__dtb_start;
	157	else
	158	panic("no dtb found");
d666cd02 KC	159
d666cd02 KC	160	__dt_setup_arch(dtb);
4b049a6b KC	161
	162	for (q = bmips_quirk_list; q->quirk_fn; q++) {
	163	if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
	164	q->compatible)) {
	165	q->quirk_fn();
	166	}
	167	}
d666cd02 KC	168	}
	169
	170	void __init device_tree_init(void)
	171	{
	172	struct device_node *np;
	173
	174	unflatten_and_copy_device_tree();
	175
	176	/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
	177	np = of_find_node_by_name(NULL, "cpus");
	178	if (np && of_get_available_child_count(np) <= 1)
	179	bmips_smp_enabled = 0;
	180	of_node_put(np);
	181	}
	182
	183	int __init plat_of_setup(void)
	184	{
c4b25709	185	return __dt_register_buses("simple-bus", NULL);
d666cd02 KC	186	}
	187
	188	arch_initcall(plat_of_setup);
	189
	190	static int __init plat_dev_init(void)
	191	{
	192	of_clk_init(NULL);
	193	return 0;
	194	}
	195
	196	device_initcall(plat_dev_init);