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e7300d04 MB |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> | |
7 | * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/cpu.h> | |
602977b0 | 13 | #include <asm/cpu.h> |
2b5b9b78 | 14 | #include <asm/cpu-info.h> |
602977b0 | 15 | #include <asm/mipsregs.h> |
e7300d04 MB |
16 | #include <bcm63xx_cpu.h> |
17 | #include <bcm63xx_regs.h> | |
18 | #include <bcm63xx_io.h> | |
19 | #include <bcm63xx_irq.h> | |
20 | ||
21 | const unsigned long *bcm63xx_regs_base; | |
22 | EXPORT_SYMBOL(bcm63xx_regs_base); | |
23 | ||
24 | const int *bcm63xx_irqs; | |
25 | EXPORT_SYMBOL(bcm63xx_irqs); | |
26 | ||
27 | static u16 bcm63xx_cpu_id; | |
28 | static u16 bcm63xx_cpu_rev; | |
29 | static unsigned int bcm63xx_cpu_freq; | |
30 | static unsigned int bcm63xx_memory_size; | |
31 | ||
32 | /* | |
33 | * 6338 register sets and irqs | |
34 | */ | |
35 | static const unsigned long bcm96338_regs_base[] = { | |
36 | [RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE, | |
37 | [RSET_PERF] = BCM_6338_PERF_BASE, | |
38 | [RSET_TIMER] = BCM_6338_TIMER_BASE, | |
39 | [RSET_WDT] = BCM_6338_WDT_BASE, | |
40 | [RSET_UART0] = BCM_6338_UART0_BASE, | |
524ef29c | 41 | [RSET_UART1] = BCM_6338_UART1_BASE, |
e7300d04 MB |
42 | [RSET_GPIO] = BCM_6338_GPIO_BASE, |
43 | [RSET_SPI] = BCM_6338_SPI_BASE, | |
44 | [RSET_OHCI0] = BCM_6338_OHCI0_BASE, | |
45 | [RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE, | |
46 | [RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE, | |
47 | [RSET_UDC0] = BCM_6338_UDC0_BASE, | |
48 | [RSET_MPI] = BCM_6338_MPI_BASE, | |
49 | [RSET_PCMCIA] = BCM_6338_PCMCIA_BASE, | |
50 | [RSET_SDRAM] = BCM_6338_SDRAM_BASE, | |
51 | [RSET_DSL] = BCM_6338_DSL_BASE, | |
52 | [RSET_ENET0] = BCM_6338_ENET0_BASE, | |
53 | [RSET_ENET1] = BCM_6338_ENET1_BASE, | |
54 | [RSET_ENETDMA] = BCM_6338_ENETDMA_BASE, | |
55 | [RSET_MEMC] = BCM_6338_MEMC_BASE, | |
56 | [RSET_DDR] = BCM_6338_DDR_BASE, | |
57 | }; | |
58 | ||
59 | static const int bcm96338_irqs[] = { | |
60 | [IRQ_TIMER] = BCM_6338_TIMER_IRQ, | |
61 | [IRQ_UART0] = BCM_6338_UART0_IRQ, | |
62 | [IRQ_DSL] = BCM_6338_DSL_IRQ, | |
63 | [IRQ_ENET0] = BCM_6338_ENET0_IRQ, | |
64 | [IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ, | |
65 | [IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ, | |
66 | [IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ, | |
67 | }; | |
68 | ||
69 | /* | |
70 | * 6345 register sets and irqs | |
71 | */ | |
72 | static const unsigned long bcm96345_regs_base[] = { | |
73 | [RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE, | |
74 | [RSET_PERF] = BCM_6345_PERF_BASE, | |
75 | [RSET_TIMER] = BCM_6345_TIMER_BASE, | |
76 | [RSET_WDT] = BCM_6345_WDT_BASE, | |
77 | [RSET_UART0] = BCM_6345_UART0_BASE, | |
524ef29c | 78 | [RSET_UART1] = BCM_6345_UART1_BASE, |
e7300d04 MB |
79 | [RSET_GPIO] = BCM_6345_GPIO_BASE, |
80 | [RSET_SPI] = BCM_6345_SPI_BASE, | |
81 | [RSET_UDC0] = BCM_6345_UDC0_BASE, | |
82 | [RSET_OHCI0] = BCM_6345_OHCI0_BASE, | |
83 | [RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE, | |
84 | [RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE, | |
85 | [RSET_MPI] = BCM_6345_MPI_BASE, | |
86 | [RSET_PCMCIA] = BCM_6345_PCMCIA_BASE, | |
87 | [RSET_DSL] = BCM_6345_DSL_BASE, | |
88 | [RSET_ENET0] = BCM_6345_ENET0_BASE, | |
89 | [RSET_ENET1] = BCM_6345_ENET1_BASE, | |
90 | [RSET_ENETDMA] = BCM_6345_ENETDMA_BASE, | |
91 | [RSET_EHCI0] = BCM_6345_EHCI0_BASE, | |
92 | [RSET_SDRAM] = BCM_6345_SDRAM_BASE, | |
93 | [RSET_MEMC] = BCM_6345_MEMC_BASE, | |
94 | [RSET_DDR] = BCM_6345_DDR_BASE, | |
95 | }; | |
96 | ||
97 | static const int bcm96345_irqs[] = { | |
98 | [IRQ_TIMER] = BCM_6345_TIMER_IRQ, | |
99 | [IRQ_UART0] = BCM_6345_UART0_IRQ, | |
100 | [IRQ_DSL] = BCM_6345_DSL_IRQ, | |
101 | [IRQ_ENET0] = BCM_6345_ENET0_IRQ, | |
102 | [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ, | |
103 | [IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ, | |
104 | [IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ, | |
105 | }; | |
106 | ||
107 | /* | |
108 | * 6348 register sets and irqs | |
109 | */ | |
110 | static const unsigned long bcm96348_regs_base[] = { | |
111 | [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE, | |
112 | [RSET_PERF] = BCM_6348_PERF_BASE, | |
113 | [RSET_TIMER] = BCM_6348_TIMER_BASE, | |
114 | [RSET_WDT] = BCM_6348_WDT_BASE, | |
115 | [RSET_UART0] = BCM_6348_UART0_BASE, | |
524ef29c | 116 | [RSET_UART1] = BCM_6348_UART1_BASE, |
e7300d04 MB |
117 | [RSET_GPIO] = BCM_6348_GPIO_BASE, |
118 | [RSET_SPI] = BCM_6348_SPI_BASE, | |
119 | [RSET_OHCI0] = BCM_6348_OHCI0_BASE, | |
120 | [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE, | |
121 | [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE, | |
122 | [RSET_MPI] = BCM_6348_MPI_BASE, | |
123 | [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE, | |
124 | [RSET_SDRAM] = BCM_6348_SDRAM_BASE, | |
125 | [RSET_DSL] = BCM_6348_DSL_BASE, | |
126 | [RSET_ENET0] = BCM_6348_ENET0_BASE, | |
127 | [RSET_ENET1] = BCM_6348_ENET1_BASE, | |
128 | [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE, | |
129 | [RSET_MEMC] = BCM_6348_MEMC_BASE, | |
130 | [RSET_DDR] = BCM_6348_DDR_BASE, | |
131 | }; | |
132 | ||
133 | static const int bcm96348_irqs[] = { | |
134 | [IRQ_TIMER] = BCM_6348_TIMER_IRQ, | |
135 | [IRQ_UART0] = BCM_6348_UART0_IRQ, | |
136 | [IRQ_DSL] = BCM_6348_DSL_IRQ, | |
137 | [IRQ_ENET0] = BCM_6348_ENET0_IRQ, | |
138 | [IRQ_ENET1] = BCM_6348_ENET1_IRQ, | |
139 | [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ, | |
140 | [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ, | |
141 | [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ, | |
142 | [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ, | |
143 | [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ, | |
144 | [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ, | |
145 | [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ, | |
146 | [IRQ_PCI] = BCM_6348_PCI_IRQ, | |
147 | }; | |
148 | ||
149 | /* | |
150 | * 6358 register sets and irqs | |
151 | */ | |
152 | static const unsigned long bcm96358_regs_base[] = { | |
153 | [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE, | |
154 | [RSET_PERF] = BCM_6358_PERF_BASE, | |
155 | [RSET_TIMER] = BCM_6358_TIMER_BASE, | |
156 | [RSET_WDT] = BCM_6358_WDT_BASE, | |
157 | [RSET_UART0] = BCM_6358_UART0_BASE, | |
524ef29c | 158 | [RSET_UART1] = BCM_6358_UART1_BASE, |
e7300d04 MB |
159 | [RSET_GPIO] = BCM_6358_GPIO_BASE, |
160 | [RSET_SPI] = BCM_6358_SPI_BASE, | |
161 | [RSET_OHCI0] = BCM_6358_OHCI0_BASE, | |
162 | [RSET_EHCI0] = BCM_6358_EHCI0_BASE, | |
163 | [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE, | |
164 | [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE, | |
165 | [RSET_MPI] = BCM_6358_MPI_BASE, | |
166 | [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE, | |
167 | [RSET_SDRAM] = BCM_6358_SDRAM_BASE, | |
168 | [RSET_DSL] = BCM_6358_DSL_BASE, | |
169 | [RSET_ENET0] = BCM_6358_ENET0_BASE, | |
170 | [RSET_ENET1] = BCM_6358_ENET1_BASE, | |
171 | [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE, | |
172 | [RSET_MEMC] = BCM_6358_MEMC_BASE, | |
173 | [RSET_DDR] = BCM_6358_DDR_BASE, | |
174 | }; | |
175 | ||
176 | static const int bcm96358_irqs[] = { | |
177 | [IRQ_TIMER] = BCM_6358_TIMER_IRQ, | |
178 | [IRQ_UART0] = BCM_6358_UART0_IRQ, | |
524ef29c | 179 | [IRQ_UART1] = BCM_6358_UART1_IRQ, |
e7300d04 MB |
180 | [IRQ_DSL] = BCM_6358_DSL_IRQ, |
181 | [IRQ_ENET0] = BCM_6358_ENET0_IRQ, | |
182 | [IRQ_ENET1] = BCM_6358_ENET1_IRQ, | |
183 | [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ, | |
184 | [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ, | |
185 | [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ, | |
186 | [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ, | |
187 | [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ, | |
188 | [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ, | |
189 | [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ, | |
190 | [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ, | |
191 | [IRQ_PCI] = BCM_6358_PCI_IRQ, | |
192 | }; | |
193 | ||
194 | u16 __bcm63xx_get_cpu_id(void) | |
195 | { | |
196 | return bcm63xx_cpu_id; | |
197 | } | |
198 | ||
199 | EXPORT_SYMBOL(__bcm63xx_get_cpu_id); | |
200 | ||
201 | u16 bcm63xx_get_cpu_rev(void) | |
202 | { | |
203 | return bcm63xx_cpu_rev; | |
204 | } | |
205 | ||
206 | EXPORT_SYMBOL(bcm63xx_get_cpu_rev); | |
207 | ||
208 | unsigned int bcm63xx_get_cpu_freq(void) | |
209 | { | |
210 | return bcm63xx_cpu_freq; | |
211 | } | |
212 | ||
213 | unsigned int bcm63xx_get_memory_size(void) | |
214 | { | |
215 | return bcm63xx_memory_size; | |
216 | } | |
217 | ||
218 | static unsigned int detect_cpu_clock(void) | |
219 | { | |
220 | unsigned int tmp, n1 = 0, n2 = 0, m1 = 0; | |
221 | ||
222 | /* BCM6338 has a fixed 240 Mhz frequency */ | |
223 | if (BCMCPU_IS_6338()) | |
224 | return 240000000; | |
225 | ||
226 | /* BCM6345 has a fixed 140Mhz frequency */ | |
227 | if (BCMCPU_IS_6345()) | |
228 | return 140000000; | |
229 | ||
230 | /* | |
231 | * frequency depends on PLL configuration: | |
232 | */ | |
233 | if (BCMCPU_IS_6348()) { | |
234 | /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */ | |
235 | tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); | |
236 | n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT; | |
237 | n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT; | |
238 | m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT; | |
239 | n1 += 1; | |
240 | n2 += 2; | |
241 | m1 += 1; | |
242 | } | |
243 | ||
244 | if (BCMCPU_IS_6358()) { | |
245 | /* 16MHz * N1 * N2 / M1_CPU */ | |
246 | tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); | |
247 | n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT; | |
248 | n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT; | |
249 | m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT; | |
250 | } | |
251 | ||
252 | return (16 * 1000000 * n1 * n2) / m1; | |
253 | } | |
254 | ||
255 | /* | |
256 | * attempt to detect the amount of memory installed | |
257 | */ | |
258 | static unsigned int detect_memory_size(void) | |
259 | { | |
260 | unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; | |
261 | u32 val; | |
262 | ||
263 | if (BCMCPU_IS_6345()) | |
264 | return (8 * 1024 * 1024); | |
265 | ||
266 | if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { | |
267 | val = bcm_sdram_readl(SDRAM_CFG_REG); | |
268 | rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT; | |
269 | cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT; | |
270 | is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0; | |
271 | banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; | |
272 | } | |
273 | ||
274 | if (BCMCPU_IS_6358()) { | |
275 | val = bcm_memc_readl(MEMC_CFG_REG); | |
276 | rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; | |
277 | cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; | |
278 | is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1; | |
279 | banks = 2; | |
280 | } | |
281 | ||
282 | /* 0 => 11 address bits ... 2 => 13 address bits */ | |
283 | rows += 11; | |
284 | ||
285 | /* 0 => 8 address bits ... 2 => 10 address bits */ | |
286 | cols += 8; | |
287 | ||
288 | return 1 << (cols + rows + (is_32bits + 1) + banks); | |
289 | } | |
290 | ||
291 | void __init bcm63xx_cpu_init(void) | |
292 | { | |
293 | unsigned int tmp, expected_cpu_id; | |
294 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
2b5b9b78 | 295 | unsigned int cpu = smp_processor_id(); |
e7300d04 MB |
296 | |
297 | /* soc registers location depends on cpu type */ | |
298 | expected_cpu_id = 0; | |
299 | ||
300 | switch (c->cputype) { | |
602977b0 KC |
301 | case CPU_BMIPS3300: |
302 | if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) { | |
303 | expected_cpu_id = BCM6348_CPU_ID; | |
304 | bcm63xx_regs_base = bcm96348_regs_base; | |
305 | bcm63xx_irqs = bcm96348_irqs; | |
306 | } else { | |
307 | __cpu_name[cpu] = "Broadcom BCM6338"; | |
308 | expected_cpu_id = BCM6338_CPU_ID; | |
309 | bcm63xx_regs_base = bcm96338_regs_base; | |
310 | bcm63xx_irqs = bcm96338_irqs; | |
311 | } | |
e7300d04 | 312 | break; |
602977b0 | 313 | case CPU_BMIPS32: |
e7300d04 MB |
314 | expected_cpu_id = BCM6345_CPU_ID; |
315 | bcm63xx_regs_base = bcm96345_regs_base; | |
316 | bcm63xx_irqs = bcm96345_irqs; | |
317 | break; | |
602977b0 | 318 | case CPU_BMIPS4350: |
e7300d04 MB |
319 | expected_cpu_id = BCM6358_CPU_ID; |
320 | bcm63xx_regs_base = bcm96358_regs_base; | |
321 | bcm63xx_irqs = bcm96358_irqs; | |
322 | break; | |
323 | } | |
324 | ||
325 | /* | |
326 | * really early to panic, but delaying panic would not help since we | |
327 | * will never get any working console | |
328 | */ | |
329 | if (!expected_cpu_id) | |
330 | panic("unsupported Broadcom CPU"); | |
331 | ||
332 | /* | |
333 | * bcm63xx_regs_base is set, we can access soc registers | |
334 | */ | |
335 | ||
336 | /* double check CPU type */ | |
337 | tmp = bcm_perf_readl(PERF_REV_REG); | |
338 | bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; | |
339 | bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; | |
340 | ||
341 | if (bcm63xx_cpu_id != expected_cpu_id) | |
342 | panic("bcm63xx CPU id mismatch"); | |
343 | ||
344 | bcm63xx_cpu_freq = detect_cpu_clock(); | |
345 | bcm63xx_memory_size = detect_memory_size(); | |
346 | ||
347 | printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n", | |
348 | bcm63xx_cpu_id, bcm63xx_cpu_rev); | |
349 | printk(KERN_INFO "CPU frequency is %u MHz\n", | |
350 | bcm63xx_cpu_freq / 1000000); | |
351 | printk(KERN_INFO "%uMB of RAM installed\n", | |
352 | bcm63xx_memory_size >> 20); | |
353 | } |