[linux-block.git] / arch / mips / bcm47xx / setup.c

/*
 *  Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
 *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
 *  Copyright (C) 2006 Michael Buesch <m@bues.ch>
 *  Copyright (C) 2010 Waldemar Brodkorb <wbx@openadk.org>
 *  Copyright (C) 2010-2012 Hauke Mehrtens <hauke@hauke-m.de>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include "bcm47xx_private.h"

#include <linux/bcm47xx_sprom.h>
#include <linux/export.h>
#include <linux/types.h>
#include <linux/ethtool.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <linux/ssb/ssb.h>
#include <linux/ssb/ssb_embedded.h>
#include <linux/bcma/bcma_soc.h>
#include <asm/bmips.h>
#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/prom.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <bcm47xx.h>
#include <bcm47xx_board.h>

/*
 * CBR addr doesn't change and we can cache it.
 * For broken SoC/Bootloader CBR addr might also be provided via DT
 * with "brcm,bmips-cbr-reg" in the "cpus" node.
 */
void __iomem *bmips_cbr_addr __read_mostly;

union bcm47xx_bus bcm47xx_bus;
EXPORT_SYMBOL(bcm47xx_bus);

enum bcm47xx_bus_type bcm47xx_bus_type;
EXPORT_SYMBOL(bcm47xx_bus_type);

static void bcm47xx_machine_restart(char *command)
{
	pr_alert("Please stand by while rebooting the system...\n");
	local_irq_disable();
	/* Set the watchdog timer to reset immediately */
	switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
	case BCM47XX_BUS_TYPE_SSB:
		if (bcm47xx_bus.ssb.chip_id == 0x4785)
			write_c0_diag4(1 << 22);
		ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
		if (bcm47xx_bus.ssb.chip_id == 0x4785) {
			__asm__ __volatile__(
				".set\tmips3\n\t"
				"sync\n\t"
				"wait\n\t"
				".set\tmips0");
		}
		break;
#endif
#ifdef CONFIG_BCM47XX_BCMA
	case BCM47XX_BUS_TYPE_BCMA:
		bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 1);
		break;
#endif
	}
	while (1)
		cpu_relax();
}

static void bcm47xx_machine_halt(void)
{
	/* Disable interrupts and watchdog and spin forever */
	local_irq_disable();
	switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
	case BCM47XX_BUS_TYPE_SSB:
		ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
		break;
#endif
#ifdef CONFIG_BCM47XX_BCMA
	case BCM47XX_BUS_TYPE_BCMA:
		bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 0);
		break;
#endif
	}
	while (1)
		cpu_relax();
}

#ifdef CONFIG_BCM47XX_SSB
static void __init bcm47xx_register_ssb(void)
{
	int err;
	char buf[100];
	struct ssb_mipscore *mcore;

	err = ssb_bus_host_soc_register(&bcm47xx_bus.ssb, SSB_ENUM_BASE);
	if (err)
		panic("Failed to initialize SSB bus (err %d)", err);

	mcore = &bcm47xx_bus.ssb.mipscore;
	if (bcm47xx_nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
		if (strstr(buf, "console=ttyS1")) {
			struct ssb_serial_port port;

			pr_debug("Swapping serial ports!\n");
			/* swap serial ports */
			memcpy(&port, &mcore->serial_ports[0], sizeof(port));
			memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1],
			       sizeof(port));
			memcpy(&mcore->serial_ports[1], &port, sizeof(port));
		}
	}
}
#endif

#ifdef CONFIG_BCM47XX_BCMA
static void __init bcm47xx_register_bcma(void)
{
	int err;

	err = bcma_host_soc_register(&bcm47xx_bus.bcma);
	if (err)
		panic("Failed to register BCMA bus (err %d)", err);
}
#endif

/*
 * Memory setup is done in the early part of MIPS's arch_mem_init. It's supposed
 * to detect memory and record it with memblock_add.
 * Any extra initializaion performed here must not use kmalloc or bootmem.
 */
void __init plat_mem_setup(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	if (c->cputype == CPU_74K) {
		pr_info("Using bcma bus\n");
#ifdef CONFIG_BCM47XX_BCMA
		bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
		bcm47xx_register_bcma();
		bcm47xx_set_system_type(bcm47xx_bus.bcma.bus.chipinfo.id);
#ifdef CONFIG_HIGHMEM
		bcm47xx_prom_highmem_init();
#endif
#endif
	} else {
		pr_info("Using ssb bus\n");
#ifdef CONFIG_BCM47XX_SSB
		bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
		bcm47xx_sprom_register_fallbacks();
		bcm47xx_register_ssb();
		bcm47xx_set_system_type(bcm47xx_bus.ssb.chip_id);
#endif
	}

	_machine_restart = bcm47xx_machine_restart;
	_machine_halt = bcm47xx_machine_halt;
	pm_power_off = bcm47xx_machine_halt;
}

#ifdef CONFIG_BCM47XX_BCMA
static struct device * __init bcm47xx_setup_device(void)
{
	struct device *dev;
	int err;

	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
	if (!dev)
		return NULL;

	err = dev_set_name(dev, "bcm47xx_soc");
	if (err) {
		pr_err("Failed to set SoC device name: %d\n", err);
		kfree(dev);
		return NULL;
	}

	err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
	if (err)
		pr_err("Failed to set SoC DMA mask: %d\n", err);

	return dev;
}
#endif

/*
 * This finishes bus initialization doing things that were not possible without
 * kmalloc. Make sure to call it late enough (after mm_init).
 */
void __init bcm47xx_bus_setup(void)
{
#ifdef CONFIG_BCM47XX_BCMA
	if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) {
		int err;

		bcm47xx_bus.bcma.dev = bcm47xx_setup_device();
		if (!bcm47xx_bus.bcma.dev)
			panic("Failed to setup SoC device\n");

		err = bcma_host_soc_init(&bcm47xx_bus.bcma);
		if (err)
			panic("Failed to initialize BCMA bus (err %d)", err);
	}
#endif

	/* With bus initialized we can access NVRAM and detect the board */
	bcm47xx_board_detect();
	mips_set_machine_name(bcm47xx_board_get_name());
}

static int __init bcm47xx_cpu_fixes(void)
{
	switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
	case BCM47XX_BUS_TYPE_SSB:
		/* Nothing to do */
		break;
#endif
#ifdef CONFIG_BCM47XX_BCMA
	case BCM47XX_BUS_TYPE_BCMA:
		/* The BCM4706 has a problem with the CPU wait instruction.
		 * When r4k_wait or r4k_wait_irqoff is used will just hang and
		 * not return from a msleep(). Removing the cpu_wait
		 * functionality is a workaround for this problem. The BCM4716
		 * does not have this problem.
		 */
		if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
			cpu_wait = NULL;
		break;
#endif
	}
	return 0;
}
arch_initcall(bcm47xx_cpu_fixes);

static struct fixed_phy_status bcm47xx_fixed_phy_status __initdata = {
	.link	= 1,
	.speed	= SPEED_100,
	.duplex	= DUPLEX_FULL,
};

static int __init bcm47xx_register_bus_complete(void)
{
	switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
	case BCM47XX_BUS_TYPE_SSB:
		/* Nothing to do */
		break;
#endif
#ifdef CONFIG_BCM47XX_BCMA
	case BCM47XX_BUS_TYPE_BCMA:
		if (device_register(bcm47xx_bus.bcma.dev))
			pr_err("Failed to register SoC device\n");
		bcma_bus_register(&bcm47xx_bus.bcma.bus);
		break;
#endif
	}
	bcm47xx_buttons_register();
	bcm47xx_leds_register();
	bcm47xx_workarounds();

	fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
	return 0;
}
device_initcall(bcm47xx_register_bus_complete);
Commit	Line	Data
1c0c13eb AJ	1	/*
1c0c13eb AJ	2	* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
1c0c13eb	3	* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
eb032b98	4	* Copyright (C) 2006 Michael Buesch <m@bues.ch>
121915c4	5	* Copyright (C) 2010 Waldemar Brodkorb <wbx@openadk.org>
f384b3dd	6	* Copyright (C) 2010-2012 Hauke Mehrtens <hauke@hauke-m.de>
1c0c13eb AJ	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	14	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	15	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	16	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	17	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	18	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	19	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	20	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	21	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	22	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	23	*
	24	* You should have received a copy of the GNU General Public License along
	25	* with this program; if not, write to the Free Software Foundation, Inc.,
	26	* 675 Mass Ave, Cambridge, MA 02139, USA.
	27	*/
	28
515fa75d RM	29	#include "bcm47xx_private.h"
515fa75d RM	30
2ab71a02	31	#include <linux/bcm47xx_sprom.h>
cae39d13	32	#include <linux/export.h>
1c0c13eb	33	#include <linux/types.h>
b04138b3 HM	34	#include <linux/ethtool.h>
	35	#include <linux/phy.h>
	36	#include <linux/phy_fixed.h>
1c0c13eb	37	#include <linux/ssb/ssb.h>
b06f3e19	38	#include <linux/ssb/ssb_embedded.h>
c1d1c5d4	39	#include <linux/bcma/bcma_soc.h>
a5c05453	40	#include <asm/bmips.h>
25e5fb97	41	#include <asm/bootinfo.h>
76b573e4	42	#include <asm/idle.h>
7da4b6f8	43	#include <asm/prom.h>
1c0c13eb AJ	44	#include <asm/reboot.h>
	45	#include <asm/time.h>
	46	#include <bcm47xx.h>
786c497a	47	#include <bcm47xx_board.h>
1c0c13eb	48
b95b30e5 CM	49	/*
	50	* CBR addr doesn't change and we can cache it.
	51	* For broken SoC/Bootloader CBR addr might also be provided via DT
	52	* with "brcm,bmips-cbr-reg" in the "cpus" node.
	53	*/
a5c05453 CM	54	void __iomem *bmips_cbr_addr __read_mostly;
a5c05453 CM	55
08ccf572 HM	56	union bcm47xx_bus bcm47xx_bus;
	57	EXPORT_SYMBOL(bcm47xx_bus);
	58
	59	enum bcm47xx_bus_type bcm47xx_bus_type;
	60	EXPORT_SYMBOL(bcm47xx_bus_type);
1c0c13eb AJ	61
	62	static void bcm47xx_machine_restart(char *command)
	63	{
d548ca6b	64	pr_alert("Please stand by while rebooting the system...\n");
1c0c13eb AJ	65	local_irq_disable();
1c0c13eb AJ	66	/* Set the watchdog timer to reset immediately */
08ccf572	67	switch (bcm47xx_bus_type) {
a656ffcb	68	#ifdef CONFIG_BCM47XX_SSB
08ccf572	69	case BCM47XX_BUS_TYPE_SSB:
2727cab2 HM	70	if (bcm47xx_bus.ssb.chip_id == 0x4785)
	71	write_c0_diag4(1 << 22);
	72	ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
	73	if (bcm47xx_bus.ssb.chip_id == 0x4785) {
	74	__asm__ __volatile__(
	75	".set\tmips3\n\t"
	76	"sync\n\t"
	77	"wait\n\t"
	78	".set\tmips0");
	79	}
08ccf572	80	break;
c1d1c5d4 HM	81	#endif
	82	#ifdef CONFIG_BCM47XX_BCMA
	83	case BCM47XX_BUS_TYPE_BCMA:
2727cab2	84	bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 1);
c1d1c5d4	85	break;
a656ffcb	86	#endif
08ccf572	87	}
1c0c13eb AJ	88	while (1)
	89	cpu_relax();
	90	}
	91
	92	static void bcm47xx_machine_halt(void)
	93	{
	94	/* Disable interrupts and watchdog and spin forever */
	95	local_irq_disable();
08ccf572	96	switch (bcm47xx_bus_type) {
a656ffcb	97	#ifdef CONFIG_BCM47XX_SSB
08ccf572 HM	98	case BCM47XX_BUS_TYPE_SSB:
	99	ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
	100	break;
c1d1c5d4 HM	101	#endif
	102	#ifdef CONFIG_BCM47XX_BCMA
	103	case BCM47XX_BUS_TYPE_BCMA:
	104	bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 0);
	105	break;
a656ffcb	106	#endif
08ccf572	107	}
1c0c13eb AJ	108	while (1)
	109	cpu_relax();
	110	}
	111
a656ffcb	112	#ifdef CONFIG_BCM47XX_SSB
08ccf572	113	static void __init bcm47xx_register_ssb(void)
1c0c13eb AJ	114	{
1c0c13eb AJ	115	int err;
1690a7f9 HM	116	char buf[100];
1690a7f9 HM	117	struct ssb_mipscore *mcore;
1c0c13eb	118
541c9a84	119	err = ssb_bus_host_soc_register(&bcm47xx_bus.ssb, SSB_ENUM_BASE);
1c0c13eb	120	if (err)
ab75dc02	121	panic("Failed to initialize SSB bus (err %d)", err);
1c0c13eb	122
08ccf572	123	mcore = &bcm47xx_bus.ssb.mipscore;
111bd981	124	if (bcm47xx_nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
1690a7f9 HM	125	if (strstr(buf, "console=ttyS1")) {
	126	struct ssb_serial_port port;
	127
d548ca6b	128	pr_debug("Swapping serial ports!\n");
1690a7f9 HM	129	/* swap serial ports */
	130	memcpy(&port, &mcore->serial_ports[0], sizeof(port));
	131	memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1],
	132	sizeof(port));
	133	memcpy(&mcore->serial_ports[1], &port, sizeof(port));
	134	}
	135	}
08ccf572	136	}
a656ffcb	137	#endif
08ccf572	138
c1d1c5d4 HM	139	#ifdef CONFIG_BCM47XX_BCMA
	140	static void __init bcm47xx_register_bcma(void)
	141	{
	142	int err;
	143
	144	err = bcma_host_soc_register(&bcm47xx_bus.bcma);
a395135d RM	145	if (err)
a395135d RM	146	panic("Failed to register BCMA bus (err %d)", err);
c1d1c5d4 HM	147	}
	148	#endif
	149
e5810fa0 RM	150	/*
e5810fa0 RM	151	* Memory setup is done in the early part of MIPS's arch_mem_init. It's supposed
e7ae8d17	152	* to detect memory and record it with memblock_add.
e5810fa0 RM	153	* Any extra initializaion performed here must not use kmalloc or bootmem.
e5810fa0 RM	154	*/
08ccf572 HM	155	void __init plat_mem_setup(void)
	156	{
	157	struct cpuinfo_mips *c = &current_cpu_data;
	158
be090fa6	159	if (c->cputype == CPU_74K) {
d548ca6b	160	pr_info("Using bcma bus\n");
c1d1c5d4 HM	161	#ifdef CONFIG_BCM47XX_BCMA
	162	bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
	163	bcm47xx_register_bcma();
dd573285	164	bcm47xx_set_system_type(bcm47xx_bus.bcma.bus.chipinfo.id);
6ee1d934 RM	165	#ifdef CONFIG_HIGHMEM
	166	bcm47xx_prom_highmem_init();
	167	#endif
c1d1c5d4 HM	168	#endif
c1d1c5d4 HM	169	} else {
d548ca6b	170	pr_info("Using ssb bus\n");
a656ffcb	171	#ifdef CONFIG_BCM47XX_SSB
c1d1c5d4	172	bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
a59da8fb	173	bcm47xx_sprom_register_fallbacks();
c1d1c5d4	174	bcm47xx_register_ssb();
dd573285	175	bcm47xx_set_system_type(bcm47xx_bus.ssb.chip_id);
a656ffcb	176	#endif
c1d1c5d4	177	}
1690a7f9	178
1c0c13eb AJ	179	_machine_restart = bcm47xx_machine_restart;
	180	_machine_halt = bcm47xx_machine_halt;
	181	pm_power_off = bcm47xx_machine_halt;
e5810fa0 RM	182	}
e5810fa0 RM	183
321c46b9 RM	184	#ifdef CONFIG_BCM47XX_BCMA
	185	static struct device * __init bcm47xx_setup_device(void)
	186	{
	187	struct device *dev;
	188	int err;
	189
	190	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
	191	if (!dev)
	192	return NULL;
	193
	194	err = dev_set_name(dev, "bcm47xx_soc");
	195	if (err) {
	196	pr_err("Failed to set SoC device name: %d\n", err);
	197	kfree(dev);
	198	return NULL;
	199	}
	200
	201	err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
	202	if (err)
	203	pr_err("Failed to set SoC DMA mask: %d\n", err);
	204
	205	return dev;
	206	}
	207	#endif
	208
e5810fa0 RM	209	/*
	210	* This finishes bus initialization doing things that were not possible without
	211	* kmalloc. Make sure to call it late enough (after mm_init).
	212	*/
	213	void __init bcm47xx_bus_setup(void)
	214	{
	215	#ifdef CONFIG_BCM47XX_BCMA
	216	if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) {
	217	int err;
	218
321c46b9 RM	219	bcm47xx_bus.bcma.dev = bcm47xx_setup_device();
	220	if (!bcm47xx_bus.bcma.dev)
	221	panic("Failed to setup SoC device\n");
	222
e5810fa0 RM	223	err = bcma_host_soc_init(&bcm47xx_bus.bcma);
	224	if (err)
	225	panic("Failed to initialize BCMA bus (err %d)", err);
e5810fa0 RM	226	}
	227	#endif
	228
	229	/* With bus initialized we can access NVRAM and detect the board */
786c497a	230	bcm47xx_board_detect();
7da4b6f8	231	mips_set_machine_name(bcm47xx_board_get_name());
1c0c13eb	232	}
c1d1c5d4	233
3c06b12b HM	234	static int __init bcm47xx_cpu_fixes(void)
	235	{
	236	switch (bcm47xx_bus_type) {
	237	#ifdef CONFIG_BCM47XX_SSB
	238	case BCM47XX_BUS_TYPE_SSB:
	239	/* Nothing to do */
	240	break;
	241	#endif
	242	#ifdef CONFIG_BCM47XX_BCMA
	243	case BCM47XX_BUS_TYPE_BCMA:
	244	/* The BCM4706 has a problem with the CPU wait instruction.
	245	* When r4k_wait or r4k_wait_irqoff is used will just hang and
	246	* not return from a msleep(). Removing the cpu_wait
	247	* functionality is a workaround for this problem. The BCM4716
	248	* does not have this problem.
	249	*/
	250	if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
	251	cpu_wait = NULL;
	252	break;
	253	#endif
	254	}
	255	return 0;
	256	}
	257	arch_initcall(bcm47xx_cpu_fixes);
	258
b04138b3 HM	259	static struct fixed_phy_status bcm47xx_fixed_phy_status __initdata = {
	260	.link = 1,
	261	.speed = SPEED_100,
	262	.duplex = DUPLEX_FULL,
	263	};
	264
c1d1c5d4 HM	265	static int __init bcm47xx_register_bus_complete(void)
	266	{
	267	switch (bcm47xx_bus_type) {
	268	#ifdef CONFIG_BCM47XX_SSB
	269	case BCM47XX_BUS_TYPE_SSB:
	270	/* Nothing to do */
	271	break;
	272	#endif
	273	#ifdef CONFIG_BCM47XX_BCMA
	274	case BCM47XX_BUS_TYPE_BCMA:
321c46b9 RM	275	if (device_register(bcm47xx_bus.bcma.dev))
321c46b9 RM	276	pr_err("Failed to register SoC device\n");
c1d1c5d4 HM	277	bcma_bus_register(&bcm47xx_bus.bcma.bus);
	278	break;
	279	#endif
	280	}
ef1e3e7a	281	bcm47xx_buttons_register();
515fa75d	282	bcm47xx_leds_register();
a2bec078	283	bcm47xx_workarounds();
515fa75d	284
5468e82f	285	fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
c1d1c5d4 HM	286	return 0;
	287	}
	288	device_initcall(bcm47xx_register_bus_complete);