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1da177e4 LT |
1 | /* |
2 | * Copyright 2000 MontaVista Software Inc. | |
3 | * Author: MontaVista Software, Inc. | |
4 | * ppopov@mvista.com or source@mvista.com | |
5 | * | |
6 | * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
27 | */ | |
28 | #include <linux/config.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/ioport.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/interrupt.h> | |
efe29c0f | 35 | #include <linux/module.h> |
fcdb27ad | 36 | #include <linux/pm.h> |
1da177e4 LT |
37 | |
38 | #include <asm/cpu.h> | |
39 | #include <asm/bootinfo.h> | |
40 | #include <asm/irq.h> | |
41 | #include <asm/mipsregs.h> | |
42 | #include <asm/reboot.h> | |
43 | #include <asm/pgtable.h> | |
44 | #include <asm/mach-au1x00/au1000.h> | |
45 | #include <asm/time.h> | |
46 | ||
47 | extern char * __init prom_getcmdline(void); | |
48 | extern void __init board_setup(void); | |
49 | extern void au1000_restart(char *); | |
50 | extern void au1000_halt(void); | |
51 | extern void au1000_power_off(void); | |
1da177e4 | 52 | extern void au1x_time_init(void); |
1da177e4 LT |
53 | extern void au1x_timer_setup(struct irqaction *irq); |
54 | extern void au1xxx_time_init(void); | |
55 | extern void au1xxx_timer_setup(struct irqaction *irq); | |
56 | extern void set_cpuspec(void); | |
57 | ||
2925aba4 | 58 | void __init plat_mem_setup(void) |
1da177e4 LT |
59 | { |
60 | struct cpu_spec *sp; | |
61 | char *argptr; | |
62 | unsigned long prid, cpupll, bclk = 1; | |
63 | ||
64 | set_cpuspec(); | |
65 | sp = cur_cpu_spec[0]; | |
66 | ||
67 | board_setup(); /* board specific setup */ | |
68 | ||
69 | prid = read_c0_prid(); | |
70 | cpupll = (au_readl(0xB1900060) & 0x3F) * 12; | |
71 | printk("(PRId %08lx) @ %ldMHZ\n", prid, cpupll); | |
72 | ||
73 | bclk = sp->cpu_bclk; | |
74 | if (bclk) | |
75 | { | |
76 | /* Enable BCLK switching */ | |
77 | bclk = au_readl(0xB190003C); | |
78 | au_writel(bclk | 0x60, 0xB190003C); | |
79 | printk("BCLK switching enabled!\n"); | |
80 | } | |
81 | ||
82 | if (sp->cpu_od) { | |
83 | /* Various early Au1000 Errata corrected by this */ | |
84 | set_c0_config(1<<19); /* Set Config[OD] */ | |
85 | } | |
86 | else { | |
87 | /* Clear to obtain best system bus performance */ | |
88 | clear_c0_config(1<<19); /* Clear Config[OD] */ | |
a3dddd56 | 89 | } |
1da177e4 LT |
90 | |
91 | argptr = prom_getcmdline(); | |
92 | ||
335bd9df | 93 | #ifdef CONFIG_SERIAL_8250_CONSOLE |
1da177e4 LT |
94 | if ((argptr = strstr(argptr, "console=")) == NULL) { |
95 | argptr = prom_getcmdline(); | |
96 | strcat(argptr, " console=ttyS0,115200"); | |
97 | } | |
42a3b4f2 | 98 | #endif |
1da177e4 LT |
99 | |
100 | #ifdef CONFIG_FB_AU1100 | |
101 | if ((argptr = strstr(argptr, "video=")) == NULL) { | |
102 | argptr = prom_getcmdline(); | |
103 | /* default panel */ | |
104 | /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ | |
105 | #ifdef CONFIG_MIPS_HYDROGEN3 | |
106 | strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor"); | |
1da177e4 LT |
107 | #endif |
108 | } | |
109 | #endif | |
1da177e4 LT |
110 | |
111 | #ifdef CONFIG_FB_XPERT98 | |
112 | if ((argptr = strstr(argptr, "video=")) == NULL) { | |
113 | argptr = prom_getcmdline(); | |
114 | strcat(argptr, " video=atyfb:1024x768-8@70"); | |
115 | } | |
116 | #endif | |
117 | ||
118 | #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) | |
119 | /* au1000 does not support vra, au1500 and au1100 do */ | |
120 | strcat(argptr, " au1000_audio=vra"); | |
121 | argptr = prom_getcmdline(); | |
122 | #endif | |
123 | _machine_restart = au1000_restart; | |
124 | _machine_halt = au1000_halt; | |
fcdb27ad | 125 | pm_power_off = au1000_power_off; |
1da177e4 LT |
126 | board_time_init = au1xxx_time_init; |
127 | board_timer_setup = au1xxx_timer_setup; | |
128 | ||
129 | /* IO/MEM resources. */ | |
130 | set_io_port_base(0); | |
131 | ioport_resource.start = IOPORT_RESOURCE_START; | |
132 | ioport_resource.end = IOPORT_RESOURCE_END; | |
133 | iomem_resource.start = IOMEM_RESOURCE_START; | |
134 | iomem_resource.end = IOMEM_RESOURCE_END; | |
135 | ||
136 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S); | |
137 | au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL); | |
138 | au_sync(); | |
139 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); | |
140 | au_writel(0, SYS_TOYTRIM); | |
1da177e4 LT |
141 | } |
142 | ||
1da177e4 LT |
143 | #if defined(CONFIG_64BIT_PHYS_ADDR) |
144 | /* This routine should be valid for all Au1x based boards */ | |
c3455b0e | 145 | phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) |
1da177e4 LT |
146 | { |
147 | u32 start, end; | |
148 | ||
149 | /* Don't fixup 36 bit addresses */ | |
150 | if ((phys_addr >> 32) != 0) return phys_addr; | |
151 | ||
152 | #ifdef CONFIG_PCI | |
153 | start = (u32)Au1500_PCI_MEM_START; | |
154 | end = (u32)Au1500_PCI_MEM_END; | |
155 | /* check for pci memory window */ | |
156 | if ((phys_addr >= start) && ((phys_addr + size) < end)) { | |
157 | return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START); | |
158 | } | |
159 | #endif | |
160 | ||
161 | /* All Au1x SOCs have a pcmcia controller */ | |
162 | /* We setup our 32 bit pseudo addresses to be equal to the | |
163 | * 36 bit addr >> 4, to make it easier to check the address | |
164 | * and fix it. | |
165 | * The Au1x socket 0 phys attribute address is 0xF 4000 0000. | |
166 | * The pseudo address we use is 0xF400 0000. Any address over | |
167 | * 0xF400 0000 is a pcmcia pseudo address. | |
168 | */ | |
169 | if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) { | |
170 | return (phys_t)(phys_addr << 4); | |
171 | } | |
172 | ||
173 | /* default nop */ | |
174 | return phys_addr; | |
175 | } | |
efe29c0f | 176 | EXPORT_SYMBOL(__fixup_bigphys_addr); |
1da177e4 | 177 | #endif |