[linux-block.git] / arch / mips / ath79 / early_printk.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *  Atheros AR7XXX/AR9XXX SoC early printk support
 *
 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 */

#include <linux/io.h>
#include <linux/errno.h>
#include <linux/serial_reg.h>
#include <asm/addrspace.h>
#include <asm/setup.h>

#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ar933x_uart.h>

static void (*_prom_putchar)(char);

static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
{
	u32 t;

	do {
		t = __raw_readl(reg);
		if ((t & mask) == val)
			break;
	} while (1);
}

#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)

static void prom_putchar_ar71xx(char ch)
{
	void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));

	prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
	__raw_writel((unsigned char)ch, base + UART_TX * 4);
	prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
}

static void prom_putchar_ar933x(char ch)
{
	void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));

	prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
			  AR933X_UART_DATA_TX_CSR);
	__raw_writel(AR933X_UART_DATA_TX_CSR | (unsigned char)ch,
		     base + AR933X_UART_DATA_REG);
	prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
			  AR933X_UART_DATA_TX_CSR);
}

static void prom_putchar_dummy(char ch)
{
	/* nothing to do */
}

static void prom_enable_uart(u32 id)
{
	void __iomem *gpio_base;
	u32 uart_en;
	u32 t;

	switch (id) {
	case REV_ID_MAJOR_AR71XX:
		uart_en = AR71XX_GPIO_FUNC_UART_EN;
		break;

	case REV_ID_MAJOR_AR7240:
	case REV_ID_MAJOR_AR7241:
	case REV_ID_MAJOR_AR7242:
		uart_en = AR724X_GPIO_FUNC_UART_EN;
		break;

	case REV_ID_MAJOR_AR913X:
		uart_en = AR913X_GPIO_FUNC_UART_EN;
		break;

	case REV_ID_MAJOR_AR9330:
	case REV_ID_MAJOR_AR9331:
		uart_en = AR933X_GPIO_FUNC_UART_EN;
		break;

	case REV_ID_MAJOR_AR9341:
	case REV_ID_MAJOR_AR9342:
	case REV_ID_MAJOR_AR9344:
		/* TODO */
	default:
		return;
	}

	gpio_base = (void __iomem *)KSEG1ADDR(AR71XX_GPIO_BASE);
	t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
	t |= uart_en;
	__raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
}

static void prom_putchar_init(void)
{
	void __iomem *base;
	u32 id;

	base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
	id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
	id &= REV_ID_MAJOR_MASK;

	switch (id) {
	case REV_ID_MAJOR_AR71XX:
	case REV_ID_MAJOR_AR7240:
	case REV_ID_MAJOR_AR7241:
	case REV_ID_MAJOR_AR7242:
	case REV_ID_MAJOR_AR913X:
	case REV_ID_MAJOR_AR9341:
	case REV_ID_MAJOR_AR9342:
	case REV_ID_MAJOR_AR9344:
	case REV_ID_MAJOR_QCA9533:
	case REV_ID_MAJOR_QCA9533_V2:
	case REV_ID_MAJOR_QCA9556:
	case REV_ID_MAJOR_QCA9558:
	case REV_ID_MAJOR_TP9343:
	case REV_ID_MAJOR_QCA956X:
		_prom_putchar = prom_putchar_ar71xx;
		break;

	case REV_ID_MAJOR_AR9330:
	case REV_ID_MAJOR_AR9331:
		_prom_putchar = prom_putchar_ar933x;
		break;

	default:
		_prom_putchar = prom_putchar_dummy;
		return;
	}

	prom_enable_uart(id);
}

void prom_putchar(char ch)
{
	if (!_prom_putchar)
		prom_putchar_init();

	_prom_putchar(ch);
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
d4a67d9d	2	/*
0bd3acdf	3	* Atheros AR7XXX/AR9XXX SoC early printk support
d4a67d9d	4	*
0bd3acdf	5	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
d4a67d9d	6	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
d4a67d9d GJ	7	*/
	8
	9	#include <linux/io.h>
0bd3acdf	10	#include <linux/errno.h>
d4a67d9d GJ	11	#include <linux/serial_reg.h>
d4a67d9d GJ	12	#include <asm/addrspace.h>
5c93316c	13	#include <asm/setup.h>
d4a67d9d	14
0bd3acdf	15	#include <asm/mach-ath79/ath79.h>
d4a67d9d	16	#include <asm/mach-ath79/ar71xx_regs.h>
0bd3acdf	17	#include <asm/mach-ath79/ar933x_uart.h>
d4a67d9d	18
5c93316c	19	static void (*_prom_putchar)(char);
0bd3acdf GJ	20
0bd3acdf GJ	21	static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
d4a67d9d	22	{
0bd3acdf	23	u32 t;
d4a67d9d GJ	24
d4a67d9d GJ	25	do {
0bd3acdf GJ	26	t = __raw_readl(reg);
0bd3acdf GJ	27	if ((t & mask) == val)
d4a67d9d GJ	28	break;
	29	} while (1);
	30	}
	31
f5b556c9 MS	32	#define BOTH_EMPTY (UART_LSR_TEMT \| UART_LSR_THRE)
f5b556c9 MS	33
5c93316c	34	static void prom_putchar_ar71xx(char ch)
d4a67d9d GJ	35	{
	36	void __iomem base = (void __iomem )(KSEG1ADDR(AR71XX_UART_BASE));
	37
f5b556c9	38	prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
5c93316c	39	__raw_writel((unsigned char)ch, base + UART_TX * 4);
f5b556c9	40	prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
0bd3acdf GJ	41	}
0bd3acdf GJ	42
5c93316c	43	static void prom_putchar_ar933x(char ch)
0bd3acdf GJ	44	{
	45	void __iomem base = (void __iomem )(KSEG1ADDR(AR933X_UART_BASE));
	46
	47	prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
	48	AR933X_UART_DATA_TX_CSR);
5c93316c AS	49	__raw_writel(AR933X_UART_DATA_TX_CSR \| (unsigned char)ch,
5c93316c AS	50	base + AR933X_UART_DATA_REG);
0bd3acdf GJ	51	prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
	52	AR933X_UART_DATA_TX_CSR);
	53	}
	54
5c93316c	55	static void prom_putchar_dummy(char ch)
0bd3acdf GJ	56	{
	57	/* nothing to do */
	58	}
	59
ffc20581 GJ	60	static void prom_enable_uart(u32 id)
	61	{
	62	void __iomem *gpio_base;
	63	u32 uart_en;
	64	u32 t;
	65
	66	switch (id) {
	67	case REV_ID_MAJOR_AR71XX:
	68	uart_en = AR71XX_GPIO_FUNC_UART_EN;
	69	break;
	70
	71	case REV_ID_MAJOR_AR7240:
	72	case REV_ID_MAJOR_AR7241:
	73	case REV_ID_MAJOR_AR7242:
	74	uart_en = AR724X_GPIO_FUNC_UART_EN;
	75	break;
	76
	77	case REV_ID_MAJOR_AR913X:
	78	uart_en = AR913X_GPIO_FUNC_UART_EN;
	79	break;
	80
	81	case REV_ID_MAJOR_AR9330:
	82	case REV_ID_MAJOR_AR9331:
	83	uart_en = AR933X_GPIO_FUNC_UART_EN;
	84	break;
	85
	86	case REV_ID_MAJOR_AR9341:
	87	case REV_ID_MAJOR_AR9342:
	88	case REV_ID_MAJOR_AR9344:
	89	/* TODO */
	90	default:
	91	return;
	92	}
	93
	94	gpio_base = (void __iomem *)KSEG1ADDR(AR71XX_GPIO_BASE);
	95	t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
	96	t \|= uart_en;
	97	__raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
	98	}
	99
0bd3acdf GJ	100	static void prom_putchar_init(void)
	101	{
	102	void __iomem *base;
	103	u32 id;
	104
	105	base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
	106	id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
	107	id &= REV_ID_MAJOR_MASK;
	108
	109	switch (id) {
	110	case REV_ID_MAJOR_AR71XX:
	111	case REV_ID_MAJOR_AR7240:
	112	case REV_ID_MAJOR_AR7241:
	113	case REV_ID_MAJOR_AR7242:
	114	case REV_ID_MAJOR_AR913X:
703327dd GJ	115	case REV_ID_MAJOR_AR9341:
	116	case REV_ID_MAJOR_AR9342:
	117	case REV_ID_MAJOR_AR9344:
af2d1b52 MS	118	case REV_ID_MAJOR_QCA9533:
af2d1b52 MS	119	case REV_ID_MAJOR_QCA9533_V2:
90898779 GJ	120	case REV_ID_MAJOR_QCA9556:
90898779 GJ	121	case REV_ID_MAJOR_QCA9558:
af2d1b52 MS	122	case REV_ID_MAJOR_TP9343:
af2d1b52 MS	123	case REV_ID_MAJOR_QCA956X:
0bd3acdf GJ	124	_prom_putchar = prom_putchar_ar71xx;
	125	break;
	126
	127	case REV_ID_MAJOR_AR9330:
	128	case REV_ID_MAJOR_AR9331:
	129	_prom_putchar = prom_putchar_ar933x;
	130	break;
	131
	132	default:
	133	_prom_putchar = prom_putchar_dummy;
ffc20581	134	return;
0bd3acdf	135	}
ffc20581 GJ	136
ffc20581 GJ	137	prom_enable_uart(id);
0bd3acdf GJ	138	}
0bd3acdf GJ	139
5c93316c	140	void prom_putchar(char ch)
0bd3acdf GJ	141	{
	142	if (!_prom_putchar)
	143	prom_putchar_init();
	144
	145	_prom_putchar(ch);
d4a67d9d	146	}