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MIPS: Alchemy: introduce helpers to access SYS register block.
[linux-block.git] / arch / mips / alchemy / devboards / db1200.c
CommitLineData
63323ec5 1/*
6f7c8623 2 * DBAu1200/PBAu1200 board platform device registration
63323ec5 3 *
7c4b24da 4 * Copyright (C) 2008-2011 Manuel Lauss
63323ec5
ML		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/gpio.h>
23#include <linux/i2c.h>
24#include <linux/init.h>
f9ded569 25#include <linux/module.h>
7c4b24da 26#include <linux/interrupt.h>
63323ec5
ML		 27#include <linux/io.h>
28#include <linux/leds.h>
29#include <linux/mmc/host.h>
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/partitions.h>
33#include <linux/platform_device.h>
34#include <linux/serial_8250.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h>
37#include <linux/smc91x.h>
54ff4a1d 38#include <linux/ata_platform.h>
7c4b24da 39#include <asm/mach-au1x00/au1000.h>
63323ec5
ML		 40#include <asm/mach-au1x00/au1100_mmc.h>
41#include <asm/mach-au1x00/au1xxx_dbdma.h>
a16afa53 42#include <asm/mach-au1x00/au1xxx_psc.h>
a9b71a8f 43#include <asm/mach-au1x00/au1200fb.h>
63323ec5
ML		 44#include <asm/mach-au1x00/au1550_spi.h>
45#include <asm/mach-db1x00/bcsr.h>
63323ec5 46
7c4b24da
ML		 47#include "platform.h"
48
a16afa53
ML		 49#define BCSR_INT_IDE 0x0001
50#define BCSR_INT_ETH 0x0002
51#define BCSR_INT_PC0 0x0004
52#define BCSR_INT_PC0STSCHG 0x0008
53#define BCSR_INT_PC1 0x0010
54#define BCSR_INT_PC1STSCHG 0x0020
55#define BCSR_INT_DC 0x0040
56#define BCSR_INT_FLASHBUSY 0x0080
57#define BCSR_INT_PC0INSERT 0x0100
58#define BCSR_INT_PC0EJECT 0x0200
59#define BCSR_INT_PC1INSERT 0x0400
60#define BCSR_INT_PC1EJECT 0x0800
61#define BCSR_INT_SD0INSERT 0x1000
62#define BCSR_INT_SD0EJECT 0x2000
63#define BCSR_INT_SD1INSERT 0x4000
64#define BCSR_INT_SD1EJECT 0x8000
65
66#define DB1200_IDE_PHYS_ADDR 0x18800000
67#define DB1200_IDE_REG_SHIFT 5
68#define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT)
69#define DB1200_ETH_PHYS_ADDR 0x19000300
70#define DB1200_NAND_PHYS_ADDR 0x20000000
71
72#define PB1200_IDE_PHYS_ADDR 0x0C800000
73#define PB1200_ETH_PHYS_ADDR 0x0D000300
74#define PB1200_NAND_PHYS_ADDR 0x1C000000
75
76#define DB1200_INT_BEGIN (AU1000_MAX_INTR + 1)
77#define DB1200_IDE_INT (DB1200_INT_BEGIN + 0)
78#define DB1200_ETH_INT (DB1200_INT_BEGIN + 1)
79#define DB1200_PC0_INT (DB1200_INT_BEGIN + 2)
80#define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3)
81#define DB1200_PC1_INT (DB1200_INT_BEGIN + 4)
82#define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5)
83#define DB1200_DC_INT (DB1200_INT_BEGIN + 6)
84#define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7)
85#define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8)
86#define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9)
87#define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10)
88#define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11)
89#define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12)
90#define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13)
91#define PB1200_SD1_INSERT_INT (DB1200_INT_BEGIN + 14)
92#define PB1200_SD1_EJECT_INT (DB1200_INT_BEGIN + 15)
93#define DB1200_INT_END (DB1200_INT_BEGIN + 15)
94
bd8510df 95const char *get_system_type(void);
7c4b24da 96
bd8510df 97static int __init db1200_detect_board(void)
6f7c8623
ML		 98{
99 int bid;
100
f2711be0
ML		 101 /* try the DB1200 first */
102 bcsr_init(DB1200_BCSR_PHYS_ADDR,
103 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
104 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
105 unsigned short t = bcsr_read(BCSR_HEXLEDS);
106 bcsr_write(BCSR_HEXLEDS, ~t);
107 if (bcsr_read(BCSR_HEXLEDS) != t) {
108 bcsr_write(BCSR_HEXLEDS, t);
109 return 0;
110 }
111 }
112
113 /* okay, try the PB1200 then */
6f7c8623
ML		 114 bcsr_init(PB1200_BCSR_PHYS_ADDR,
115 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
116 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
117 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
f2711be0
ML		 118 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
119 unsigned short t = bcsr_read(BCSR_HEXLEDS);
120 bcsr_write(BCSR_HEXLEDS, ~t);
121 if (bcsr_read(BCSR_HEXLEDS) != t) {
122 bcsr_write(BCSR_HEXLEDS, t);
123 return 0;
124 }
125 }
6f7c8623 126
f2711be0 127 return 1; /* it's neither */
7c4b24da
ML		 128}
129
bd8510df 130int __init db1200_board_setup(void)
7c4b24da
ML		 131{
132 unsigned long freq0, clksrc, div, pfc;
133 unsigned short whoami;
134
bd8510df
ML		 135 if (db1200_detect_board())
136 return -ENODEV;
7c4b24da
ML		 137
138 whoami = bcsr_read(BCSR_WHOAMI);
970e268d
ML		 139 switch (BCSR_WHOAMI_BOARD(whoami)) {
140 case BCSR_WHOAMI_PB1200_DDR1:
141 case BCSR_WHOAMI_PB1200_DDR2:
142 case BCSR_WHOAMI_DB1200:
143 break;
144 default:
145 return -ENODEV;
146 }
147
6f7c8623 148 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
70342287 149 " Board-ID %d Daughtercard ID %d\n", get_system_type(),
7c4b24da
ML		 150 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
151
152 /* SMBus/SPI on PSC0, Audio on PSC1 */
1d09de7d 153 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
7c4b24da
ML		 154 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
155 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
70342287 156 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
1d09de7d 157 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
7c4b24da
ML		 158
159 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
160 * CPU clock; all other clock generators off/unused.
161 */
162 div = (get_au1x00_speed() + 25000000) / 50000000;
163 if (div & 1)
164 div++;
165 div = ((div >> 1) - 1) & 0xff;
166
167 freq0 = div << SYS_FC_FRDIV0_BIT;
1d09de7d 168 alchemy_wrsys(freq0, AU1000_SYS_FREQCTRL0);
7c4b24da 169 freq0 |= SYS_FC_FE0; /* enable F0 */
1d09de7d 170 alchemy_wrsys(freq0, AU1000_SYS_FREQCTRL0);
7c4b24da
ML		 171
172 /* psc0_intclk comes 1:1 from F0 */
173 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
1d09de7d 174 alchemy_wrsys(clksrc, AU1000_SYS_CLKSRC);
bd8510df
ML		 175
176 return 0;
7c4b24da
ML		 177}
178
179/******************************************************************************/
63323ec5
ML		 180
181static struct mtd_partition db1200_spiflash_parts[] = {
182 {
6f7c8623 183 .name = "spi_flash",
70342287 184 .offset = 0,
63323ec5
ML		 185 .size = MTDPART_SIZ_FULL,
186 },
187};
188
189static struct flash_platform_data db1200_spiflash_data = {
190 .name = "s25fl001",
191 .parts = db1200_spiflash_parts,
192 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts),
193 .type = "m25p10",
194};
195
196static struct spi_board_info db1200_spi_devs[] __initdata = {
197 {
198 /* TI TMP121AIDBVR temp sensor */
199 .modalias = "tmp121",
200 .max_speed_hz = 2000000,
201 .bus_num = 0,
202 .chip_select = 0,
203 .mode = 0,
204 },
205 {
206 /* Spansion S25FL001D0FMA SPI flash */
207 .modalias = "m25p80",
208 .max_speed_hz = 50000000,
209 .bus_num = 0,
210 .chip_select = 1,
211 .mode = 0,
212 .platform_data = &db1200_spiflash_data,
213 },
214};
215
216static struct i2c_board_info db1200_i2c_devs[] __initdata = {
7c4b24da
ML		 217 { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */
218 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
219 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
63323ec5
ML		 220};
221
222/**********************************************************************/
223
224static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
225 unsigned int ctrl)
226{
227 struct nand_chip *this = mtd->priv;
228 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
229
230 ioaddr &= 0xffffff00;
231
232 if (ctrl & NAND_CLE) {
233 ioaddr += MEM_STNAND_CMD;
234 } else if (ctrl & NAND_ALE) {
235 ioaddr += MEM_STNAND_ADDR;
236 } else {
237 /* assume we want to r/w real data by default */
238 ioaddr += MEM_STNAND_DATA;
239 }
240 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
241 if (cmd != NAND_CMD_NONE) {
242 __raw_writeb(cmd, this->IO_ADDR_W);
243 wmb();
244 }
245}
246
247static int au1200_nand_device_ready(struct mtd_info *mtd)
248{
249 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
250}
251
63323ec5
ML		 252static struct mtd_partition db1200_nand_parts[] = {
253 {
254 .name = "NAND FS 0",
70342287 255 .offset = 0,
63323ec5
ML		 256 .size = 8 * 1024 * 1024,
257 },
258 {
259 .name = "NAND FS 1",
70342287 260 .offset = MTDPART_OFS_APPEND,
63323ec5
ML		 261 .size = MTDPART_SIZ_FULL
262 },
263};
264
265struct platform_nand_data db1200_nand_platdata = {
266 .chip = {
267 .nr_chips = 1,
268 .chip_offset = 0,
269 .nr_partitions = ARRAY_SIZE(db1200_nand_parts),
270 .partitions = db1200_nand_parts,
271 .chip_delay = 20,
63323ec5
ML		 272 },
273 .ctrl = {
274 .dev_ready = au1200_nand_device_ready,
275 .cmd_ctrl = au1200_nand_cmd_ctrl,
276 },
277};
278
279static struct resource db1200_nand_res[] = {
280 [0] = {
281 .start = DB1200_NAND_PHYS_ADDR,
282 .end = DB1200_NAND_PHYS_ADDR + 0xff,
283 .flags = IORESOURCE_MEM,
284 },
285};
286
287static struct platform_device db1200_nand_dev = {
288 .name = "gen_nand",
289 .num_resources = ARRAY_SIZE(db1200_nand_res),
290 .resource = db1200_nand_res,
291 .id = -1,
292 .dev = {
293 .platform_data = &db1200_nand_platdata,
294 }
295};
296
297/**********************************************************************/
298
299static struct smc91x_platdata db1200_eth_data = {
300 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
301 .leda = RPC_LED_100_10,
302 .ledb = RPC_LED_TX_RX,
303};
304
305static struct resource db1200_eth_res[] = {
306 [0] = {
307 .start = DB1200_ETH_PHYS_ADDR,
308 .end = DB1200_ETH_PHYS_ADDR + 0xf,
309 .flags = IORESOURCE_MEM,
310 },
311 [1] = {
312 .start = DB1200_ETH_INT,
313 .end = DB1200_ETH_INT,
314 .flags = IORESOURCE_IRQ,
315 },
316};
317
318static struct platform_device db1200_eth_dev = {
319 .dev = {
320 .platform_data = &db1200_eth_data,
321 },
322 .name = "smc91x",
323 .id = -1,
324 .num_resources = ARRAY_SIZE(db1200_eth_res),
325 .resource = db1200_eth_res,
326};
327
328/**********************************************************************/
329
54ff4a1d
ML		 330static struct pata_platform_info db1200_ide_info = {
331 .ioport_shift = DB1200_IDE_REG_SHIFT,
332};
333
334#define IDE_ALT_START (14 << DB1200_IDE_REG_SHIFT)
63323ec5
ML		 335static struct resource db1200_ide_res[] = {
336 [0] = {
337 .start = DB1200_IDE_PHYS_ADDR,
54ff4a1d 338 .end = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1,
63323ec5
ML		 339 .flags = IORESOURCE_MEM,
340 },
341 [1] = {
54ff4a1d
ML		 342 .start = DB1200_IDE_PHYS_ADDR + IDE_ALT_START,
343 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
344 .flags = IORESOURCE_MEM,
345 },
346 [2] = {
63323ec5
ML		 347 .start = DB1200_IDE_INT,
348 .end = DB1200_IDE_INT,
349 .flags = IORESOURCE_IRQ,
d4f07ae7 350 },
63323ec5
ML		 351};
352
7c4b24da 353static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
63323ec5
ML		 354
355static struct platform_device db1200_ide_dev = {
54ff4a1d 356 .name = "pata_platform",
63323ec5
ML		 357 .id = 0,
358 .dev = {
7c4b24da 359 .dma_mask = &au1200_ide_dmamask,
25c8f838 360 .coherent_dma_mask = DMA_BIT_MASK(32),
54ff4a1d 361 .platform_data = &db1200_ide_info,
63323ec5
ML		 362 },
363 .num_resources = ARRAY_SIZE(db1200_ide_res),
364 .resource = db1200_ide_res,
365};
366
367/**********************************************************************/
368
63323ec5
ML		 369/* SD carddetects: they're supposed to be edge-triggered, but ack
370 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one
371 * is disabled and its counterpart enabled. The 500ms timeout is
372 * because the carddetect isn't debounced in hardware.
373 */
374static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
375{
376 void(*mmc_cd)(struct mmc_host *, unsigned long);
377
378 if (irq == DB1200_SD0_INSERT_INT) {
379 disable_irq_nosync(DB1200_SD0_INSERT_INT);
380 enable_irq(DB1200_SD0_EJECT_INT);
381 } else {
382 disable_irq_nosync(DB1200_SD0_EJECT_INT);
383 enable_irq(DB1200_SD0_INSERT_INT);
384 }
385
386 /* link against CONFIG_MMC=m */
387 mmc_cd = symbol_get(mmc_detect_change);
388 if (mmc_cd) {
389 mmc_cd(ptr, msecs_to_jiffies(500));
390 symbol_put(mmc_detect_change);
391 }
392
393 return IRQ_HANDLED;
394}
395
396static int db1200_mmc_cd_setup(void *mmc_host, int en)
397{
398 int ret;
399
400 if (en) {
401 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
8b5690f8 402 0, "sd_insert", mmc_host);
63323ec5
ML		 403 if (ret)
404 goto out;
405
406 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
8b5690f8 407 0, "sd_eject", mmc_host);
63323ec5
ML		 408 if (ret) {
409 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
410 goto out;
411 }
412
413 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
414 enable_irq(DB1200_SD0_EJECT_INT);
415 else
416 enable_irq(DB1200_SD0_INSERT_INT);
417
418 } else {
419 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
420 free_irq(DB1200_SD0_EJECT_INT, mmc_host);
421 }
422 ret = 0;
423out:
424 return ret;
425}
426
427static void db1200_mmc_set_power(void *mmc_host, int state)
428{
429 if (state) {
430 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
431 msleep(400); /* stabilization time */
432 } else
433 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
434}
435
436static int db1200_mmc_card_readonly(void *mmc_host)
437{
438 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
439}
440
441static int db1200_mmc_card_inserted(void *mmc_host)
442{
443 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
444}
445
446static void db1200_mmcled_set(struct led_classdev *led,
447 enum led_brightness brightness)
448{
449 if (brightness != LED_OFF)
450 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
451 else
452 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
453}
454
455static struct led_classdev db1200_mmc_led = {
70342287 456 .brightness_set = db1200_mmcled_set,
63323ec5
ML		 457};
458
6f7c8623
ML		 459/* -- */
460
461static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
462{
463 void(*mmc_cd)(struct mmc_host *, unsigned long);
464
465 if (irq == PB1200_SD1_INSERT_INT) {
466 disable_irq_nosync(PB1200_SD1_INSERT_INT);
467 enable_irq(PB1200_SD1_EJECT_INT);
468 } else {
469 disable_irq_nosync(PB1200_SD1_EJECT_INT);
470 enable_irq(PB1200_SD1_INSERT_INT);
471 }
472
473 /* link against CONFIG_MMC=m */
474 mmc_cd = symbol_get(mmc_detect_change);
475 if (mmc_cd) {
476 mmc_cd(ptr, msecs_to_jiffies(500));
477 symbol_put(mmc_detect_change);
478 }
479
480 return IRQ_HANDLED;
481}
482
483static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
484{
485 int ret;
486
487 if (en) {
488 ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0,
489 "sd1_insert", mmc_host);
490 if (ret)
491 goto out;
492
493 ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0,
494 "sd1_eject", mmc_host);
495 if (ret) {
496 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
497 goto out;
498 }
499
500 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
501 enable_irq(PB1200_SD1_EJECT_INT);
502 else
503 enable_irq(PB1200_SD1_INSERT_INT);
504
505 } else {
506 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
507 free_irq(PB1200_SD1_EJECT_INT, mmc_host);
508 }
509 ret = 0;
510out:
511 return ret;
512}
513
514static void pb1200_mmc1led_set(struct led_classdev *led,
515 enum led_brightness brightness)
516{
517 if (brightness != LED_OFF)
518 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
519 else
520 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
521}
522
523static struct led_classdev pb1200_mmc1_led = {
70342287 524 .brightness_set = pb1200_mmc1led_set,
6f7c8623
ML		 525};
526
527static void pb1200_mmc1_set_power(void *mmc_host, int state)
528{
529 if (state) {
530 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
531 msleep(400); /* stabilization time */
532 } else
533 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
534}
535
536static int pb1200_mmc1_card_readonly(void *mmc_host)
537{
538 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
539}
540
541static int pb1200_mmc1_card_inserted(void *mmc_host)
542{
543 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
544}
545
546
547static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
548 [0] = {
549 .cd_setup = db1200_mmc_cd_setup,
550 .set_power = db1200_mmc_set_power,
551 .card_inserted = db1200_mmc_card_inserted,
552 .card_readonly = db1200_mmc_card_readonly,
553 .led = &db1200_mmc_led,
554 },
555 [1] = {
556 .cd_setup = pb1200_mmc1_cd_setup,
557 .set_power = pb1200_mmc1_set_power,
558 .card_inserted = pb1200_mmc1_card_inserted,
559 .card_readonly = pb1200_mmc1_card_readonly,
560 .led = &pb1200_mmc1_led,
561 },
37663860
ML		 562};
563
564static struct resource au1200_mmc0_resources[] = {
63323ec5 565 [0] = {
37663860
ML		 566 .start = AU1100_SD0_PHYS_ADDR,
567 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
568 .flags = IORESOURCE_MEM,
569 },
570 [1] = {
571 .start = AU1200_SD_INT,
572 .end = AU1200_SD_INT,
573 .flags = IORESOURCE_IRQ,
574 },
575 [2] = {
576 .start = AU1200_DSCR_CMD0_SDMS_TX0,
577 .end = AU1200_DSCR_CMD0_SDMS_TX0,
578 .flags = IORESOURCE_DMA,
579 },
580 [3] = {
581 .start = AU1200_DSCR_CMD0_SDMS_RX0,
582 .end = AU1200_DSCR_CMD0_SDMS_RX0,
583 .flags = IORESOURCE_DMA,
584 }
585};
586
70342287 587static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
37663860
ML		 588
589static struct platform_device db1200_mmc0_dev = {
590 .name = "au1xxx-mmc",
591 .id = 0,
592 .dev = {
593 .dma_mask = &au1xxx_mmc_dmamask,
594 .coherent_dma_mask = DMA_BIT_MASK(32),
6f7c8623 595 .platform_data = &db1200_mmc_platdata[0],
37663860
ML		 596 },
597 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
598 .resource = au1200_mmc0_resources,
599};
600
6f7c8623
ML		 601static struct resource au1200_mmc1_res[] = {
602 [0] = {
603 .start = AU1100_SD1_PHYS_ADDR,
604 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
605 .flags = IORESOURCE_MEM,
606 },
607 [1] = {
608 .start = AU1200_SD_INT,
609 .end = AU1200_SD_INT,
610 .flags = IORESOURCE_IRQ,
611 },
612 [2] = {
613 .start = AU1200_DSCR_CMD0_SDMS_TX1,
614 .end = AU1200_DSCR_CMD0_SDMS_TX1,
615 .flags = IORESOURCE_DMA,
616 },
617 [3] = {
618 .start = AU1200_DSCR_CMD0_SDMS_RX1,
619 .end = AU1200_DSCR_CMD0_SDMS_RX1,
620 .flags = IORESOURCE_DMA,
621 }
622};
623
624static struct platform_device pb1200_mmc1_dev = {
625 .name = "au1xxx-mmc",
626 .id = 1,
627 .dev = {
628 .dma_mask = &au1xxx_mmc_dmamask,
629 .coherent_dma_mask = DMA_BIT_MASK(32),
630 .platform_data = &db1200_mmc_platdata[1],
631 },
632 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
633 .resource = au1200_mmc1_res,
634};
635
37663860
ML		 636/**********************************************************************/
637
a9b71a8f
ML		 638static int db1200fb_panel_index(void)
639{
640 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
641}
642
643static int db1200fb_panel_init(void)
644{
645 /* Apply power */
646 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
647 BCSR_BOARD_LCDBL);
648 return 0;
649}
650
651static int db1200fb_panel_shutdown(void)
652{
653 /* Remove power */
654 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
655 BCSR_BOARD_LCDBL, 0);
656 return 0;
657}
658
659static struct au1200fb_platdata db1200fb_pd = {
660 .panel_index = db1200fb_panel_index,
661 .panel_init = db1200fb_panel_init,
70342287 662 .panel_shutdown = db1200fb_panel_shutdown,
a9b71a8f
ML		 663};
664
37663860 665static struct resource au1200_lcd_res[] = {
63323ec5 666 [0] = {
37663860
ML		 667 .start = AU1200_LCD_PHYS_ADDR,
668 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
669 .flags = IORESOURCE_MEM,
670 },
671 [1] = {
672 .start = AU1200_LCD_INT,
673 .end = AU1200_LCD_INT,
674 .flags = IORESOURCE_IRQ,
675 }
676};
677
678static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
679
680static struct platform_device au1200_lcd_dev = {
681 .name = "au1200-lcd",
682 .id = 0,
683 .dev = {
684 .dma_mask = &au1200_lcd_dmamask,
685 .coherent_dma_mask = DMA_BIT_MASK(32),
a9b71a8f 686 .platform_data = &db1200fb_pd,
63323ec5 687 },
37663860
ML		 688 .num_resources = ARRAY_SIZE(au1200_lcd_res),
689 .resource = au1200_lcd_res,
63323ec5
ML		 690};
691
692/**********************************************************************/
693
694static struct resource au1200_psc0_res[] = {
695 [0] = {
7cc2e272
ML		 696 .start = AU1550_PSC0_PHYS_ADDR,
697 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
63323ec5
ML		 698 .flags = IORESOURCE_MEM,
699 },
700 [1] = {
701 .start = AU1200_PSC0_INT,
702 .end = AU1200_PSC0_INT,
703 .flags = IORESOURCE_IRQ,
704 },
705 [2] = {
f2e442fd
ML		 706 .start = AU1200_DSCR_CMD0_PSC0_TX,
707 .end = AU1200_DSCR_CMD0_PSC0_TX,
63323ec5
ML		 708 .flags = IORESOURCE_DMA,
709 },
710 [3] = {
f2e442fd
ML		 711 .start = AU1200_DSCR_CMD0_PSC0_RX,
712 .end = AU1200_DSCR_CMD0_PSC0_RX,
63323ec5
ML		 713 .flags = IORESOURCE_DMA,
714 },
715};
716
717static struct platform_device db1200_i2c_dev = {
718 .name = "au1xpsc_smbus",
719 .id = 0, /* bus number */
720 .num_resources = ARRAY_SIZE(au1200_psc0_res),
721 .resource = au1200_psc0_res,
722};
723
724static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
725{
726 if (cs)
727 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
728 else
729 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
730}
731
732static struct au1550_spi_info db1200_spi_platdata = {
733 .mainclk_hz = 50000000, /* PSC0 clock */
734 .num_chipselect = 2,
735 .activate_cs = db1200_spi_cs_en,
736};
737
25c8f838 738static u64 spi_dmamask = DMA_BIT_MASK(32);
63323ec5
ML		 739
740static struct platform_device db1200_spi_dev = {
741 .dev = {
742 .dma_mask = &spi_dmamask,
25c8f838 743 .coherent_dma_mask = DMA_BIT_MASK(32),
63323ec5
ML		 744 .platform_data = &db1200_spi_platdata,
745 },
746 .name = "au1550-spi",
747 .id = 0, /* bus number */
748 .num_resources = ARRAY_SIZE(au1200_psc0_res),
749 .resource = au1200_psc0_res,
750};
751
05ae3231
ML		 752static struct resource au1200_psc1_res[] = {
753 [0] = {
7cc2e272
ML		 754 .start = AU1550_PSC1_PHYS_ADDR,
755 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
05ae3231
ML		 756 .flags = IORESOURCE_MEM,
757 },
758 [1] = {
759 .start = AU1200_PSC1_INT,
760 .end = AU1200_PSC1_INT,
761 .flags = IORESOURCE_IRQ,
762 },
763 [2] = {
f2e442fd
ML		 764 .start = AU1200_DSCR_CMD0_PSC1_TX,
765 .end = AU1200_DSCR_CMD0_PSC1_TX,
05ae3231
ML		 766 .flags = IORESOURCE_DMA,
767 },
768 [3] = {
f2e442fd
ML		 769 .start = AU1200_DSCR_CMD0_PSC1_RX,
770 .end = AU1200_DSCR_CMD0_PSC1_RX,
05ae3231
ML		 771 .flags = IORESOURCE_DMA,
772 },
773};
774
adbc7a5a 775/* AC97 or I2S device */
05ae3231
ML		 776static struct platform_device db1200_audio_dev = {
777 /* name assigned later based on switch setting */
778 .id = 1, /* PSC ID */
779 .num_resources = ARRAY_SIZE(au1200_psc1_res),
780 .resource = au1200_psc1_res,
781};
782
adbc7a5a
ML		 783/* DB1200 ASoC card device */
784static struct platform_device db1200_sound_dev = {
785 /* name assigned later based on switch setting */
786 .id = 1, /* PSC ID */
787};
788
ffc4fdbb
ML		 789static struct platform_device db1200_stac_dev = {
790 .name = "ac97-codec",
791 .id = 1, /* on PSC1 */
792};
793
5b0912be
ML		 794static struct platform_device db1200_audiodma_dev = {
795 .name = "au1xpsc-pcm",
796 .id = 1, /* PSC ID */
797};
798
63323ec5
ML		 799static struct platform_device *db1200_devs[] __initdata = {
800 NULL, /* PSC0, selected by S6.8 */
801 &db1200_ide_dev,
37663860
ML		 802 &db1200_mmc0_dev,
803 &au1200_lcd_dev,
63323ec5 804 &db1200_eth_dev,
63323ec5 805 &db1200_nand_dev,
5b0912be 806 &db1200_audiodma_dev,
05ae3231 807 &db1200_audio_dev,
ffc4fdbb 808 &db1200_stac_dev,
adbc7a5a 809 &db1200_sound_dev,
63323ec5
ML		 810};
811
6f7c8623
ML		 812static struct platform_device *pb1200_devs[] __initdata = {
813 &pb1200_mmc1_dev,
814};
815
816/* Some peripheral base addresses differ on the PB1200 */
817static int __init pb1200_res_fixup(void)
818{
819 /* CPLD Revs earlier than 4 cause problems */
820 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
821 printk(KERN_ERR "WARNING!!!\n");
822 printk(KERN_ERR "WARNING!!!\n");
823 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
824 printk(KERN_ERR "the board updated to latest revisions.\n");
825 printk(KERN_ERR "This software will not work reliably\n");
826 printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
827 printk(KERN_ERR "WARNING!!!\n");
828 printk(KERN_ERR "WARNING!!!\n");
829 return 1;
830 }
831
832 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
70342287 833 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff;
6f7c8623 834 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
70342287 835 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
6f7c8623 836 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
70342287 837 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff;
6f7c8623
ML		 838 return 0;
839}
840
bd8510df 841int __init db1200_dev_setup(void)
63323ec5
ML		 842{
843 unsigned long pfc;
844 unsigned short sw;
6f7c8623
ML		 845 int swapped, bid;
846
847 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
848 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
849 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
850 if (pb1200_res_fixup())
851 return -ENODEV;
852 }
63323ec5 853
7c4b24da 854 /* GPIO7 is low-level triggered CPLD cascade */
6f7c8623 855 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
7c4b24da
ML		 856 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
857
70342287 858 /* insert/eject pairs: one of both is always screaming. To avoid
7c4b24da
ML		 859 * issues they must not be automatically enabled when initially
860 * requested.
861 */
862 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
863 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
864 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
865 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
866 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
867 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
63323ec5
ML		 868
869 i2c_register_board_info(0, db1200_i2c_devs,
870 ARRAY_SIZE(db1200_i2c_devs));
871 spi_register_board_info(db1200_spi_devs,
872 ARRAY_SIZE(db1200_i2c_devs));
873
70342287 874 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
05ae3231 875 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
6f7c8623 876 * or S12 on the PB1200.
63323ec5
ML		 877 */
878
879 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
880 * this pin is claimed by PSC0 (unused though, but pinmux doesn't
881 * allow to free it without crippling the SPI interface).
882 * As a result, in SPI mode, OTG simply won't work (PSC0 uses
883 * it as an input pin which is pulled high on the boards).
884 */
1d09de7d 885 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
63323ec5
ML		 886
887 /* switch off OTG VBUS supply */
888 gpio_request(215, "otg-vbus");
889 gpio_direction_output(215, 1);
890
bd8510df 891 printk(KERN_INFO "%s device configuration:\n", get_system_type());
63323ec5
ML		 892
893 sw = bcsr_read(BCSR_SWITCHES);
894 if (sw & BCSR_SWITCHES_DIP_8) {
895 db1200_devs[0] = &db1200_i2c_dev;
896 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
897
898 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */
899
900 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
901 printk(KERN_INFO " OTG port VBUS supply available!\n");
902 } else {
903 db1200_devs[0] = &db1200_spi_dev;
904 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
905
906 pfc |= (1 << 17); /* PSC0 owns GPIO215 */
907
908 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
909 printk(KERN_INFO " OTG port VBUS supply disabled\n");
910 }
1d09de7d 911 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
63323ec5 912
05ae3231
ML		 913 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
914 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
915 */
916 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
917 if (sw == BCSR_SWITCHES_DIP_8) {
918 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
919 db1200_audio_dev.name = "au1xpsc_i2s";
adbc7a5a 920 db1200_sound_dev.name = "db1200-i2s";
05ae3231
ML		 921 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
922 } else {
923 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
924 db1200_audio_dev.name = "au1xpsc_ac97";
adbc7a5a 925 db1200_sound_dev.name = "db1200-ac97";
05ae3231
ML		 926 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
927 }
928
929 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
930 __raw_writel(PSC_SEL_CLK_SERCLK,
7c4b24da 931 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
05ae3231
ML		 932 wmb();
933
7cc2e272
ML		 934 db1x_register_pcmcia_socket(
935 AU1000_PCMCIA_ATTR_PHYS_ADDR,
936 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
937 AU1000_PCMCIA_MEM_PHYS_ADDR,
938 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
939 AU1000_PCMCIA_IO_PHYS_ADDR,
940 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
941 DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
942 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
943
944 db1x_register_pcmcia_socket(
945 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
946 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
947 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
948 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
949 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
950 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
951 DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
952 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
63323ec5
ML		 953
954 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
955 db1x_register_norflash(64 << 20, 2, swapped);
956
6f7c8623 957 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
63323ec5 958
6f7c8623
ML		 959 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
960 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
961 (bid == BCSR_WHOAMI_PB1200_DDR2))
962 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
63323ec5 963
63323ec5
ML		 964 return 0;
965}
Linux 6.x block layer and io_uring tree(s)