[linux-2.6-block.git] / arch / mips / alchemy / board-gpr.c

/*
 * GPR board platform device registration (Au1550)
 *
 * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <linux/gpio/machine.h>
#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/reboot.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1000.h>
#include <prom.h>

const char *get_system_type(void)
{
	return "GPR";
}

void __init prom_init(void)
{
	unsigned char *memsize_str;
	unsigned long memsize;

	prom_argc = fw_arg0;
	prom_argv = (char **)fw_arg1;
	prom_envp = (char **)fw_arg2;

	prom_init_cmdline();

	memsize_str = prom_getenv("memsize");
	if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
		memsize = 0x04000000;
	add_memory_region(0, memsize, BOOT_MEM_RAM);
}

void prom_putchar(unsigned char c)
{
	alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
}

static void gpr_reset(char *c)
{
	/* switch System-LED to orange (red# and green# on) */
	alchemy_gpio_direction_output(4, 0);
	alchemy_gpio_direction_output(5, 0);

	/* trigger watchdog to reset board in 200ms */
	printk(KERN_EMERG "Triggering watchdog soft reset...\n");
	raw_local_irq_disable();
	alchemy_gpio_direction_output(1, 0);
	udelay(1);
	alchemy_gpio_set_value(1, 1);
	while (1)
		cpu_wait();
}

static void gpr_power_off(void)
{
	while (1)
		cpu_wait();
}

void __init board_setup(void)
{
	printk(KERN_INFO "Trapeze ITS GPR board\n");

	pm_power_off = gpr_power_off;
	_machine_halt = gpr_power_off;
	_machine_restart = gpr_reset;

	/* Enable UART1/3 */
	alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
	alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);

	/* Take away Reset of UMTS-card */
	alchemy_gpio_direction_output(215, 1);
}

/*
 * Watchdog
 */
static struct resource gpr_wdt_resource[] = {
	[0] = {
		.start	= 1,
		.end	= 1,
		.name	= "gpr-adm6320-wdt",
		.flags	= IORESOURCE_IRQ,
	}
};

static struct platform_device gpr_wdt_device = {
	.name = "adm6320-wdt",
	.id = 0,
	.num_resources = ARRAY_SIZE(gpr_wdt_resource),
	.resource = gpr_wdt_resource,
};

/*
 * FLASH
 *
 * 0x00000000-0x00200000 : "kernel"
 * 0x00200000-0x00a00000 : "rootfs"
 * 0x01d00000-0x01f00000 : "config"
 * 0x01c00000-0x01d00000 : "yamon"
 * 0x01d00000-0x01d40000 : "yamon env vars"
 * 0x00000000-0x00a00000 : "kernel+rootfs"
 */
static struct mtd_partition gpr_mtd_partitions[] = {
	{
		.name	= "kernel",
		.size	= 0x00200000,
		.offset = 0,
	},
	{
		.name	= "rootfs",
		.size	= 0x00800000,
		.offset = MTDPART_OFS_APPEND,
		.mask_flags = MTD_WRITEABLE,
	},
	{
		.name	= "config",
		.size	= 0x00200000,
		.offset = 0x01d00000,
	},
	{
		.name	= "yamon",
		.size	= 0x00100000,
		.offset = 0x01c00000,
	},
	{
		.name	= "yamon env vars",
		.size	= 0x00040000,
		.offset = MTDPART_OFS_APPEND,
	},
	{
		.name	= "kernel+rootfs",
		.size	= 0x00a00000,
		.offset = 0,
	},
};

static struct physmap_flash_data gpr_flash_data = {
	.width		= 4,
	.nr_parts	= ARRAY_SIZE(gpr_mtd_partitions),
	.parts		= gpr_mtd_partitions,
};

static struct resource gpr_mtd_resource = {
	.start	= 0x1e000000,
	.end	= 0x1fffffff,
	.flags	= IORESOURCE_MEM,
};

static struct platform_device gpr_mtd_device = {
	.name		= "physmap-flash",
	.dev		= {
		.platform_data	= &gpr_flash_data,
	},
	.num_resources	= 1,
	.resource	= &gpr_mtd_resource,
};

/*
 * LEDs
 */
static const struct gpio_led gpr_gpio_leds[] = {
	{	/* green */
		.name			= "gpr:green",
		.gpio			= 4,
		.active_low		= 1,
	},
	{	/* red */
		.name			= "gpr:red",
		.gpio			= 5,
		.active_low		= 1,
	}
};

static struct gpio_led_platform_data gpr_led_data = {
	.num_leds = ARRAY_SIZE(gpr_gpio_leds),
	.leds = gpr_gpio_leds,
};

static struct platform_device gpr_led_devices = {
	.name = "leds-gpio",
	.id = -1,
	.dev = {
		.platform_data = &gpr_led_data,
	}
};

/*
 * I2C
 */
static struct gpiod_lookup_table gpr_i2c_gpiod_table = {
	.dev_id = "i2c-gpio",
	.table = {
		/*
		 * This should be on "GPIO2" which has base at 200 so
		 * the global numbers 209 and 210 should correspond to
		 * local offsets 9 and 10.
		 */
		GPIO_LOOKUP_IDX("alchemy-gpio2", 9, NULL, 0,
				GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP_IDX("alchemy-gpio2", 10, NULL, 1,
				GPIO_ACTIVE_HIGH),
	},
};

static struct i2c_gpio_platform_data gpr_i2c_data = {
	/*
	 * The open drain mode is hardwired somewhere or an electrical
	 * property of the alchemy GPIO controller.
	 */
	.sda_is_open_drain	= 1,
	.scl_is_open_drain	= 1,
	.udelay			= 2,		/* ~100 kHz */
	.timeout		= HZ,
};

static struct platform_device gpr_i2c_device = {
	.name			= "i2c-gpio",
	.id			= -1,
	.dev.platform_data	= &gpr_i2c_data,
};

static struct i2c_board_info gpr_i2c_info[] __initdata = {
	{
		I2C_BOARD_INFO("lm83", 0x18),
	}
};


static struct resource alchemy_pci_host_res[] = {
	[0] = {
		.start	= AU1500_PCI_PHYS_ADDR,
		.end	= AU1500_PCI_PHYS_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	},
};

static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
{
	if ((slot == 0) && (pin == 1))
		return AU1550_PCI_INTA;
	else if ((slot == 0) && (pin == 2))
		return AU1550_PCI_INTB;

	return 0xff;
}

static struct alchemy_pci_platdata gpr_pci_pd = {
	.board_map_irq	= gpr_map_pci_irq,
	.pci_cfg_set	= PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
			  PCI_CONFIG_CH |
#if defined(__MIPSEB__)
			  PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
#else
			  0,
#endif
};

static struct platform_device gpr_pci_host_dev = {
	.dev.platform_data = &gpr_pci_pd,
	.name		= "alchemy-pci",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(alchemy_pci_host_res),
	.resource	= alchemy_pci_host_res,
};

static struct platform_device *gpr_devices[] __initdata = {
	&gpr_wdt_device,
	&gpr_mtd_device,
	&gpr_i2c_device,
	&gpr_led_devices,
};

static int __init gpr_pci_init(void)
{
	return platform_device_register(&gpr_pci_host_dev);
}
/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
arch_initcall(gpr_pci_init);


static int __init gpr_dev_init(void)
{
	gpiod_add_lookup_table(&gpr_i2c_gpiod_table);
	i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));

	return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
}
device_initcall(gpr_dev_init);
Commit	Line	Data
cb8f55b9	1	/*
8e026910	2	* GPR board platform device registration (Au1550)
cb8f55b9 WG	3	*
	4	* Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20
8e026910	21	#include <linux/delay.h>
cb8f55b9	22	#include <linux/init.h>
8e026910 ML	23	#include <linux/interrupt.h>
8e026910 ML	24	#include <linux/kernel.h>
cb8f55b9	25	#include <linux/platform_device.h>
8e026910	26	#include <linux/pm.h>
cb8f55b9 WG	27	#include <linux/mtd/partitions.h>
	28	#include <linux/mtd/physmap.h>
	29	#include <linux/leds.h>
	30	#include <linux/gpio.h>
	31	#include <linux/i2c.h>
	32	#include <linux/i2c-gpio.h>
b2e63555	33	#include <linux/gpio/machine.h>
8e026910	34	#include <asm/bootinfo.h>
bdc92d74	35	#include <asm/idle.h>
8e026910	36	#include <asm/reboot.h>
cb8f55b9	37	#include <asm/mach-au1x00/au1000.h>
832f5dac	38	#include <asm/mach-au1x00/gpio-au1000.h>
8e026910 ML	39	#include <prom.h>
	40
	41	const char *get_system_type(void)
	42	{
	43	return "GPR";
	44	}
	45
	46	void __init prom_init(void)
	47	{
	48	unsigned char *memsize_str;
	49	unsigned long memsize;
	50
	51	prom_argc = fw_arg0;
	52	prom_argv = (char **)fw_arg1;
	53	prom_envp = (char **)fw_arg2;
	54
	55	prom_init_cmdline();
	56
	57	memsize_str = prom_getenv("memsize");
d334c2b9	58	if (!memsize_str \|\| kstrtoul(memsize_str, 0, &memsize))
8e026910	59	memsize = 0x04000000;
8e026910 ML	60	add_memory_region(0, memsize, BOOT_MEM_RAM);
	61	}
	62
	63	void prom_putchar(unsigned char c)
	64	{
	65	alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
	66	}
	67
	68	static void gpr_reset(char *c)
	69	{
	70	/* switch System-LED to orange (red# and green# on) */
	71	alchemy_gpio_direction_output(4, 0);
	72	alchemy_gpio_direction_output(5, 0);
	73
	74	/* trigger watchdog to reset board in 200ms */
	75	printk(KERN_EMERG "Triggering watchdog soft reset...\n");
	76	raw_local_irq_disable();
	77	alchemy_gpio_direction_output(1, 0);
	78	udelay(1);
	79	alchemy_gpio_set_value(1, 1);
	80	while (1)
	81	cpu_wait();
	82	}
	83
	84	static void gpr_power_off(void)
	85	{
	86	while (1)
	87	cpu_wait();
	88	}
	89
	90	void __init board_setup(void)
	91	{
	92	printk(KERN_INFO "Trapeze ITS GPR board\n");
	93
	94	pm_power_off = gpr_power_off;
	95	_machine_halt = gpr_power_off;
	96	_machine_restart = gpr_reset;
	97
	98	/* Enable UART1/3 */
	99	alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
	100	alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
	101
	102	/* Take away Reset of UMTS-card */
	103	alchemy_gpio_direction_output(215, 1);
	104	}
cb8f55b9 WG	105
	106	/*
	107	* Watchdog
	108	*/
	109	static struct resource gpr_wdt_resource[] = {
	110	[0] = {
	111	.start = 1,
	112	.end = 1,
	113	.name = "gpr-adm6320-wdt",
	114	.flags = IORESOURCE_IRQ,
	115	}
	116	};
	117
	118	static struct platform_device gpr_wdt_device = {
	119	.name = "adm6320-wdt",
	120	.id = 0,
	121	.num_resources = ARRAY_SIZE(gpr_wdt_resource),
	122	.resource = gpr_wdt_resource,
	123	};
	124
	125	/*
	126	* FLASH
	127	*
	128	* 0x00000000-0x00200000 : "kernel"
	129	* 0x00200000-0x00a00000 : "rootfs"
	130	* 0x01d00000-0x01f00000 : "config"
	131	* 0x01c00000-0x01d00000 : "yamon"
	132	* 0x01d00000-0x01d40000 : "yamon env vars"
	133	* 0x00000000-0x00a00000 : "kernel+rootfs"
	134	*/
	135	static struct mtd_partition gpr_mtd_partitions[] = {
	136	{
	137	.name = "kernel",
	138	.size = 0x00200000,
70342287	139	.offset = 0,
cb8f55b9 WG	140	},
	141	{
	142	.name = "rootfs",
	143	.size = 0x00800000,
70342287	144	.offset = MTDPART_OFS_APPEND,
cb8f55b9 WG	145	.mask_flags = MTD_WRITEABLE,
	146	},
	147	{
	148	.name = "config",
	149	.size = 0x00200000,
70342287	150	.offset = 0x01d00000,
cb8f55b9 WG	151	},
	152	{
	153	.name = "yamon",
	154	.size = 0x00100000,
70342287	155	.offset = 0x01c00000,
cb8f55b9 WG	156	},
	157	{
	158	.name = "yamon env vars",
	159	.size = 0x00040000,
70342287	160	.offset = MTDPART_OFS_APPEND,
cb8f55b9 WG	161	},
	162	{
	163	.name = "kernel+rootfs",
	164	.size = 0x00a00000,
70342287	165	.offset = 0,
cb8f55b9 WG	166	},
	167	};
	168
	169	static struct physmap_flash_data gpr_flash_data = {
	170	.width = 4,
	171	.nr_parts = ARRAY_SIZE(gpr_mtd_partitions),
	172	.parts = gpr_mtd_partitions,
	173	};
	174
	175	static struct resource gpr_mtd_resource = {
	176	.start = 0x1e000000,
	177	.end = 0x1fffffff,
	178	.flags = IORESOURCE_MEM,
	179	};
	180
	181	static struct platform_device gpr_mtd_device = {
	182	.name = "physmap-flash",
	183	.dev = {
	184	.platform_data = &gpr_flash_data,
	185	},
	186	.num_resources = 1,
	187	.resource = &gpr_mtd_resource,
	188	};
	189
	190	/*
	191	* LEDs
	192	*/
1fd88d9b	193	static const struct gpio_led gpr_gpio_leds[] = {
cb8f55b9 WG	194	{ /* green */
	195	.name = "gpr:green",
	196	.gpio = 4,
	197	.active_low = 1,
	198	},
	199	{ /* red */
	200	.name = "gpr:red",
	201	.gpio = 5,
	202	.active_low = 1,
	203	}
	204	};
	205
	206	static struct gpio_led_platform_data gpr_led_data = {
	207	.num_leds = ARRAY_SIZE(gpr_gpio_leds),
	208	.leds = gpr_gpio_leds,
	209	};
	210
	211	static struct platform_device gpr_led_devices = {
	212	.name = "leds-gpio",
	213	.id = -1,
	214	.dev = {
	215	.platform_data = &gpr_led_data,
	216	}
	217	};
	218
	219	/*
	220	* I2C
	221	*/
b2e63555 LW	222	static struct gpiod_lookup_table gpr_i2c_gpiod_table = {
	223	.dev_id = "i2c-gpio",
	224	.table = {
	225	/*
	226	* This should be on "GPIO2" which has base at 200 so
	227	* the global numbers 209 and 210 should correspond to
	228	* local offsets 9 and 10.
	229	*/
	230	GPIO_LOOKUP_IDX("alchemy-gpio2", 9, NULL, 0,
	231	GPIO_ACTIVE_HIGH),
	232	GPIO_LOOKUP_IDX("alchemy-gpio2", 10, NULL, 1,
	233	GPIO_ACTIVE_HIGH),
	234	},
	235	};
	236
cb8f55b9	237	static struct i2c_gpio_platform_data gpr_i2c_data = {
4d0ce62c LW	238	/*
	239	* The open drain mode is hardwired somewhere or an electrical
	240	* property of the alchemy GPIO controller.
	241	*/
cb8f55b9	242	.sda_is_open_drain = 1,
cb8f55b9 WG	243	.scl_is_open_drain = 1,
	244	.udelay = 2, /* ~100 kHz */
	245	.timeout = HZ,
8e026910	246	};
cb8f55b9 WG	247
	248	static struct platform_device gpr_i2c_device = {
	249	.name = "i2c-gpio",
	250	.id = -1,
	251	.dev.platform_data = &gpr_i2c_data,
	252	};
	253
	254	static struct i2c_board_info gpr_i2c_info[] __initdata = {
	255	{
	256	I2C_BOARD_INFO("lm83", 0x18),
cb8f55b9 WG	257	}
	258	};
	259
7517de34 ML	260
	261
	262	static struct resource alchemy_pci_host_res[] = {
	263	[0] = {
	264	.start = AU1500_PCI_PHYS_ADDR,
	265	.end = AU1500_PCI_PHYS_ADDR + 0xfff,
	266	.flags = IORESOURCE_MEM,
	267	},
	268	};
	269
	270	static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
	271	{
	272	if ((slot == 0) && (pin == 1))
	273	return AU1550_PCI_INTA;
	274	else if ((slot == 0) && (pin == 2))
	275	return AU1550_PCI_INTB;
	276
8e026910	277	return 0xff;
7517de34 ML	278	}
	279
	280	static struct alchemy_pci_platdata gpr_pci_pd = {
	281	.board_map_irq = gpr_map_pci_irq,
	282	.pci_cfg_set = PCI_CONFIG_AEN \| PCI_CONFIG_R2H \| PCI_CONFIG_R1H \|
	283	PCI_CONFIG_CH \|
	284	#if defined(__MIPSEB__)
	285	PCI_CONFIG_SIC_HWA_DAT \| PCI_CONFIG_SM,
	286	#else
	287	0,
	288	#endif
	289	};
	290
	291	static struct platform_device gpr_pci_host_dev = {
	292	.dev.platform_data = &gpr_pci_pd,
	293	.name = "alchemy-pci",
	294	.id = 0,
	295	.num_resources = ARRAY_SIZE(alchemy_pci_host_res),
	296	.resource = alchemy_pci_host_res,
	297	};
	298
cb8f55b9 WG	299	static struct platform_device *gpr_devices[] __initdata = {
	300	&gpr_wdt_device,
	301	&gpr_mtd_device,
	302	&gpr_i2c_device,
	303	&gpr_led_devices,
	304	};
	305
7517de34 ML	306	static int __init gpr_pci_init(void)
	307	{
	308	return platform_device_register(&gpr_pci_host_dev);
	309	}
	310	/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
	311	arch_initcall(gpr_pci_init);
	312
	313
cb8f55b9 WG	314	static int __init gpr_dev_init(void)
cb8f55b9 WG	315	{
b2e63555	316	gpiod_add_lookup_table(&gpr_i2c_gpiod_table);
cb8f55b9 WG	317	i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
	318
	319	return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
	320	}
	321	device_initcall(gpr_dev_init);