Commit | Line | Data |
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eedbdab9 | 1 | /* |
1e529803 MS |
2 | * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> |
3 | * Copyright (C) 2012-2013 Xilinx, Inc. | |
eedbdab9 MS |
4 | * Copyright (C) 2007-2009 PetaLogix |
5 | * Copyright (C) 2006 Atmark Techno, Inc. | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
eedbdab9 | 12 | #include <linux/interrupt.h> |
eedbdab9 MS |
13 | #include <linux/delay.h> |
14 | #include <linux/sched.h> | |
e6017571 | 15 | #include <linux/sched/clock.h> |
839396ab | 16 | #include <linux/sched_clock.h> |
eedbdab9 | 17 | #include <linux/clk.h> |
eedbdab9 | 18 | #include <linux/clockchips.h> |
cfd4eaef | 19 | #include <linux/of_address.h> |
5c9f303e | 20 | #include <linux/of_irq.h> |
5ce07a5c | 21 | #include <linux/timecounter.h> |
eedbdab9 | 22 | #include <asm/cpuinfo.h> |
eedbdab9 | 23 | |
cfd4eaef | 24 | static void __iomem *timer_baseaddr; |
eedbdab9 | 25 | |
29e3dbb1 MS |
26 | static unsigned int freq_div_hz; |
27 | static unsigned int timer_clock_freq; | |
ccea0e6e | 28 | |
eedbdab9 MS |
29 | #define TCSR0 (0x00) |
30 | #define TLR0 (0x04) | |
31 | #define TCR0 (0x08) | |
32 | #define TCSR1 (0x10) | |
33 | #define TLR1 (0x14) | |
34 | #define TCR1 (0x18) | |
35 | ||
36 | #define TCSR_MDT (1<<0) | |
37 | #define TCSR_UDT (1<<1) | |
38 | #define TCSR_GENT (1<<2) | |
39 | #define TCSR_CAPT (1<<3) | |
40 | #define TCSR_ARHT (1<<4) | |
41 | #define TCSR_LOAD (1<<5) | |
42 | #define TCSR_ENIT (1<<6) | |
43 | #define TCSR_ENT (1<<7) | |
44 | #define TCSR_TINT (1<<8) | |
45 | #define TCSR_PWMA (1<<9) | |
46 | #define TCSR_ENALL (1<<10) | |
47 | ||
a1715bb7 MS |
48 | static unsigned int (*read_fn)(void __iomem *); |
49 | static void (*write_fn)(u32, void __iomem *); | |
50 | ||
51 | static void timer_write32(u32 val, void __iomem *addr) | |
52 | { | |
53 | iowrite32(val, addr); | |
54 | } | |
55 | ||
56 | static unsigned int timer_read32(void __iomem *addr) | |
57 | { | |
58 | return ioread32(addr); | |
59 | } | |
60 | ||
61 | static void timer_write32_be(u32 val, void __iomem *addr) | |
62 | { | |
63 | iowrite32be(val, addr); | |
64 | } | |
65 | ||
66 | static unsigned int timer_read32_be(void __iomem *addr) | |
67 | { | |
68 | return ioread32be(addr); | |
69 | } | |
70 | ||
5955563a | 71 | static inline void xilinx_timer0_stop(void) |
eedbdab9 | 72 | { |
a1715bb7 MS |
73 | write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT, |
74 | timer_baseaddr + TCSR0); | |
eedbdab9 MS |
75 | } |
76 | ||
5955563a | 77 | static inline void xilinx_timer0_start_periodic(unsigned long load_val) |
eedbdab9 MS |
78 | { |
79 | if (!load_val) | |
80 | load_val = 1; | |
9e77dab6 | 81 | /* loading value to timer reg */ |
a1715bb7 | 82 | write_fn(load_val, timer_baseaddr + TLR0); |
eedbdab9 MS |
83 | |
84 | /* load the initial value */ | |
a1715bb7 | 85 | write_fn(TCSR_LOAD, timer_baseaddr + TCSR0); |
eedbdab9 MS |
86 | |
87 | /* see timer data sheet for detail | |
88 | * !ENALL - don't enable 'em all | |
89 | * !PWMA - disable pwm | |
90 | * TINT - clear interrupt status | |
91 | * ENT- enable timer itself | |
f7f4786c | 92 | * ENIT - enable interrupt |
eedbdab9 MS |
93 | * !LOAD - clear the bit to let go |
94 | * ARHT - auto reload | |
95 | * !CAPT - no external trigger | |
96 | * !GENT - no external signal | |
97 | * UDT - set the timer as down counter | |
98 | * !MDT0 - generate mode | |
99 | */ | |
a1715bb7 MS |
100 | write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT, |
101 | timer_baseaddr + TCSR0); | |
eedbdab9 MS |
102 | } |
103 | ||
5955563a | 104 | static inline void xilinx_timer0_start_oneshot(unsigned long load_val) |
eedbdab9 MS |
105 | { |
106 | if (!load_val) | |
107 | load_val = 1; | |
9e77dab6 | 108 | /* loading value to timer reg */ |
a1715bb7 | 109 | write_fn(load_val, timer_baseaddr + TLR0); |
eedbdab9 MS |
110 | |
111 | /* load the initial value */ | |
a1715bb7 | 112 | write_fn(TCSR_LOAD, timer_baseaddr + TCSR0); |
eedbdab9 | 113 | |
a1715bb7 MS |
114 | write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT, |
115 | timer_baseaddr + TCSR0); | |
eedbdab9 MS |
116 | } |
117 | ||
5955563a | 118 | static int xilinx_timer_set_next_event(unsigned long delta, |
eedbdab9 MS |
119 | struct clock_event_device *dev) |
120 | { | |
121 | pr_debug("%s: next event, delta %x\n", __func__, (u32)delta); | |
5955563a | 122 | xilinx_timer0_start_oneshot(delta); |
eedbdab9 MS |
123 | return 0; |
124 | } | |
125 | ||
9797529d | 126 | static int xilinx_timer_shutdown(struct clock_event_device *evt) |
eedbdab9 | 127 | { |
9797529d VK |
128 | pr_info("%s\n", __func__); |
129 | xilinx_timer0_stop(); | |
130 | return 0; | |
131 | } | |
132 | ||
133 | static int xilinx_timer_set_periodic(struct clock_event_device *evt) | |
134 | { | |
135 | pr_info("%s\n", __func__); | |
136 | xilinx_timer0_start_periodic(freq_div_hz); | |
137 | return 0; | |
eedbdab9 MS |
138 | } |
139 | ||
5955563a | 140 | static struct clock_event_device clockevent_xilinx_timer = { |
9797529d VK |
141 | .name = "xilinx_clockevent", |
142 | .features = CLOCK_EVT_FEAT_ONESHOT | | |
143 | CLOCK_EVT_FEAT_PERIODIC, | |
144 | .shift = 8, | |
145 | .rating = 300, | |
146 | .set_next_event = xilinx_timer_set_next_event, | |
147 | .set_state_shutdown = xilinx_timer_shutdown, | |
148 | .set_state_periodic = xilinx_timer_set_periodic, | |
eedbdab9 MS |
149 | }; |
150 | ||
151 | static inline void timer_ack(void) | |
152 | { | |
a1715bb7 | 153 | write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0); |
eedbdab9 MS |
154 | } |
155 | ||
156 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | |
157 | { | |
5955563a | 158 | struct clock_event_device *evt = &clockevent_xilinx_timer; |
eedbdab9 MS |
159 | timer_ack(); |
160 | evt->event_handler(evt); | |
161 | return IRQ_HANDLED; | |
162 | } | |
163 | ||
164 | static struct irqaction timer_irqaction = { | |
165 | .handler = timer_interrupt, | |
db2a7df0 | 166 | .flags = IRQF_TIMER, |
eedbdab9 | 167 | .name = "timer", |
5955563a | 168 | .dev_id = &clockevent_xilinx_timer, |
eedbdab9 MS |
169 | }; |
170 | ||
05864217 | 171 | static __init int xilinx_clockevent_init(void) |
eedbdab9 | 172 | { |
5955563a | 173 | clockevent_xilinx_timer.mult = |
ccea0e6e | 174 | div_sc(timer_clock_freq, NSEC_PER_SEC, |
5955563a MS |
175 | clockevent_xilinx_timer.shift); |
176 | clockevent_xilinx_timer.max_delta_ns = | |
177 | clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer); | |
bb26081a | 178 | clockevent_xilinx_timer.max_delta_ticks = (u32)~0; |
5955563a MS |
179 | clockevent_xilinx_timer.min_delta_ns = |
180 | clockevent_delta2ns(1, &clockevent_xilinx_timer); | |
bb26081a | 181 | clockevent_xilinx_timer.min_delta_ticks = 1; |
5955563a MS |
182 | clockevent_xilinx_timer.cpumask = cpumask_of(0); |
183 | clockevents_register_device(&clockevent_xilinx_timer); | |
05864217 DL |
184 | |
185 | return 0; | |
eedbdab9 MS |
186 | } |
187 | ||
839396ab MS |
188 | static u64 xilinx_clock_read(void) |
189 | { | |
a1715bb7 | 190 | return read_fn(timer_baseaddr + TCR1); |
839396ab MS |
191 | } |
192 | ||
a5a1d1c2 | 193 | static u64 xilinx_read(struct clocksource *cs) |
eedbdab9 MS |
194 | { |
195 | /* reading actual value of timer 1 */ | |
a5a1d1c2 | 196 | return (u64)xilinx_clock_read(); |
eedbdab9 MS |
197 | } |
198 | ||
5955563a | 199 | static struct timecounter xilinx_tc = { |
519e9f41 MS |
200 | .cc = NULL, |
201 | }; | |
202 | ||
a5a1d1c2 | 203 | static u64 xilinx_cc_read(const struct cyclecounter *cc) |
519e9f41 | 204 | { |
5955563a | 205 | return xilinx_read(NULL); |
519e9f41 MS |
206 | } |
207 | ||
5955563a MS |
208 | static struct cyclecounter xilinx_cc = { |
209 | .read = xilinx_cc_read, | |
519e9f41 | 210 | .mask = CLOCKSOURCE_MASK(32), |
c8f77436 | 211 | .shift = 8, |
519e9f41 MS |
212 | }; |
213 | ||
5955563a | 214 | static int __init init_xilinx_timecounter(void) |
519e9f41 | 215 | { |
5955563a MS |
216 | xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, |
217 | xilinx_cc.shift); | |
519e9f41 | 218 | |
5955563a | 219 | timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock()); |
519e9f41 MS |
220 | |
221 | return 0; | |
222 | } | |
223 | ||
eedbdab9 | 224 | static struct clocksource clocksource_microblaze = { |
5955563a | 225 | .name = "xilinx_clocksource", |
eedbdab9 | 226 | .rating = 300, |
5955563a | 227 | .read = xilinx_read, |
eedbdab9 | 228 | .mask = CLOCKSOURCE_MASK(32), |
eedbdab9 MS |
229 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
230 | }; | |
231 | ||
5955563a | 232 | static int __init xilinx_clocksource_init(void) |
eedbdab9 | 233 | { |
05864217 DL |
234 | int ret; |
235 | ||
236 | ret = clocksource_register_hz(&clocksource_microblaze, | |
237 | timer_clock_freq); | |
238 | if (ret) { | |
239 | pr_err("failed to register clocksource"); | |
240 | return ret; | |
241 | } | |
eedbdab9 MS |
242 | |
243 | /* stop timer1 */ | |
a1715bb7 MS |
244 | write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT, |
245 | timer_baseaddr + TCSR1); | |
eedbdab9 | 246 | /* start timer1 - up counting without interrupt */ |
a1715bb7 | 247 | write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1); |
519e9f41 MS |
248 | |
249 | /* register timecounter - for ftrace support */ | |
05864217 | 250 | return init_xilinx_timecounter(); |
eedbdab9 MS |
251 | } |
252 | ||
05864217 | 253 | static int __init xilinx_timer_init(struct device_node *timer) |
eedbdab9 | 254 | { |
c1120542 | 255 | struct clk *clk; |
03fe0d3c | 256 | static int initialized; |
5a26cd69 | 257 | u32 irq; |
eedbdab9 | 258 | u32 timer_num = 1; |
05864217 | 259 | int ret; |
cfd4eaef | 260 | |
03fe0d3c | 261 | if (initialized) |
63b7c83e | 262 | return -EINVAL; |
03fe0d3c MS |
263 | |
264 | initialized = 1; | |
265 | ||
cfd4eaef MS |
266 | timer_baseaddr = of_iomap(timer, 0); |
267 | if (!timer_baseaddr) { | |
268 | pr_err("ERROR: invalid timer base address\n"); | |
05864217 | 269 | return -ENXIO; |
cfd4eaef | 270 | } |
9e77dab6 | 271 | |
a1715bb7 MS |
272 | write_fn = timer_write32; |
273 | read_fn = timer_read32; | |
274 | ||
275 | write_fn(TCSR_MDT, timer_baseaddr + TCSR0); | |
276 | if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) { | |
277 | write_fn = timer_write32_be; | |
278 | read_fn = timer_read32_be; | |
279 | } | |
280 | ||
9d0ced00 | 281 | irq = irq_of_parse_and_map(timer, 0); |
05864217 DL |
282 | if (irq <= 0) { |
283 | pr_err("Failed to parse and map irq"); | |
284 | return -EINVAL; | |
285 | } | |
cfd4eaef MS |
286 | |
287 | of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num); | |
eedbdab9 | 288 | if (timer_num) { |
05864217 DL |
289 | pr_err("Please enable two timers in HW\n"); |
290 | return -EINVAL; | |
eedbdab9 MS |
291 | } |
292 | ||
f2b8ae0e | 293 | pr_info("%pOF: irq=%d\n", timer, irq); |
eedbdab9 | 294 | |
c1120542 MS |
295 | clk = of_clk_get(timer, 0); |
296 | if (IS_ERR(clk)) { | |
297 | pr_err("ERROR: timer CCF input clock not found\n"); | |
298 | /* If there is clock-frequency property than use it */ | |
299 | of_property_read_u32(timer, "clock-frequency", | |
300 | &timer_clock_freq); | |
301 | } else { | |
302 | timer_clock_freq = clk_get_rate(clk); | |
303 | } | |
304 | ||
305 | if (!timer_clock_freq) { | |
306 | pr_err("ERROR: Using CPU clock frequency\n"); | |
ccea0e6e | 307 | timer_clock_freq = cpuinfo.cpu_clock_freq; |
c1120542 | 308 | } |
ccea0e6e MS |
309 | |
310 | freq_div_hz = timer_clock_freq / HZ; | |
eedbdab9 | 311 | |
05864217 DL |
312 | ret = setup_irq(irq, &timer_irqaction); |
313 | if (ret) { | |
314 | pr_err("Failed to setup IRQ"); | |
315 | return ret; | |
316 | } | |
317 | ||
05864217 DL |
318 | ret = xilinx_clocksource_init(); |
319 | if (ret) | |
320 | return ret; | |
321 | ||
322 | ret = xilinx_clockevent_init(); | |
323 | if (ret) | |
324 | return ret; | |
9c6f6f54 | 325 | |
839396ab | 326 | sched_clock_register(xilinx_clock_read, 32, timer_clock_freq); |
05864217 DL |
327 | |
328 | return 0; | |
eedbdab9 | 329 | } |
4bcd943e | 330 | |
17273395 | 331 | TIMER_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a", |
4bcd943e | 332 | xilinx_timer_init); |