[linux-block.git] / arch / microblaze / kernel / timer.c

/*
 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
 * Copyright (C) 2007-2009 PetaLogix
 * Copyright (C) 2006 Atmark Techno, Inc.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/interrupt.h>
#include <linux/profile.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/bug.h>
#include <asm/cpuinfo.h>
#include <asm/setup.h>
#include <asm/prom.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <linux/cnt32_to_63.h>

#ifdef CONFIG_SELFMOD_TIMER
#include <asm/selfmod.h>
#define TIMER_BASE	BARRIER_BASE_ADDR
#else
static unsigned int timer_baseaddr;
#define TIMER_BASE	timer_baseaddr
#endif

unsigned int freq_div_hz;
unsigned int timer_clock_freq;

#define TCSR0	(0x00)
#define TLR0	(0x04)
#define TCR0	(0x08)
#define TCSR1	(0x10)
#define TLR1	(0x14)
#define TCR1	(0x18)

#define TCSR_MDT	(1<<0)
#define TCSR_UDT	(1<<1)
#define TCSR_GENT	(1<<2)
#define TCSR_CAPT	(1<<3)
#define TCSR_ARHT	(1<<4)
#define TCSR_LOAD	(1<<5)
#define TCSR_ENIT	(1<<6)
#define TCSR_ENT	(1<<7)
#define TCSR_TINT	(1<<8)
#define TCSR_PWMA	(1<<9)
#define TCSR_ENALL	(1<<10)

static inline void microblaze_timer0_stop(void)
{
	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT);
}

static inline void microblaze_timer0_start_periodic(unsigned long load_val)
{
	if (!load_val)
		load_val = 1;
	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */

	/* load the initial value */
	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);

	/* see timer data sheet for detail
	 * !ENALL - don't enable 'em all
	 * !PWMA - disable pwm
	 * TINT - clear interrupt status
	 * ENT- enable timer itself
	 * EINT - enable interrupt
	 * !LOAD - clear the bit to let go
	 * ARHT - auto reload
	 * !CAPT - no external trigger
	 * !GENT - no external signal
	 * UDT - set the timer as down counter
	 * !MDT0 - generate mode
	 */
	out_be32(TIMER_BASE + TCSR0,
			TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
}

static inline void microblaze_timer0_start_oneshot(unsigned long load_val)
{
	if (!load_val)
		load_val = 1;
	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */

	/* load the initial value */
	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);

	out_be32(TIMER_BASE + TCSR0,
			TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
}

static int microblaze_timer_set_next_event(unsigned long delta,
					struct clock_event_device *dev)
{
	pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
	microblaze_timer0_start_oneshot(delta);
	return 0;
}

static void microblaze_timer_set_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		printk(KERN_INFO "%s: periodic\n", __func__);
		microblaze_timer0_start_periodic(freq_div_hz);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		printk(KERN_INFO "%s: oneshot\n", __func__);
		break;
	case CLOCK_EVT_MODE_UNUSED:
		printk(KERN_INFO "%s: unused\n", __func__);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
		printk(KERN_INFO "%s: shutdown\n", __func__);
		microblaze_timer0_stop();
		break;
	case CLOCK_EVT_MODE_RESUME:
		printk(KERN_INFO "%s: resume\n", __func__);
		break;
	}
}

static struct clock_event_device clockevent_microblaze_timer = {
	.name		= "microblaze_clockevent",
	.features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
	.shift		= 8,
	.rating		= 300,
	.set_next_event	= microblaze_timer_set_next_event,
	.set_mode	= microblaze_timer_set_mode,
};

static inline void timer_ack(void)
{
	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0));
}

static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_microblaze_timer;
#ifdef CONFIG_HEART_BEAT
	heartbeat();
#endif
	timer_ack();
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction timer_irqaction = {
	.handler = timer_interrupt,
	.flags = IRQF_DISABLED | IRQF_TIMER,
	.name = "timer",
	.dev_id = &clockevent_microblaze_timer,
};

static __init void microblaze_clockevent_init(void)
{
	clockevent_microblaze_timer.mult =
		div_sc(timer_clock_freq, NSEC_PER_SEC,
				clockevent_microblaze_timer.shift);
	clockevent_microblaze_timer.max_delta_ns =
		clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);
	clockevent_microblaze_timer.min_delta_ns =
		clockevent_delta2ns(1, &clockevent_microblaze_timer);
	clockevent_microblaze_timer.cpumask = cpumask_of(0);
	clockevents_register_device(&clockevent_microblaze_timer);
}

static cycle_t microblaze_read(struct clocksource *cs)
{
	/* reading actual value of timer 1 */
	return (cycle_t) (in_be32(TIMER_BASE + TCR1));
}

static struct timecounter microblaze_tc = {
	.cc = NULL,
};

static cycle_t microblaze_cc_read(const struct cyclecounter *cc)
{
	return microblaze_read(NULL);
}

static struct cyclecounter microblaze_cc = {
	.read = microblaze_cc_read,
	.mask = CLOCKSOURCE_MASK(32),
	.shift = 8,
};

int __init init_microblaze_timecounter(void)
{
	microblaze_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
				microblaze_cc.shift);

	timecounter_init(&microblaze_tc, &microblaze_cc, sched_clock());

	return 0;
}

static struct clocksource clocksource_microblaze = {
	.name		= "microblaze_clocksource",
	.rating		= 300,
	.read		= microblaze_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.shift		= 8, /* I can shift it */
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static int __init microblaze_clocksource_init(void)
{
	clocksource_microblaze.mult =
			clocksource_hz2mult(timer_clock_freq,
						clocksource_microblaze.shift);
	if (clocksource_register(&clocksource_microblaze))
		panic("failed to register clocksource");

	/* stop timer1 */
	out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);
	/* start timer1 - up counting without interrupt */
	out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);

	/* register timecounter - for ftrace support */
	init_microblaze_timecounter();
	return 0;
}

/*
 * We have to protect accesses before timer initialization
 * and return 0 for sched_clock function below.
 */
static int timer_initialized;

void __init time_init(void)
{
	u32 irq, i = 0;
	u32 timer_num = 1;
	struct device_node *timer = NULL;
	const void *prop;
#ifdef CONFIG_SELFMOD_TIMER
	unsigned int timer_baseaddr = 0;
	int arr_func[] = {
				(int)&microblaze_read,
				(int)&timer_interrupt,
				(int)&microblaze_clocksource_init,
				(int)&microblaze_timer_set_mode,
				(int)&microblaze_timer_set_next_event,
				0
			};
#endif
	const char * const timer_list[] = {
		"xlnx,xps-timer-1.00.a",
		NULL
	};

	for (i = 0; timer_list[i] != NULL; i++) {
		timer = of_find_compatible_node(NULL, NULL, timer_list[i]);
		if (timer)
			break;
	}
	BUG_ON(!timer);

	timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL));
	timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
	irq = be32_to_cpup(of_get_property(timer, "interrupts", NULL));
	timer_num = be32_to_cpup(of_get_property(timer,
						"xlnx,one-timer-only", NULL));
	if (timer_num) {
		eprintk(KERN_EMERG "Please enable two timers in HW\n");
		BUG();
	}

#ifdef CONFIG_SELFMOD_TIMER
	selfmod_function((int *) arr_func, timer_baseaddr);
#endif
	printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
		timer_list[i], timer_baseaddr, irq);

	/* If there is clock-frequency property than use it */
	prop = of_get_property(timer, "clock-frequency", NULL);
	if (prop)
		timer_clock_freq = be32_to_cpup(prop);
	else
		timer_clock_freq = cpuinfo.cpu_clock_freq;

	freq_div_hz = timer_clock_freq / HZ;

	setup_irq(irq, &timer_irqaction);
#ifdef CONFIG_HEART_BEAT
	setup_heartbeat();
#endif
	microblaze_clocksource_init();
	microblaze_clockevent_init();
	timer_initialized = 1;
}

unsigned long long notrace sched_clock(void)
{
	if (timer_initialized) {
		struct clocksource *cs = &clocksource_microblaze;
		cycle_t cyc = cnt32_to_63(cs->read(NULL));
		return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
	}
	return 0;
}
Commit	Line	Data
eedbdab9 MS	1	/*
	2	* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
	3	* Copyright (C) 2007-2009 PetaLogix
	4	* Copyright (C) 2006 Atmark Techno, Inc.
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/param.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/profile.h>
	16	#include <linux/irq.h>
	17	#include <linux/delay.h>
	18	#include <linux/sched.h>
	19	#include <linux/spinlock.h>
	20	#include <linux/err.h>
	21	#include <linux/clk.h>
	22	#include <linux/clocksource.h>
	23	#include <linux/clockchips.h>
	24	#include <linux/io.h>
892ee92b	25	#include <linux/bug.h>
eedbdab9 MS	26	#include <asm/cpuinfo.h>
	27	#include <asm/setup.h>
	28	#include <asm/prom.h>
	29	#include <asm/irq.h>
	30	#include <asm/system.h>
c8f77436	31	#include <linux/cnt32_to_63.h>
eedbdab9 MS	32
	33	#ifdef CONFIG_SELFMOD_TIMER
	34	#include <asm/selfmod.h>
	35	#define TIMER_BASE BARRIER_BASE_ADDR
	36	#else
	37	static unsigned int timer_baseaddr;
	38	#define TIMER_BASE timer_baseaddr
	39	#endif
	40
ccea0e6e MS	41	unsigned int freq_div_hz;
	42	unsigned int timer_clock_freq;
	43
eedbdab9 MS	44	#define TCSR0 (0x00)
	45	#define TLR0 (0x04)
	46	#define TCR0 (0x08)
	47	#define TCSR1 (0x10)
	48	#define TLR1 (0x14)
	49	#define TCR1 (0x18)
	50
	51	#define TCSR_MDT (1<<0)
	52	#define TCSR_UDT (1<<1)
	53	#define TCSR_GENT (1<<2)
	54	#define TCSR_CAPT (1<<3)
	55	#define TCSR_ARHT (1<<4)
	56	#define TCSR_LOAD (1<<5)
	57	#define TCSR_ENIT (1<<6)
	58	#define TCSR_ENT (1<<7)
	59	#define TCSR_TINT (1<<8)
	60	#define TCSR_PWMA (1<<9)
	61	#define TCSR_ENALL (1<<10)
	62
	63	static inline void microblaze_timer0_stop(void)
	64	{
	65	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT);
	66	}
	67
	68	static inline void microblaze_timer0_start_periodic(unsigned long load_val)
	69	{
	70	if (!load_val)
	71	load_val = 1;
	72	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
	73
	74	/* load the initial value */
	75	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
	76
	77	/* see timer data sheet for detail
	78	* !ENALL - don't enable 'em all
	79	* !PWMA - disable pwm
	80	* TINT - clear interrupt status
	81	* ENT- enable timer itself
	82	* EINT - enable interrupt
	83	* !LOAD - clear the bit to let go
	84	* ARHT - auto reload
	85	* !CAPT - no external trigger
	86	* !GENT - no external signal
	87	* UDT - set the timer as down counter
	88	* !MDT0 - generate mode
	89	*/
	90	out_be32(TIMER_BASE + TCSR0,
	91	TCSR_TINT\|TCSR_ENIT\|TCSR_ENT\|TCSR_ARHT\|TCSR_UDT);
	92	}
	93
	94	static inline void microblaze_timer0_start_oneshot(unsigned long load_val)
	95	{
	96	if (!load_val)
	97	load_val = 1;
	98	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
	99
	100	/* load the initial value */
	101	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
	102
	103	out_be32(TIMER_BASE + TCSR0,
	104	TCSR_TINT\|TCSR_ENIT\|TCSR_ENT\|TCSR_ARHT\|TCSR_UDT);
	105	}
	106
	107	static int microblaze_timer_set_next_event(unsigned long delta,
108	struct clock_event_device *dev)
109	{
110	pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
111	microblaze_timer0_start_oneshot(delta);
112	return 0;
113	}
114
115	static void microblaze_timer_set_mode(enum clock_event_mode mode,
116	struct clock_event_device *evt)
117	{
118	switch (mode) {
119	case CLOCK_EVT_MODE_PERIODIC:
120	printk(KERN_INFO "%s: periodic\n", __func__);
ccea0e6e	121	microblaze_timer0_start_periodic(freq_div_hz);
eedbdab9 MS	122	break;
	123	case CLOCK_EVT_MODE_ONESHOT:
	124	printk(KERN_INFO "%s: oneshot\n", __func__);
	125	break;
	126	case CLOCK_EVT_MODE_UNUSED:
	127	printk(KERN_INFO "%s: unused\n", __func__);
	128	break;
	129	case CLOCK_EVT_MODE_SHUTDOWN:
	130	printk(KERN_INFO "%s: shutdown\n", __func__);
	131	microblaze_timer0_stop();
	132	break;
	133	case CLOCK_EVT_MODE_RESUME:
	134	printk(KERN_INFO "%s: resume\n", __func__);
	135	break;
	136	}
	137	}
	138
	139	static struct clock_event_device clockevent_microblaze_timer = {
	140	.name = "microblaze_clockevent",
	141	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,
c8f77436	142	.shift = 8,
eedbdab9 MS	143	.rating = 300,
	144	.set_next_event = microblaze_timer_set_next_event,
	145	.set_mode = microblaze_timer_set_mode,
	146	};
	147
	148	static inline void timer_ack(void)
	149	{
	150	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0));
	151	}
	152
	153	static irqreturn_t timer_interrupt(int irq, void *dev_id)
	154	{
	155	struct clock_event_device *evt = &clockevent_microblaze_timer;
	156	#ifdef CONFIG_HEART_BEAT
	157	heartbeat();
	158	#endif
	159	timer_ack();
	160	evt->event_handler(evt);
	161	return IRQ_HANDLED;
	162	}
	163
	164	static struct irqaction timer_irqaction = {
	165	.handler = timer_interrupt,
	166	.flags = IRQF_DISABLED \| IRQF_TIMER,
	167	.name = "timer",
	168	.dev_id = &clockevent_microblaze_timer,
	169	};
	170
	171	static __init void microblaze_clockevent_init(void)
	172	{
	173	clockevent_microblaze_timer.mult =
ccea0e6e	174	div_sc(timer_clock_freq, NSEC_PER_SEC,
eedbdab9 MS	175	clockevent_microblaze_timer.shift);
	176	clockevent_microblaze_timer.max_delta_ns =
	177	clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);
	178	clockevent_microblaze_timer.min_delta_ns =
	179	clockevent_delta2ns(1, &clockevent_microblaze_timer);
	180	clockevent_microblaze_timer.cpumask = cpumask_of(0);
	181	clockevents_register_device(&clockevent_microblaze_timer);
	182	}
	183
f57f2fe2	184	static cycle_t microblaze_read(struct clocksource *cs)
eedbdab9 MS	185	{
	186	/* reading actual value of timer 1 */
	187	return (cycle_t) (in_be32(TIMER_BASE + TCR1));
	188	}
	189
519e9f41 MS	190	static struct timecounter microblaze_tc = {
	191	.cc = NULL,
	192	};
	193
	194	static cycle_t microblaze_cc_read(const struct cyclecounter *cc)
	195	{
	196	return microblaze_read(NULL);
	197	}
	198
	199	static struct cyclecounter microblaze_cc = {
	200	.read = microblaze_cc_read,
	201	.mask = CLOCKSOURCE_MASK(32),
c8f77436	202	.shift = 8,
519e9f41 MS	203	};
	204
	205	int __init init_microblaze_timecounter(void)
	206	{
ccea0e6e	207	microblaze_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
519e9f41 MS	208	microblaze_cc.shift);
	209
	210	timecounter_init(&microblaze_tc, &microblaze_cc, sched_clock());
	211
	212	return 0;
	213	}
	214
eedbdab9 MS	215	static struct clocksource clocksource_microblaze = {
	216	.name = "microblaze_clocksource",
	217	.rating = 300,
	218	.read = microblaze_read,
	219	.mask = CLOCKSOURCE_MASK(32),
c8f77436	220	.shift = 8, /* I can shift it */
eedbdab9 MS	221	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	222	};
	223
	224	static int __init microblaze_clocksource_init(void)
	225	{
	226	clocksource_microblaze.mult =
ccea0e6e	227	clocksource_hz2mult(timer_clock_freq,
eedbdab9 MS	228	clocksource_microblaze.shift);
	229	if (clocksource_register(&clocksource_microblaze))
	230	panic("failed to register clocksource");
	231
	232	/* stop timer1 */
	233	out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);
	234	/* start timer1 - up counting without interrupt */
	235	out_be32(TIMER_BASE + TCSR1, TCSR_TINT\|TCSR_ENT\|TCSR_ARHT);
519e9f41 MS	236
	237	/* register timecounter - for ftrace support */
	238	init_microblaze_timecounter();
eedbdab9 MS	239	return 0;
	240	}
	241
6f34b08f MS	242	/*
	243	* We have to protect accesses before timer initialization
	244	* and return 0 for sched_clock function below.
	245	*/
	246	static int timer_initialized;
	247
eedbdab9 MS	248	void __init time_init(void)
	249	{
	250	u32 irq, i = 0;
	251	u32 timer_num = 1;
	252	struct device_node *timer = NULL;
ccea0e6e	253	const void *prop;
eedbdab9 MS	254	#ifdef CONFIG_SELFMOD_TIMER
	255	unsigned int timer_baseaddr = 0;
	256	int arr_func[] = {
	257	(int)&microblaze_read,
	258	(int)&timer_interrupt,
	259	(int)&microblaze_clocksource_init,
	260	(int)&microblaze_timer_set_mode,
	261	(int)&microblaze_timer_set_next_event,
	262	0
	263	};
	264	#endif
92ee8bd4 JP	265	const char * const timer_list[] = {
92ee8bd4 JP	266	"xlnx,xps-timer-1.00.a",
92ee8bd4 JP	267	NULL
92ee8bd4 JP	268	};
eedbdab9 MS	269
	270	for (i = 0; timer_list[i] != NULL; i++) {
	271	timer = of_find_compatible_node(NULL, NULL, timer_list[i]);
	272	if (timer)
	273	break;
	274	}
892ee92b	275	BUG_ON(!timer);
eedbdab9	276
02b08045	277	timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL));
eedbdab9	278	timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
02b08045 MS	279	irq = be32_to_cpup(of_get_property(timer, "interrupts", NULL));
	280	timer_num = be32_to_cpup(of_get_property(timer,
	281	"xlnx,one-timer-only", NULL));
eedbdab9	282	if (timer_num) {
69717607	283	eprintk(KERN_EMERG "Please enable two timers in HW\n");
eedbdab9 MS	284	BUG();
	285	}
	286
	287	#ifdef CONFIG_SELFMOD_TIMER
	288	selfmod_function((int *) arr_func, timer_baseaddr);
	289	#endif
	290	printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
	291	timer_list[i], timer_baseaddr, irq);
	292
ccea0e6e MS	293	/* If there is clock-frequency property than use it */
	294	prop = of_get_property(timer, "clock-frequency", NULL);
	295	if (prop)
	296	timer_clock_freq = be32_to_cpup(prop);
	297	else
	298	timer_clock_freq = cpuinfo.cpu_clock_freq;
	299
	300	freq_div_hz = timer_clock_freq / HZ;
eedbdab9 MS	301
	302	setup_irq(irq, &timer_irqaction);
	303	#ifdef CONFIG_HEART_BEAT
	304	setup_heartbeat();
	305	#endif
	306	microblaze_clocksource_init();
	307	microblaze_clockevent_init();
6f34b08f MS	308	timer_initialized = 1;
	309	}
	310
	311	unsigned long long notrace sched_clock(void)
	312	{
	313	if (timer_initialized) {
	314	struct clocksource *cs = &clocksource_microblaze;
c8f77436	315	cycle_t cyc = cnt32_to_63(cs->read(NULL));
6f34b08f MS	316	return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
	317	}
	318	return 0;
eedbdab9	319	}