projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 3f50425c MS |
1 | /* |
| 2 | * Miscellaneous low-level MMU functions. | |
| 3 | * | |
| 4 | * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> | |
| 5 | * Copyright (C) 2008-2009 PetaLogix | |
| 6 | * Copyright (C) 2007 Xilinx, Inc. All rights reserved. | |
| 7 | * | |
| 8 | * Derived from arch/ppc/kernel/misc.S | |
| 9 | * | |
| 10 | * This file is subject to the terms and conditions of the GNU General | |
| 11 | * Public License. See the file COPYING in the main directory of this | |
| 12 | * archive for more details. | |
| 13 | */ | |
| 14 | ||
| 15 | #include <linux/linkage.h> | |
| 16 | #include <linux/sys.h> | |
| 17 | #include <asm/unistd.h> | |
| 18 | #include <linux/errno.h> | |
| 19 | #include <asm/mmu.h> | |
| 20 | #include <asm/page.h> | |
| 21 | ||
| 22 | .text | |
| 23 | /* | |
| 24 | * Flush MMU TLB | |
| 25 | * | |
| 26 | * We avoid flushing the pinned 0, 1 and possibly 2 entries. | |
| 27 | */ | |
| 28 | .globl _tlbia; | |
| 29 | .align 4; | |
| 30 | _tlbia: | |
| 31 | addik r12, r0, 63 /* flush all entries (63 - 3) */ | |
| 32 | /* isync */ | |
| 33 | _tlbia_1: | |
| 34 | mts rtlbx, r12 | |
| 35 | nop | |
| 36 | mts rtlbhi, r0 /* flush: ensure V is clear */ | |
| 37 | nop | |
| 38 | addik r11, r12, -2 | |
| 39 | bneid r11, _tlbia_1 /* loop for all entries */ | |
| 40 | addik r12, r12, -1 | |
| 41 | /* sync */ | |
| 42 | rtsd r15, 8 | |
| 43 | nop | |
| 44 | ||
| 45 | /* | |
| 46 | * Flush MMU TLB for a particular address (in r5) | |
| 47 | */ | |
| 48 | .globl _tlbie; | |
| 49 | .align 4; | |
| 50 | _tlbie: | |
| 51 | mts rtlbsx, r5 /* look up the address in TLB */ | |
| 52 | nop | |
| 53 | mfs r12, rtlbx /* Retrieve index */ | |
| 54 | nop | |
| 55 | blti r12, _tlbie_1 /* Check if found */ | |
| 56 | mts rtlbhi, r0 /* flush: ensure V is clear */ | |
| 57 | nop | |
| 58 | _tlbie_1: | |
| 59 | rtsd r15, 8 | |
| 60 | nop | |
| 61 | ||
| 62 | /* | |
| 63 | * Allocate TLB entry for early console | |
| 64 | */ | |
| 65 | .globl early_console_reg_tlb_alloc; | |
| 66 | .align 4; | |
| 67 | early_console_reg_tlb_alloc: | |
| 68 | /* | |
| 69 | * Load a TLB entry for the UART, so that microblaze_progress() can use | |
| 70 | * the UARTs nice and early. We use a 4k real==virtual mapping. | |
| 71 | */ | |
| fee3c55d | 72 | ori r4, r0, 63 |
| 3f50425c MS |
73 | mts rtlbx, r4 /* TLB slot 2 */ |
| 74 | ||
| 75 | or r4,r5,r0 | |
| 76 | andi r4,r4,0xfffff000 | |
| 77 | ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G) | |
| 78 | ||
| 79 | andi r5,r5,0xfffff000 | |
| 80 | ori r5,r5,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) | |
| 81 | ||
| 82 | mts rtlblo,r4 /* Load the data portion of the entry */ | |
| 83 | nop | |
| 84 | mts rtlbhi,r5 /* Load the tag portion of the entry */ | |
| 85 | nop | |
| 86 | rtsd r15, 8 | |
| 87 | nop | |
| 88 | ||
| 89 | /* | |
| 90 | * Copy a whole page (4096 bytes). | |
| 91 | */ | |
| 92 | #define COPY_16_BYTES \ | |
| 93 | lwi r7, r6, 0; \ | |
| 94 | lwi r8, r6, 4; \ | |
| 95 | lwi r9, r6, 8; \ | |
| 96 | lwi r10, r6, 12; \ | |
| 97 | swi r7, r5, 0; \ | |
| 98 | swi r8, r5, 4; \ | |
| 99 | swi r9, r5, 8; \ | |
| 100 | swi r10, r5, 12 | |
| 101 | ||
| 102 | ||
| 103 | /* FIXME DCACHE_LINE_BYTES (CONFIG_XILINX_MICROBLAZE0_DCACHE_LINE_LEN * 4)*/ | |
| 104 | #define DCACHE_LINE_BYTES (4 * 4) | |
| 105 | ||
| 106 | .globl copy_page; | |
| 107 | .align 4; | |
| 108 | copy_page: | |
| 109 | ori r11, r0, (PAGE_SIZE/DCACHE_LINE_BYTES) - 1 | |
| 110 | _copy_page_loop: | |
| 111 | COPY_16_BYTES | |
| 112 | #if DCACHE_LINE_BYTES >= 32 | |
| 113 | COPY_16_BYTES | |
| 114 | #endif | |
| 115 | addik r6, r6, DCACHE_LINE_BYTES | |
| 116 | addik r5, r5, DCACHE_LINE_BYTES | |
| 117 | bneid r11, _copy_page_loop | |
| 118 | addik r11, r11, -1 | |
| 119 | rtsd r15, 8 | |
| 120 | nop |