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eedbdab9 | 1 | /* |
968674bd MS |
2 | * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> |
3 | * Copyright (C) 2012-2013 Xilinx, Inc. | |
eedbdab9 MS |
4 | * Copyright (C) 2007-2009 PetaLogix |
5 | * Copyright (C) 2006 Atmark Techno, Inc. | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
2462bacd | 13 | #include <linux/irqdomain.h> |
eedbdab9 MS |
14 | #include <linux/irq.h> |
15 | #include <asm/page.h> | |
16 | #include <linux/io.h> | |
892ee92b | 17 | #include <linux/bug.h> |
eedbdab9 MS |
18 | |
19 | #include <asm/prom.h> | |
20 | #include <asm/irq.h> | |
21 | ||
eedbdab9 | 22 | static unsigned int intc_baseaddr; |
eedbdab9 | 23 | |
eedbdab9 MS |
24 | /* No one else should require these constants, so define them locally here. */ |
25 | #define ISR 0x00 /* Interrupt Status Register */ | |
26 | #define IPR 0x04 /* Interrupt Pending Register */ | |
27 | #define IER 0x08 /* Interrupt Enable Register */ | |
28 | #define IAR 0x0c /* Interrupt Acknowledge Register */ | |
29 | #define SIE 0x10 /* Set Interrupt Enable bits */ | |
30 | #define CIE 0x14 /* Clear Interrupt Enable bits */ | |
31 | #define IVR 0x18 /* Interrupt Vector Register */ | |
32 | #define MER 0x1c /* Master Enable Register */ | |
33 | ||
34 | #define MER_ME (1<<0) | |
35 | #define MER_HIE (1<<1) | |
36 | ||
6f205a4c | 37 | static void intc_enable_or_unmask(struct irq_data *d) |
eedbdab9 | 38 | { |
6c7a2676 MS |
39 | unsigned long mask = 1 << d->hwirq; |
40 | ||
41 | pr_debug("enable_or_unmask: %ld\n", d->hwirq); | |
33d9ff59 | 42 | |
43 | /* ack level irqs because they can't be acked during | |
44 | * ack function since the handle_level_irq function | |
45 | * acks the irq before calling the interrupt handler | |
46 | */ | |
4adc192e | 47 | if (irqd_is_level_type(d)) |
9e77dab6 | 48 | out_be32(intc_baseaddr + IAR, mask); |
7958a689 | 49 | |
9e77dab6 | 50 | out_be32(intc_baseaddr + SIE, mask); |
eedbdab9 MS |
51 | } |
52 | ||
6f205a4c | 53 | static void intc_disable_or_mask(struct irq_data *d) |
eedbdab9 | 54 | { |
6c7a2676 | 55 | pr_debug("disable: %ld\n", d->hwirq); |
9e77dab6 | 56 | out_be32(intc_baseaddr + CIE, 1 << d->hwirq); |
eedbdab9 MS |
57 | } |
58 | ||
6f205a4c | 59 | static void intc_ack(struct irq_data *d) |
eedbdab9 | 60 | { |
6c7a2676 | 61 | pr_debug("ack: %ld\n", d->hwirq); |
9e77dab6 | 62 | out_be32(intc_baseaddr + IAR, 1 << d->hwirq); |
eedbdab9 MS |
63 | } |
64 | ||
6f205a4c | 65 | static void intc_mask_ack(struct irq_data *d) |
eedbdab9 | 66 | { |
6c7a2676 MS |
67 | unsigned long mask = 1 << d->hwirq; |
68 | ||
69 | pr_debug("disable_and_ack: %ld\n", d->hwirq); | |
9e77dab6 MS |
70 | out_be32(intc_baseaddr + CIE, mask); |
71 | out_be32(intc_baseaddr + IAR, mask); | |
eedbdab9 MS |
72 | } |
73 | ||
eedbdab9 MS |
74 | static struct irq_chip intc_dev = { |
75 | .name = "Xilinx INTC", | |
6f205a4c TG |
76 | .irq_unmask = intc_enable_or_unmask, |
77 | .irq_mask = intc_disable_or_mask, | |
78 | .irq_ack = intc_ack, | |
79 | .irq_mask_ack = intc_mask_ack, | |
eedbdab9 MS |
80 | }; |
81 | ||
2462bacd GL |
82 | static struct irq_domain *root_domain; |
83 | ||
84 | unsigned int get_irq(void) | |
eedbdab9 | 85 | { |
2462bacd | 86 | unsigned int hwirq, irq = -1; |
eedbdab9 | 87 | |
9e77dab6 | 88 | hwirq = in_be32(intc_baseaddr + IVR); |
2462bacd GL |
89 | if (hwirq != -1U) |
90 | irq = irq_find_mapping(root_domain, hwirq); | |
91 | ||
92 | pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq); | |
eedbdab9 MS |
93 | |
94 | return irq; | |
95 | } | |
96 | ||
c0d997fb | 97 | static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) |
2462bacd GL |
98 | { |
99 | u32 intr_mask = (u32)d->host_data; | |
100 | ||
101 | if (intr_mask & (1 << hw)) { | |
102 | irq_set_chip_and_handler_name(irq, &intc_dev, | |
103 | handle_edge_irq, "edge"); | |
104 | irq_clear_status_flags(irq, IRQ_LEVEL); | |
105 | } else { | |
106 | irq_set_chip_and_handler_name(irq, &intc_dev, | |
107 | handle_level_irq, "level"); | |
108 | irq_set_status_flags(irq, IRQ_LEVEL); | |
109 | } | |
110 | return 0; | |
111 | } | |
112 | ||
113 | static const struct irq_domain_ops xintc_irq_domain_ops = { | |
114 | .xlate = irq_domain_xlate_onetwocell, | |
115 | .map = xintc_map, | |
116 | }; | |
117 | ||
eedbdab9 MS |
118 | void __init init_IRQ(void) |
119 | { | |
2462bacd | 120 | u32 nr_irq, intr_mask; |
eedbdab9 | 121 | struct device_node *intc = NULL; |
9e77dab6 | 122 | |
5a26cd69 | 123 | intc = of_find_compatible_node(NULL, NULL, "xlnx,xps-intc-1.00.a"); |
892ee92b | 124 | BUG_ON(!intc); |
eedbdab9 | 125 | |
6c7a2676 | 126 | intc_baseaddr = be32_to_cpup(of_get_property(intc, "reg", NULL)); |
eedbdab9 | 127 | intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE); |
02b08045 MS |
128 | nr_irq = be32_to_cpup(of_get_property(intc, |
129 | "xlnx,num-intr-inputs", NULL)); | |
eedbdab9 | 130 | |
2ecb899b MS |
131 | intr_mask = |
132 | be32_to_cpup(of_get_property(intc, "xlnx,kind-of-intr", NULL)); | |
133 | if (intr_mask > (u32)((1ULL << nr_irq) - 1)) | |
6bd55f0b | 134 | pr_info(" ERROR: Mismatch in kind-of-intr param\n"); |
eedbdab9 | 135 | |
6bd55f0b | 136 | pr_info("%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n", |
cc5647a6 | 137 | intc->name, intc_baseaddr, nr_irq, intr_mask); |
eedbdab9 MS |
138 | |
139 | /* | |
140 | * Disable all external interrupts until they are | |
141 | * explicity requested. | |
142 | */ | |
143 | out_be32(intc_baseaddr + IER, 0); | |
144 | ||
145 | /* Acknowledge any pending interrupts just in case. */ | |
146 | out_be32(intc_baseaddr + IAR, 0xffffffff); | |
147 | ||
148 | /* Turn on the Master Enable. */ | |
149 | out_be32(intc_baseaddr + MER, MER_HIE | MER_ME); | |
150 | ||
2462bacd GL |
151 | /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm |
152 | * lazy and Michal can clean it up to something nicer when he tests | |
153 | * and commits this patch. ~~gcl */ | |
154 | root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops, | |
155 | (void *)intr_mask); | |
7c2c8513 DC |
156 | |
157 | irq_set_default_host(root_domain); | |
eedbdab9 | 158 | } |