Commit | Line | Data |
---|---|---|
eedbdab9 | 1 | /* |
968674bd MS |
2 | * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> |
3 | * Copyright (C) 2012-2013 Xilinx, Inc. | |
eedbdab9 MS |
4 | * Copyright (C) 2007-2009 PetaLogix |
5 | * Copyright (C) 2006 Atmark Techno, Inc. | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
2462bacd | 13 | #include <linux/irqdomain.h> |
eedbdab9 MS |
14 | #include <linux/irq.h> |
15 | #include <asm/page.h> | |
16 | #include <linux/io.h> | |
892ee92b | 17 | #include <linux/bug.h> |
eedbdab9 MS |
18 | |
19 | #include <asm/prom.h> | |
20 | #include <asm/irq.h> | |
8a9e90a1 | 21 | #include "../../drivers/irqchip/irqchip.h" |
eedbdab9 | 22 | |
eedbdab9 | 23 | static unsigned int intc_baseaddr; |
eedbdab9 | 24 | |
eedbdab9 MS |
25 | /* No one else should require these constants, so define them locally here. */ |
26 | #define ISR 0x00 /* Interrupt Status Register */ | |
27 | #define IPR 0x04 /* Interrupt Pending Register */ | |
28 | #define IER 0x08 /* Interrupt Enable Register */ | |
29 | #define IAR 0x0c /* Interrupt Acknowledge Register */ | |
30 | #define SIE 0x10 /* Set Interrupt Enable bits */ | |
31 | #define CIE 0x14 /* Clear Interrupt Enable bits */ | |
32 | #define IVR 0x18 /* Interrupt Vector Register */ | |
33 | #define MER 0x1c /* Master Enable Register */ | |
34 | ||
35 | #define MER_ME (1<<0) | |
36 | #define MER_HIE (1<<1) | |
37 | ||
6f205a4c | 38 | static void intc_enable_or_unmask(struct irq_data *d) |
eedbdab9 | 39 | { |
6c7a2676 MS |
40 | unsigned long mask = 1 << d->hwirq; |
41 | ||
42 | pr_debug("enable_or_unmask: %ld\n", d->hwirq); | |
33d9ff59 | 43 | |
44 | /* ack level irqs because they can't be acked during | |
45 | * ack function since the handle_level_irq function | |
46 | * acks the irq before calling the interrupt handler | |
47 | */ | |
4adc192e | 48 | if (irqd_is_level_type(d)) |
9e77dab6 | 49 | out_be32(intc_baseaddr + IAR, mask); |
7958a689 | 50 | |
9e77dab6 | 51 | out_be32(intc_baseaddr + SIE, mask); |
eedbdab9 MS |
52 | } |
53 | ||
6f205a4c | 54 | static void intc_disable_or_mask(struct irq_data *d) |
eedbdab9 | 55 | { |
6c7a2676 | 56 | pr_debug("disable: %ld\n", d->hwirq); |
9e77dab6 | 57 | out_be32(intc_baseaddr + CIE, 1 << d->hwirq); |
eedbdab9 MS |
58 | } |
59 | ||
6f205a4c | 60 | static void intc_ack(struct irq_data *d) |
eedbdab9 | 61 | { |
6c7a2676 | 62 | pr_debug("ack: %ld\n", d->hwirq); |
9e77dab6 | 63 | out_be32(intc_baseaddr + IAR, 1 << d->hwirq); |
eedbdab9 MS |
64 | } |
65 | ||
6f205a4c | 66 | static void intc_mask_ack(struct irq_data *d) |
eedbdab9 | 67 | { |
6c7a2676 MS |
68 | unsigned long mask = 1 << d->hwirq; |
69 | ||
70 | pr_debug("disable_and_ack: %ld\n", d->hwirq); | |
9e77dab6 MS |
71 | out_be32(intc_baseaddr + CIE, mask); |
72 | out_be32(intc_baseaddr + IAR, mask); | |
eedbdab9 MS |
73 | } |
74 | ||
eedbdab9 MS |
75 | static struct irq_chip intc_dev = { |
76 | .name = "Xilinx INTC", | |
6f205a4c TG |
77 | .irq_unmask = intc_enable_or_unmask, |
78 | .irq_mask = intc_disable_or_mask, | |
79 | .irq_ack = intc_ack, | |
80 | .irq_mask_ack = intc_mask_ack, | |
eedbdab9 MS |
81 | }; |
82 | ||
2462bacd GL |
83 | static struct irq_domain *root_domain; |
84 | ||
85 | unsigned int get_irq(void) | |
eedbdab9 | 86 | { |
2462bacd | 87 | unsigned int hwirq, irq = -1; |
eedbdab9 | 88 | |
9e77dab6 | 89 | hwirq = in_be32(intc_baseaddr + IVR); |
2462bacd GL |
90 | if (hwirq != -1U) |
91 | irq = irq_find_mapping(root_domain, hwirq); | |
92 | ||
93 | pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq); | |
eedbdab9 MS |
94 | |
95 | return irq; | |
96 | } | |
97 | ||
c0d997fb | 98 | static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) |
2462bacd GL |
99 | { |
100 | u32 intr_mask = (u32)d->host_data; | |
101 | ||
102 | if (intr_mask & (1 << hw)) { | |
103 | irq_set_chip_and_handler_name(irq, &intc_dev, | |
104 | handle_edge_irq, "edge"); | |
105 | irq_clear_status_flags(irq, IRQ_LEVEL); | |
106 | } else { | |
107 | irq_set_chip_and_handler_name(irq, &intc_dev, | |
108 | handle_level_irq, "level"); | |
109 | irq_set_status_flags(irq, IRQ_LEVEL); | |
110 | } | |
111 | return 0; | |
112 | } | |
113 | ||
114 | static const struct irq_domain_ops xintc_irq_domain_ops = { | |
115 | .xlate = irq_domain_xlate_onetwocell, | |
116 | .map = xintc_map, | |
117 | }; | |
118 | ||
8a9e90a1 MS |
119 | static int __init xilinx_intc_of_init(struct device_node *intc, |
120 | struct device_node *parent) | |
eedbdab9 | 121 | { |
2462bacd | 122 | u32 nr_irq, intr_mask; |
eedbdab9 | 123 | |
6c7a2676 | 124 | intc_baseaddr = be32_to_cpup(of_get_property(intc, "reg", NULL)); |
eedbdab9 | 125 | intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE); |
02b08045 MS |
126 | nr_irq = be32_to_cpup(of_get_property(intc, |
127 | "xlnx,num-intr-inputs", NULL)); | |
eedbdab9 | 128 | |
2ecb899b MS |
129 | intr_mask = |
130 | be32_to_cpup(of_get_property(intc, "xlnx,kind-of-intr", NULL)); | |
131 | if (intr_mask > (u32)((1ULL << nr_irq) - 1)) | |
6bd55f0b | 132 | pr_info(" ERROR: Mismatch in kind-of-intr param\n"); |
eedbdab9 | 133 | |
6bd55f0b | 134 | pr_info("%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n", |
cc5647a6 | 135 | intc->name, intc_baseaddr, nr_irq, intr_mask); |
eedbdab9 MS |
136 | |
137 | /* | |
138 | * Disable all external interrupts until they are | |
139 | * explicity requested. | |
140 | */ | |
141 | out_be32(intc_baseaddr + IER, 0); | |
142 | ||
143 | /* Acknowledge any pending interrupts just in case. */ | |
144 | out_be32(intc_baseaddr + IAR, 0xffffffff); | |
145 | ||
146 | /* Turn on the Master Enable. */ | |
147 | out_be32(intc_baseaddr + MER, MER_HIE | MER_ME); | |
148 | ||
2462bacd GL |
149 | /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm |
150 | * lazy and Michal can clean it up to something nicer when he tests | |
151 | * and commits this patch. ~~gcl */ | |
152 | root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops, | |
153 | (void *)intr_mask); | |
7c2c8513 DC |
154 | |
155 | irq_set_default_host(root_domain); | |
8a9e90a1 MS |
156 | |
157 | return 0; | |
eedbdab9 | 158 | } |
8a9e90a1 MS |
159 | |
160 | IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init); |