[linux-block.git] / arch / microblaze / kernel / intc.c

/*
 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
 * Copyright (C) 2007-2009 PetaLogix
 * Copyright (C) 2006 Atmark Techno, Inc.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/init.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <asm/page.h>
#include <linux/io.h>
#include <linux/bug.h>

#include <asm/prom.h>
#include <asm/irq.h>

static unsigned int intc_baseaddr;

/* No one else should require these constants, so define them locally here. */
#define ISR 0x00			/* Interrupt Status Register */
#define IPR 0x04			/* Interrupt Pending Register */
#define IER 0x08			/* Interrupt Enable Register */
#define IAR 0x0c			/* Interrupt Acknowledge Register */
#define SIE 0x10			/* Set Interrupt Enable bits */
#define CIE 0x14			/* Clear Interrupt Enable bits */
#define IVR 0x18			/* Interrupt Vector Register */
#define MER 0x1c			/* Master Enable Register */

#define MER_ME (1<<0)
#define MER_HIE (1<<1)

static void intc_enable_or_unmask(struct irq_data *d)
{
	unsigned long mask = 1 << d->hwirq;

	pr_debug("enable_or_unmask: %ld\n", d->hwirq);

	/* ack level irqs because they can't be acked during
	 * ack function since the handle_level_irq function
	 * acks the irq before calling the interrupt handler
	 */
	if (irqd_is_level_type(d))
		out_be32(intc_baseaddr + IAR, mask);

	out_be32(intc_baseaddr + SIE, mask);
}

static void intc_disable_or_mask(struct irq_data *d)
{
	pr_debug("disable: %ld\n", d->hwirq);
	out_be32(intc_baseaddr + CIE, 1 << d->hwirq);
}

static void intc_ack(struct irq_data *d)
{
	pr_debug("ack: %ld\n", d->hwirq);
	out_be32(intc_baseaddr + IAR, 1 << d->hwirq);
}

static void intc_mask_ack(struct irq_data *d)
{
	unsigned long mask = 1 << d->hwirq;

	pr_debug("disable_and_ack: %ld\n", d->hwirq);
	out_be32(intc_baseaddr + CIE, mask);
	out_be32(intc_baseaddr + IAR, mask);
}

static struct irq_chip intc_dev = {
	.name = "Xilinx INTC",
	.irq_unmask = intc_enable_or_unmask,
	.irq_mask = intc_disable_or_mask,
	.irq_ack = intc_ack,
	.irq_mask_ack = intc_mask_ack,
};

static struct irq_domain *root_domain;

unsigned int get_irq(void)
{
	unsigned int hwirq, irq = -1;

	hwirq = in_be32(intc_baseaddr + IVR);
	if (hwirq != -1U)
		irq = irq_find_mapping(root_domain, hwirq);

	pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);

	return irq;
}

static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
{
	u32 intr_mask = (u32)d->host_data;

	if (intr_mask & (1 << hw)) {
		irq_set_chip_and_handler_name(irq, &intc_dev,
						handle_edge_irq, "edge");
		irq_clear_status_flags(irq, IRQ_LEVEL);
	} else {
		irq_set_chip_and_handler_name(irq, &intc_dev,
						handle_level_irq, "level");
		irq_set_status_flags(irq, IRQ_LEVEL);
	}
	return 0;
}

static const struct irq_domain_ops xintc_irq_domain_ops = {
	.xlate = irq_domain_xlate_onetwocell,
	.map = xintc_map,
};

void __init init_IRQ(void)
{
	u32 nr_irq, intr_mask;
	struct device_node *intc = NULL;

	intc = of_find_compatible_node(NULL, NULL, "xlnx,xps-intc-1.00.a");
	BUG_ON(!intc);

	intc_baseaddr = be32_to_cpup(of_get_property(intc, "reg", NULL));
	intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
	nr_irq = be32_to_cpup(of_get_property(intc,
						"xlnx,num-intr-inputs", NULL));

	intr_mask =
		be32_to_cpup(of_get_property(intc, "xlnx,kind-of-intr", NULL));
	if (intr_mask > (u32)((1ULL << nr_irq) - 1))
		pr_info(" ERROR: Mismatch in kind-of-intr param\n");

	pr_info("%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
		intc->name, intc_baseaddr, nr_irq, intr_mask);

	/*
	 * Disable all external interrupts until they are
	 * explicity requested.
	 */
	out_be32(intc_baseaddr + IER, 0);

	/* Acknowledge any pending interrupts just in case. */
	out_be32(intc_baseaddr + IAR, 0xffffffff);

	/* Turn on the Master Enable. */
	out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);

	/* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
	 * lazy and Michal can clean it up to something nicer when he tests
	 * and commits this patch.  ~~gcl */
	root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops,
							(void *)intr_mask);

	irq_set_default_host(root_domain);
}
Commit	Line	Data
eedbdab9 MS	1	/*
	2	* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
	3	* Copyright (C) 2007-2009 PetaLogix
	4	* Copyright (C) 2006 Atmark Techno, Inc.
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#include <linux/init.h>
2462bacd	12	#include <linux/irqdomain.h>
eedbdab9 MS	13	#include <linux/irq.h>
	14	#include <asm/page.h>
	15	#include <linux/io.h>
892ee92b	16	#include <linux/bug.h>
eedbdab9 MS	17
	18	#include <asm/prom.h>
	19	#include <asm/irq.h>
	20
eedbdab9	21	static unsigned int intc_baseaddr;
eedbdab9	22
eedbdab9 MS	23	/* No one else should require these constants, so define them locally here. */
	24	#define ISR 0x00 /* Interrupt Status Register */
	25	#define IPR 0x04 /* Interrupt Pending Register */
	26	#define IER 0x08 /* Interrupt Enable Register */
	27	#define IAR 0x0c /* Interrupt Acknowledge Register */
	28	#define SIE 0x10 /* Set Interrupt Enable bits */
	29	#define CIE 0x14 /* Clear Interrupt Enable bits */
	30	#define IVR 0x18 /* Interrupt Vector Register */
	31	#define MER 0x1c /* Master Enable Register */
	32
	33	#define MER_ME (1<<0)
	34	#define MER_HIE (1<<1)
	35
6f205a4c	36	static void intc_enable_or_unmask(struct irq_data *d)
eedbdab9	37	{
6c7a2676 MS	38	unsigned long mask = 1 << d->hwirq;
	39
	40	pr_debug("enable_or_unmask: %ld\n", d->hwirq);
33d9ff59	41
	42	/* ack level irqs because they can't be acked during
	43	* ack function since the handle_level_irq function
	44	* acks the irq before calling the interrupt handler
	45	*/
4adc192e	46	if (irqd_is_level_type(d))
9e77dab6	47	out_be32(intc_baseaddr + IAR, mask);
7958a689	48
9e77dab6	49	out_be32(intc_baseaddr + SIE, mask);
eedbdab9 MS	50	}
eedbdab9 MS	51
6f205a4c	52	static void intc_disable_or_mask(struct irq_data *d)
eedbdab9	53	{
6c7a2676	54	pr_debug("disable: %ld\n", d->hwirq);
9e77dab6	55	out_be32(intc_baseaddr + CIE, 1 << d->hwirq);
eedbdab9 MS	56	}
eedbdab9 MS	57
6f205a4c	58	static void intc_ack(struct irq_data *d)
eedbdab9	59	{
6c7a2676	60	pr_debug("ack: %ld\n", d->hwirq);
9e77dab6	61	out_be32(intc_baseaddr + IAR, 1 << d->hwirq);
eedbdab9 MS	62	}
eedbdab9 MS	63
6f205a4c	64	static void intc_mask_ack(struct irq_data *d)
eedbdab9	65	{
6c7a2676 MS	66	unsigned long mask = 1 << d->hwirq;
	67
	68	pr_debug("disable_and_ack: %ld\n", d->hwirq);
9e77dab6 MS	69	out_be32(intc_baseaddr + CIE, mask);
9e77dab6 MS	70	out_be32(intc_baseaddr + IAR, mask);
eedbdab9 MS	71	}
eedbdab9 MS	72
eedbdab9 MS	73	static struct irq_chip intc_dev = {
eedbdab9 MS	74	.name = "Xilinx INTC",
6f205a4c TG	75	.irq_unmask = intc_enable_or_unmask,
	76	.irq_mask = intc_disable_or_mask,
	77	.irq_ack = intc_ack,
	78	.irq_mask_ack = intc_mask_ack,
eedbdab9 MS	79	};
eedbdab9 MS	80
2462bacd GL	81	static struct irq_domain *root_domain;
	82
	83	unsigned int get_irq(void)
eedbdab9	84	{
2462bacd	85	unsigned int hwirq, irq = -1;
eedbdab9	86
9e77dab6	87	hwirq = in_be32(intc_baseaddr + IVR);
2462bacd GL	88	if (hwirq != -1U)
	89	irq = irq_find_mapping(root_domain, hwirq);
	90
	91	pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);
eedbdab9 MS	92
	93	return irq;
	94	}
	95
c0d997fb	96	static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
2462bacd GL	97	{
	98	u32 intr_mask = (u32)d->host_data;
	99
	100	if (intr_mask & (1 << hw)) {
	101	irq_set_chip_and_handler_name(irq, &intc_dev,
	102	handle_edge_irq, "edge");
	103	irq_clear_status_flags(irq, IRQ_LEVEL);
	104	} else {
	105	irq_set_chip_and_handler_name(irq, &intc_dev,
	106	handle_level_irq, "level");
	107	irq_set_status_flags(irq, IRQ_LEVEL);
	108	}
	109	return 0;
	110	}
	111
	112	static const struct irq_domain_ops xintc_irq_domain_ops = {
	113	.xlate = irq_domain_xlate_onetwocell,
	114	.map = xintc_map,
	115	};
	116
eedbdab9 MS	117	void __init init_IRQ(void)
eedbdab9 MS	118	{
2462bacd	119	u32 nr_irq, intr_mask;
eedbdab9	120	struct device_node *intc = NULL;
9e77dab6	121
5a26cd69	122	intc = of_find_compatible_node(NULL, NULL, "xlnx,xps-intc-1.00.a");
892ee92b	123	BUG_ON(!intc);
eedbdab9	124
6c7a2676	125	intc_baseaddr = be32_to_cpup(of_get_property(intc, "reg", NULL));
eedbdab9	126	intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
02b08045 MS	127	nr_irq = be32_to_cpup(of_get_property(intc,
02b08045 MS	128	"xlnx,num-intr-inputs", NULL));
eedbdab9	129
2ecb899b MS	130	intr_mask =
	131	be32_to_cpup(of_get_property(intc, "xlnx,kind-of-intr", NULL));
	132	if (intr_mask > (u32)((1ULL << nr_irq) - 1))
6bd55f0b	133	pr_info(" ERROR: Mismatch in kind-of-intr param\n");
eedbdab9	134
6bd55f0b	135	pr_info("%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
cc5647a6	136	intc->name, intc_baseaddr, nr_irq, intr_mask);
eedbdab9 MS	137
	138	/*
	139	* Disable all external interrupts until they are
	140	* explicity requested.
	141	*/
	142	out_be32(intc_baseaddr + IER, 0);
	143
	144	/* Acknowledge any pending interrupts just in case. */
	145	out_be32(intc_baseaddr + IAR, 0xffffffff);
	146
	147	/* Turn on the Master Enable. */
	148	out_be32(intc_baseaddr + MER, MER_HIE \| MER_ME);
	149
2462bacd GL	150	/* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
	151	* lazy and Michal can clean it up to something nicer when he tests
	152	* and commits this patch. ~~gcl */
	153	root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops,
	154	(void *)intr_mask);
7c2c8513 DC	155
7c2c8513 DC	156	irq_set_default_host(root_domain);
eedbdab9	157	}