[linux-2.6-block.git] / arch / microblaze / kernel / head.S

/*
 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
 * Copyright (C) 2007-2009 PetaLogix
 * Copyright (C) 2006 Atmark Techno, Inc.
 *
 * MMU code derived from arch/ppc/kernel/head_4xx.S:
 *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
 *      Initial PowerPC version.
 *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
 *      Rewritten for PReP
 *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
 *      Low-level exception handers, MMU support, and rewrite.
 *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
 *      PowerPC 8xx modifications.
 *    Copyright (c) 1998-1999 TiVo, Inc.
 *      PowerPC 403GCX modifications.
 *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
 *      PowerPC 403GCX/405GP modifications.
 *    Copyright 2000 MontaVista Software Inc.
 *	PPC405 modifications
 *      PowerPC 403GCX/405GP modifications.
 * 	Author: MontaVista Software, Inc.
 *         	frank_rowand@mvista.com or source@mvista.com
 * 	   	debbie_chu@mvista.com
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/thread_info.h>
#include <asm/page.h>
#include <linux/of_fdt.h>		/* for OF_DT_HEADER */

#ifdef CONFIG_MMU
#include <asm/setup.h> /* COMMAND_LINE_SIZE */
#include <asm/mmu.h>
#include <asm/processor.h>

.section .data
.global empty_zero_page
.align 12
empty_zero_page:
	.space	PAGE_SIZE
.global swapper_pg_dir
swapper_pg_dir:
	.space	PAGE_SIZE

#endif /* CONFIG_MMU */

.section .rodata
.align 4
endian_check:
	.word	1

	__HEAD
ENTRY(_start)
#if CONFIG_KERNEL_BASE_ADDR == 0
	brai	TOPHYS(real_start)
	.org	0x100
real_start:
#endif

	mfs	r1, rmsr
	andi	r1, r1, ~2
	mts	rmsr, r1
/*
 * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
 * if the msrclr instruction is not enabled. We use this to detect
 * if the opcode is available, by issuing msrclr and then testing the result.
 * r8 == 0 - msr instructions are implemented
 * r8 != 0 - msr instructions are not implemented
 */
	msrclr	r8, 0 /* clear nothing - just read msr for test */
	cmpu	r8, r8, r1 /* r1 must contain msr reg content */

/* r7 may point to an FDT, or there may be one linked in.
   if it's in r7, we've got to save it away ASAP.
   We ensure r7 points to a valid FDT, just in case the bootloader
   is broken or non-existent */
	beqi	r7, no_fdt_arg			/* NULL pointer?  don't copy */
/* Does r7 point to a valid FDT? Load HEADER magic number */
	/* Run time Big/Little endian platform */
	/* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */
	lbui	r11, r0, TOPHYS(endian_check)
	beqid	r11, big_endian /* DO NOT break delay stop dependency */
	lw	r11, r0, r7 /* Big endian load in delay slot */
	lwr	r11, r0, r7 /* Little endian load */
big_endian:
	rsubi	r11, r11, OF_DT_HEADER	/* Check FDT header */
	beqi	r11, _prepare_copy_fdt
	or	r7, r0, r0		/* clear R7 when not valid DTB */
	bnei	r11, no_fdt_arg			/* No - get out of here */
_prepare_copy_fdt:
	or	r11, r0, r0 /* incremment */
	ori	r4, r0, TOPHYS(_fdt_start)
	ori	r3, r0, (0x4000 - 4)
_copy_fdt:
	lw	r12, r7, r11 /* r12 = r7 + r11 */
	sw	r12, r4, r11 /* addr[r4 + r11] = r12 */
	addik	r11, r11, 4 /* increment counting */
	bgtid	r3, _copy_fdt /* loop for all entries */
	addik	r3, r3, -4 /* descrement loop */
no_fdt_arg:

#ifdef CONFIG_MMU

#ifndef CONFIG_CMDLINE_BOOL
/*
 * handling command line
 * copy command line to __init_end. There is space for storing command line.
 */
	or	r6, r0, r0		/* incremment */
	ori	r4, r0, __init_end	/* load address of command line */
	tophys(r4,r4)			/* convert to phys address */
	ori	r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
_copy_command_line:
	lbu	r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */
	sb	r2, r4, r6		/* addr[r4+r6]= r2*/
	addik	r6, r6, 1		/* increment counting */
	bgtid	r3, _copy_command_line	/* loop for all entries       */
	addik	r3, r3, -1		/* descrement loop */
	addik	r5, r4, 0		/* add new space for command line */
	tovirt(r5,r5)
#endif /* CONFIG_CMDLINE_BOOL */

#ifdef NOT_COMPILE
/* save bram context */
	or	r6, r0, r0				/* incremment */
	ori	r4, r0, TOPHYS(_bram_load_start)	/* save bram context */
	ori	r3, r0, (LMB_SIZE - 4)
_copy_bram:
	lw	r7, r0, r6		/* r7 = r0 + r6 */
	sw	r7, r4, r6		/* addr[r4 + r6] = r7*/
	addik	r6, r6, 4		/* increment counting */
	bgtid	r3, _copy_bram		/* loop for all entries */
	addik	r3, r3, -4		/* descrement loop */
#endif
	/* We have to turn on the MMU right away. */

	/*
	 * Set up the initial MMU state so we can do the first level of
	 * kernel initialization.  This maps the first 16 MBytes of memory 1:1
	 * virtual to physical.
	 */
	nop
	addik	r3, r0, MICROBLAZE_TLB_SIZE -1	/* Invalidate all TLB entries */
_invalidate:
	mts	rtlbx, r3
	mts	rtlbhi, r0			/* flush: ensure V is clear   */
	bgtid	r3, _invalidate		/* loop for all entries       */
	addik	r3, r3, -1
	/* sync */

	/* Setup the kernel PID */
	mts	rpid,r0			/* Load the kernel PID */
	nop
	bri	4

	/*
	 * We should still be executing code at physical address area
	 * RAM_BASEADDR at this point. However, kernel code is at
	 * a virtual address. So, set up a TLB mapping to cover this once
	 * translation is enabled.
	 */

	addik	r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
	tophys(r4,r3)			/* Load the kernel physical address */

	/*
	 * Configure and load two entries into TLB slots 0 and 1.
	 * In case we are pinning TLBs, these are reserved in by the
	 * other TLB functions.  If not reserving, then it doesn't
	 * matter where they are loaded.
	 */
	andi	r4,r4,0xfffffc00	/* Mask off the real page number */
	ori	r4,r4,(TLB_WR | TLB_EX)	/* Set the write and execute bits */

	andi	r3,r3,0xfffffc00	/* Mask off the effective page number */
	ori	r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))

	mts     rtlbx,r0		/* TLB slow 0 */

	mts	rtlblo,r4		/* Load the data portion of the entry */
	mts	rtlbhi,r3		/* Load the tag portion of the entry */

	addik	r4, r4, 0x01000000	/* Map next 16 M entries */
	addik	r3, r3, 0x01000000

	ori	r6,r0,1			/* TLB slot 1 */
	mts     rtlbx,r6

	mts	rtlblo,r4		/* Load the data portion of the entry */
	mts	rtlbhi,r3		/* Load the tag portion of the entry */

	/*
	 * Load a TLB entry for LMB, since we need access to
	 * the exception vectors, using a 4k real==virtual mapping.
	 */
	ori	r6,r0,3			/* TLB slot 3 */
	mts     rtlbx,r6

	ori	r4,r0,(TLB_WR | TLB_EX)
	ori	r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))

	mts	rtlblo,r4		/* Load the data portion of the entry */
	mts	rtlbhi,r3		/* Load the tag portion of the entry */

	/*
	 * We now have the lower 16 Meg of RAM mapped into TLB entries, and the
	 * caches ready to work.
	 */
turn_on_mmu:
	ori	r15,r0,start_here
	ori	r4,r0,MSR_KERNEL_VMS
	mts	rmsr,r4
	nop
	rted	r15,0			/* enables MMU */
	nop

start_here:
#endif /* CONFIG_MMU */

	/* Initialize small data anchors */
	addik	r13, r0, _KERNEL_SDA_BASE_
	addik	r2, r0, _KERNEL_SDA2_BASE_

	/* Initialize stack pointer */
	addik	r1, r0, init_thread_union + THREAD_SIZE - 4

	/* Initialize r31 with current task address */
	addik	r31, r0, init_task

	/*
	 * Call platform dependent initialize function.
	 * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
	 * the function.
	 */
	addik	r9, r0, machine_early_init
	brald	r15, r9
	nop

#ifndef CONFIG_MMU
	addik	r15, r0, machine_halt
	braid	start_kernel
	nop
#else
	/*
	 * Initialize the MMU.
	 */
	bralid	r15, mmu_init
	nop

	/* Go back to running unmapped so we can load up new values
	 * and change to using our exception vectors.
	 * On the MicroBlaze, all we invalidate the used TLB entries to clear
	 * the old 16M byte TLB mappings.
	 */
	ori	r15,r0,TOPHYS(kernel_load_context)
	ori	r4,r0,MSR_KERNEL
	mts	rmsr,r4
	nop
	bri	4
	rted	r15,0
	nop

	/* Load up the kernel context */
kernel_load_context:
	# Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away.
	ori	r5,r0,3
	mts     rtlbx,r5
	nop
	mts	rtlbhi,r0
	nop
	addi	r15, r0, machine_halt
	ori	r17, r0, start_kernel
	ori	r4, r0, MSR_KERNEL_VMS
	mts	rmsr, r4
	nop
	rted	r17, 0		/* enable MMU and jump to start_kernel */
	nop
#endif /* CONFIG_MMU */
Commit	Line	Data
6d5af1a3 MS	1	/*
	2	* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
	3	* Copyright (C) 2007-2009 PetaLogix
	4	* Copyright (C) 2006 Atmark Techno, Inc.
	5	*
5846cc60 MS	6	* MMU code derived from arch/ppc/kernel/head_4xx.S:
	7	* Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
	8	* Initial PowerPC version.
	9	* Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
	10	* Rewritten for PReP
	11	* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
	12	* Low-level exception handers, MMU support, and rewrite.
	13	* Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
	14	* PowerPC 8xx modifications.
	15	* Copyright (c) 1998-1999 TiVo, Inc.
	16	* PowerPC 403GCX modifications.
	17	* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
	18	* PowerPC 403GCX/405GP modifications.
	19	* Copyright 2000 MontaVista Software Inc.
	20	* PPC405 modifications
	21	* PowerPC 403GCX/405GP modifications.
	22	* Author: MontaVista Software, Inc.
	23	* frank_rowand@mvista.com or source@mvista.com
	24	* debbie_chu@mvista.com
	25	*
6d5af1a3 MS	26	* This file is subject to the terms and conditions of the GNU General Public
	27	* License. See the file "COPYING" in the main directory of this archive
	28	* for more details.
	29	*/
	30
7a0248e8	31	#include <linux/init.h>
6d5af1a3 MS	32	#include <linux/linkage.h>
	33	#include <asm/thread_info.h>
	34	#include <asm/page.h>
d8678b58	35	#include <linux/of_fdt.h> /* for OF_DT_HEADER */
6d5af1a3	36
5846cc60 MS	37	#ifdef CONFIG_MMU
	38	#include <asm/setup.h> /* COMMAND_LINE_SIZE */
	39	#include <asm/mmu.h>
	40	#include <asm/processor.h>
	41
495162df	42	.section .data
5846cc60 MS	43	.global empty_zero_page
	44	.align 12
	45	empty_zero_page:
ba9c4f88	46	.space PAGE_SIZE
5846cc60 MS	47	.global swapper_pg_dir
5846cc60 MS	48	swapper_pg_dir:
ba9c4f88	49	.space PAGE_SIZE
5846cc60 MS	50
	51	#endif /* CONFIG_MMU */
	52
495162df MS	53	.section .rodata
	54	.align 4
	55	endian_check:
	56	.word 1
	57
7a0248e8	58	__HEAD
6d5af1a3	59	ENTRY(_start)
ee68f174 MS	60	#if CONFIG_KERNEL_BASE_ADDR == 0
	61	brai TOPHYS(real_start)
	62	.org 0x100
	63	real_start:
	64	#endif
	65
6d5af1a3 MS	66	mfs r1, rmsr
	67	andi r1, r1, ~2
	68	mts rmsr, r1
2622434e	69	/*
0eb6aaf5 MS	70	* According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
	71	* if the msrclr instruction is not enabled. We use this to detect
	72	* if the opcode is available, by issuing msrclr and then testing the result.
	73	* r8 == 0 - msr instructions are implemented
	74	* r8 != 0 - msr instructions are not implemented
2622434e	75	*/
0eb6aaf5 MS	76	msrclr r8, 0 /* clear nothing - just read msr for test */
0eb6aaf5 MS	77	cmpu r8, r8, r1 /* r1 must contain msr reg content */
2622434e	78
909964ec JW	79	/* r7 may point to an FDT, or there may be one linked in.
	80	if it's in r7, we've got to save it away ASAP.
	81	We ensure r7 points to a valid FDT, just in case the bootloader
	82	is broken or non-existent */
	83	beqi r7, no_fdt_arg /* NULL pointer? don't copy */
026a2078 MS	84	/* Does r7 point to a valid FDT? Load HEADER magic number */
	85	/* Run time Big/Little endian platform */
	86	/* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */
495162df	87	lbui r11, r0, TOPHYS(endian_check)
026a2078 MS	88	beqid r11, big_endian /* DO NOT break delay stop dependency */
	89	lw r11, r0, r7 /* Big endian load in delay slot */
	90	lwr r11, r0, r7 /* Little endian load */
	91	big_endian:
	92	rsubi r11, r11, OF_DT_HEADER /* Check FDT header */
ea3fd146 MS	93	beqi r11, _prepare_copy_fdt
ea3fd146 MS	94	or r7, r0, r0 /* clear R7 when not valid DTB */
909964ec	95	bnei r11, no_fdt_arg /* No - get out of here */
ea3fd146	96	_prepare_copy_fdt:
6d5af1a3	97	or r11, r0, r0 /* incremment */
909964ec	98	ori r4, r0, TOPHYS(_fdt_start)
6d5af1a3 MS	99	ori r3, r0, (0x4000 - 4)
	100	_copy_fdt:
	101	lw r12, r7, r11 /* r12 = r7 + r11 */
	102	sw r12, r4, r11 /* addr[r4 + r11] = r12 */
	103	addik r11, r11, 4 /* increment counting */
	104	bgtid r3, _copy_fdt /* loop for all entries */
	105	addik r3, r3, -4 /* descrement loop */
	106	no_fdt_arg:
	107
5846cc60 MS	108	#ifdef CONFIG_MMU
	109
	110	#ifndef CONFIG_CMDLINE_BOOL
	111	/*
	112	* handling command line
	113	* copy command line to __init_end. There is space for storing command line.
	114	*/
	115	or r6, r0, r0 /* incremment */
	116	ori r4, r0, __init_end /* load address of command line */
	117	tophys(r4,r4) /* convert to phys address */
	118	ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
	119	_copy_command_line:
3f218935 MS	120	lbu r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */
3f218935 MS	121	sb r2, r4, r6 /* addr[r4+r6]= r2*/
5846cc60 MS	122	addik r6, r6, 1 /* increment counting */
	123	bgtid r3, _copy_command_line /* loop for all entries */
	124	addik r3, r3, -1 /* descrement loop */
	125	addik r5, r4, 0 /* add new space for command line */
	126	tovirt(r5,r5)
	127	#endif /* CONFIG_CMDLINE_BOOL */
	128
	129	#ifdef NOT_COMPILE
	130	/* save bram context */
	131	or r6, r0, r0 /* incremment */
	132	ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */
	133	ori r3, r0, (LMB_SIZE - 4)
	134	_copy_bram:
	135	lw r7, r0, r6 /* r7 = r0 + r6 */
	136	sw r7, r4, r6 /* addr[r4 + r6] = r7*/
	137	addik r6, r6, 4 /* increment counting */
	138	bgtid r3, _copy_bram /* loop for all entries */
	139	addik r3, r3, -4 /* descrement loop */
	140	#endif
	141	/* We have to turn on the MMU right away. */
	142
	143	/*
	144	* Set up the initial MMU state so we can do the first level of
	145	* kernel initialization. This maps the first 16 MBytes of memory 1:1
	146	* virtual to physical.
	147	*/
	148	nop
0691c97d	149	addik r3, r0, MICROBLAZE_TLB_SIZE -1 /* Invalidate all TLB entries */
5846cc60 MS	150	_invalidate:
	151	mts rtlbx, r3
	152	mts rtlbhi, r0 /* flush: ensure V is clear */
	153	bgtid r3, _invalidate /* loop for all entries */
	154	addik r3, r3, -1
	155	/* sync */
	156
137d0795 MS	157	/* Setup the kernel PID */
	158	mts rpid,r0 /* Load the kernel PID */
	159	nop
	160	bri 4
	161
5846cc60 MS	162	/*
	163	* We should still be executing code at physical address area
	164	* RAM_BASEADDR at this point. However, kernel code is at
	165	* a virtual address. So, set up a TLB mapping to cover this once
	166	* translation is enabled.
	167	*/
	168
	169	addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
	170	tophys(r4,r3) /* Load the kernel physical address */
	171
5846cc60 MS	172	/*
	173	* Configure and load two entries into TLB slots 0 and 1.
	174	* In case we are pinning TLBs, these are reserved in by the
	175	* other TLB functions. If not reserving, then it doesn't
	176	* matter where they are loaded.
	177	*/
	178	andi r4,r4,0xfffffc00 /* Mask off the real page number */
	179	ori r4,r4,(TLB_WR \| TLB_EX) /* Set the write and execute bits */
	180
	181	andi r3,r3,0xfffffc00 /* Mask off the effective page number */
	182	ori r3,r3,(TLB_VALID \| TLB_PAGESZ(PAGESZ_16M))
	183
	184	mts rtlbx,r0 /* TLB slow 0 */
	185
	186	mts rtlblo,r4 /* Load the data portion of the entry */
	187	mts rtlbhi,r3 /* Load the tag portion of the entry */
	188
	189	addik r4, r4, 0x01000000 /* Map next 16 M entries */
	190	addik r3, r3, 0x01000000
	191
	192	ori r6,r0,1 /* TLB slot 1 */
	193	mts rtlbx,r6
	194
	195	mts rtlblo,r4 /* Load the data portion of the entry */
	196	mts rtlbhi,r3 /* Load the tag portion of the entry */
	197
	198	/*
	199	* Load a TLB entry for LMB, since we need access to
	200	* the exception vectors, using a 4k real==virtual mapping.
	201	*/
	202	ori r6,r0,3 /* TLB slot 3 */
	203	mts rtlbx,r6
	204
	205	ori r4,r0,(TLB_WR \| TLB_EX)
	206	ori r3,r0,(TLB_VALID \| TLB_PAGESZ(PAGESZ_4K))
	207
	208	mts rtlblo,r4 /* Load the data portion of the entry */
	209	mts rtlbhi,r3 /* Load the tag portion of the entry */
	210
	211	/*
	212	* We now have the lower 16 Meg of RAM mapped into TLB entries, and the
	213	* caches ready to work.
	214	*/
	215	turn_on_mmu:
	216	ori r15,r0,start_here
	217	ori r4,r0,MSR_KERNEL_VMS
	218	mts rmsr,r4
	219	nop
	220	rted r15,0 /* enables MMU */
	221	nop
	222
	223	start_here:
	224	#endif /* CONFIG_MMU */
	225
6d5af1a3	226	/* Initialize small data anchors */
cd341577 MS	227	addik r13, r0, _KERNEL_SDA_BASE_
cd341577 MS	228	addik r2, r0, _KERNEL_SDA2_BASE_
6d5af1a3 MS	229
6d5af1a3 MS	230	/* Initialize stack pointer */
cd341577	231	addik r1, r0, init_thread_union + THREAD_SIZE - 4
6d5af1a3 MS	232
6d5af1a3 MS	233	/* Initialize r31 with current task address */
cd341577	234	addik r31, r0, init_task
6d5af1a3 MS	235
	236	/*
	237	* Call platform dependent initialize function.
	238	* Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
	239	* the function.
	240	*/
cd341577	241	addik r9, r0, machine_early_init
2622434e	242	brald r15, r9
6d5af1a3 MS	243	nop
6d5af1a3 MS	244
5846cc60	245	#ifndef CONFIG_MMU
cd341577	246	addik r15, r0, machine_halt
6d5af1a3 MS	247	braid start_kernel
6d5af1a3 MS	248	nop
5846cc60 MS	249	#else
	250	/*
	251	* Initialize the MMU.
	252	*/
	253	bralid r15, mmu_init
	254	nop
	255
	256	/* Go back to running unmapped so we can load up new values
	257	* and change to using our exception vectors.
	258	* On the MicroBlaze, all we invalidate the used TLB entries to clear
	259	* the old 16M byte TLB mappings.
	260	*/
	261	ori r15,r0,TOPHYS(kernel_load_context)
	262	ori r4,r0,MSR_KERNEL
	263	mts rmsr,r4
	264	nop
	265	bri 4
	266	rted r15,0
	267	nop
	268
	269	/* Load up the kernel context */
	270	kernel_load_context:
	271	# Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away.
	272	ori r5,r0,3
	273	mts rtlbx,r5
	274	nop
	275	mts rtlbhi,r0
	276	nop
	277	addi r15, r0, machine_halt
	278	ori r17, r0, start_kernel
	279	ori r4, r0, MSR_KERNEL_VMS
	280	mts rmsr, r4
	281	nop
	282	rted r17, 0 /* enable MMU and jump to start_kernel */
	283	nop
	284	#endif /* CONFIG_MMU */