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c4df4bc1 MS |
1 | /* |
2 | * HW exception handling | |
3 | * | |
4 | * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> | |
5 | * Copyright (C) 2008 PetaLogix | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General | |
8 | * Public License. See the file COPYING in the main directory of this | |
9 | * archive for more details. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * This file handles the architecture-dependent parts of hardware exceptions | |
14 | */ | |
15 | ||
d64af918 | 16 | #include <linux/export.h> |
c4df4bc1 MS |
17 | #include <linux/kernel.h> |
18 | #include <linux/signal.h> | |
19 | #include <linux/sched.h> | |
b17b0153 | 20 | #include <linux/sched/debug.h> |
c4df4bc1 | 21 | #include <linux/kallsyms.h> |
c4df4bc1 MS |
22 | |
23 | #include <asm/exceptions.h> | |
24 | #include <asm/entry.h> /* For KM CPU var */ | |
4bb73c3d MS |
25 | #include <linux/uaccess.h> |
26 | #include <linux/errno.h> | |
27 | #include <linux/ptrace.h> | |
c4df4bc1 | 28 | #include <asm/current.h> |
17b93146 | 29 | #include <asm/cacheflush.h> |
c4df4bc1 MS |
30 | |
31 | #define MICROBLAZE_ILL_OPCODE_EXCEPTION 0x02 | |
32 | #define MICROBLAZE_IBUS_EXCEPTION 0x03 | |
33 | #define MICROBLAZE_DBUS_EXCEPTION 0x04 | |
34 | #define MICROBLAZE_DIV_ZERO_EXCEPTION 0x05 | |
35 | #define MICROBLAZE_FPU_EXCEPTION 0x06 | |
4bb73c3d | 36 | #define MICROBLAZE_PRIVILEGED_EXCEPTION 0x07 |
c4df4bc1 MS |
37 | |
38 | static DEFINE_SPINLOCK(die_lock); | |
39 | ||
40 | void die(const char *str, struct pt_regs *fp, long err) | |
41 | { | |
42 | console_verbose(); | |
43 | spin_lock_irq(&die_lock); | |
6bd55f0b | 44 | pr_warn("Oops: %s, sig: %ld\n", str, err); |
c4df4bc1 MS |
45 | show_regs(fp); |
46 | spin_unlock_irq(&die_lock); | |
47 | /* do_exit() should take care of panic'ing from an interrupt | |
48 | * context so we don't handle it here | |
49 | */ | |
50 | do_exit(err); | |
51 | } | |
52 | ||
751f1605 | 53 | /* for user application debugging */ |
f699980b | 54 | asmlinkage void sw_exception(struct pt_regs *regs) |
751f1605 MS |
55 | { |
56 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16); | |
17b93146 MS |
57 | flush_dcache_range(regs->r16, regs->r16 + 0x4); |
58 | flush_icache_range(regs->r16, regs->r16 + 0x4); | |
751f1605 MS |
59 | } |
60 | ||
c4df4bc1 MS |
61 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
62 | { | |
63 | siginfo_t info; | |
64 | ||
6bd55f0b | 65 | if (kernel_mode(regs)) |
c4df4bc1 | 66 | die("Exception in kernel mode", regs, signr); |
6bd55f0b | 67 | |
c4df4bc1 MS |
68 | info.si_signo = signr; |
69 | info.si_errno = 0; | |
70 | info.si_code = code; | |
71 | info.si_addr = (void __user *) addr; | |
72 | force_sig_info(signr, &info, current); | |
73 | } | |
74 | ||
75 | asmlinkage void full_exception(struct pt_regs *regs, unsigned int type, | |
76 | int fsr, int addr) | |
77 | { | |
4bb73c3d | 78 | #ifdef CONFIG_MMU |
4bb73c3d MS |
79 | addr = regs->pc; |
80 | #endif | |
81 | ||
c4df4bc1 | 82 | #if 0 |
6bd55f0b | 83 | pr_warn("Exception %02x in %s mode, FSR=%08x PC=%08x ESR=%08x\n", |
c4df4bc1 MS |
84 | type, user_mode(regs) ? "user" : "kernel", fsr, |
85 | (unsigned int) regs->pc, (unsigned int) regs->esr); | |
86 | #endif | |
87 | ||
88 | switch (type & 0x1F) { | |
89 | case MICROBLAZE_ILL_OPCODE_EXCEPTION: | |
4bb73c3d | 90 | if (user_mode(regs)) { |
c4554c32 | 91 | pr_debug("Illegal opcode exception in user mode\n"); |
4bb73c3d MS |
92 | _exception(SIGILL, regs, ILL_ILLOPC, addr); |
93 | return; | |
94 | } | |
6bd55f0b | 95 | pr_warn("Illegal opcode exception in kernel mode.\n"); |
4bb73c3d | 96 | die("opcode exception", regs, SIGBUS); |
c4df4bc1 MS |
97 | break; |
98 | case MICROBLAZE_IBUS_EXCEPTION: | |
99 | if (user_mode(regs)) { | |
c4554c32 | 100 | pr_debug("Instruction bus error exception in user mode\n"); |
c4df4bc1 MS |
101 | _exception(SIGBUS, regs, BUS_ADRERR, addr); |
102 | return; | |
103 | } | |
6bd55f0b | 104 | pr_warn("Instruction bus error exception in kernel mode.\n"); |
c4df4bc1 MS |
105 | die("bus exception", regs, SIGBUS); |
106 | break; | |
107 | case MICROBLAZE_DBUS_EXCEPTION: | |
108 | if (user_mode(regs)) { | |
c4554c32 | 109 | pr_debug("Data bus error exception in user mode\n"); |
c4df4bc1 MS |
110 | _exception(SIGBUS, regs, BUS_ADRERR, addr); |
111 | return; | |
112 | } | |
6bd55f0b | 113 | pr_warn("Data bus error exception in kernel mode.\n"); |
c4df4bc1 MS |
114 | die("bus exception", regs, SIGBUS); |
115 | break; | |
116 | case MICROBLAZE_DIV_ZERO_EXCEPTION: | |
4bb73c3d | 117 | if (user_mode(regs)) { |
c4554c32 | 118 | pr_debug("Divide by zero exception in user mode\n"); |
15ec0908 | 119 | _exception(SIGFPE, regs, FPE_INTDIV, addr); |
4bb73c3d MS |
120 | return; |
121 | } | |
6bd55f0b | 122 | pr_warn("Divide by zero exception in kernel mode.\n"); |
f3ff8212 | 123 | die("Divide by zero exception", regs, SIGBUS); |
c4df4bc1 | 124 | break; |
c4df4bc1 | 125 | case MICROBLAZE_FPU_EXCEPTION: |
c4554c32 | 126 | pr_debug("FPU exception\n"); |
c4df4bc1 MS |
127 | /* IEEE FP exception */ |
128 | /* I removed fsr variable and use code var for storing fsr */ | |
129 | if (fsr & FSR_IO) | |
130 | fsr = FPE_FLTINV; | |
131 | else if (fsr & FSR_OF) | |
132 | fsr = FPE_FLTOVF; | |
133 | else if (fsr & FSR_UF) | |
134 | fsr = FPE_FLTUND; | |
135 | else if (fsr & FSR_DZ) | |
136 | fsr = FPE_FLTDIV; | |
137 | else if (fsr & FSR_DO) | |
138 | fsr = FPE_FLTRES; | |
139 | _exception(SIGFPE, regs, fsr, addr); | |
140 | break; | |
141 | ||
4bb73c3d MS |
142 | #ifdef CONFIG_MMU |
143 | case MICROBLAZE_PRIVILEGED_EXCEPTION: | |
c4554c32 | 144 | pr_debug("Privileged exception\n"); |
04256096 | 145 | _exception(SIGILL, regs, ILL_PRVOPC, addr); |
4bb73c3d MS |
146 | break; |
147 | #endif | |
c4df4bc1 | 148 | default: |
4bb73c3d | 149 | /* FIXME what to do in unexpected exception */ |
6bd55f0b MS |
150 | pr_warn("Unexpected exception %02x PC=%08x in %s mode\n", |
151 | type, (unsigned int) addr, | |
c4df4bc1 MS |
152 | kernel_mode(regs) ? "kernel" : "user"); |
153 | } | |
154 | return; | |
155 | } |