projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | ! SPDX-License-Identifier: GPL-2.0 |
| 086e9dc0 JH |
2 | ! Copyright (C) 2012 Imagination Technologies Ltd. |
| 3 | ! | |
| 4 | ! Signed/unsigned 64-bit division routines. | |
| 5 | ! | |
| 6 | ||
| 7 | .text | |
| 8 | .global _div_u64 | |
| 9 | .type _div_u64,function | |
| 10 | ||
| 11 | _div_u64: | |
| 12 | $L1: | |
| 13 | ORS A0.3,D1Ar3,D0Ar4 | |
| 14 | BNE $L3 | |
| 15 | $L2: | |
| 16 | MOV D0Re0,D0Ar2 | |
| 17 | MOV D1Re0,D1Ar1 | |
| 18 | MOV PC,D1RtP | |
| 19 | $L3: | |
| 20 | CMP D1Ar3,D1Ar1 | |
| 21 | CMPEQ D0Ar4,D0Ar2 | |
| 22 | MOV D0Re0,#1 | |
| 23 | MOV D1Re0,#0 | |
| 24 | BHS $L6 | |
| 25 | $L4: | |
| 26 | ADDS D0Ar6,D0Ar4,D0Ar4 | |
| 27 | ADD D1Ar5,D1Ar3,D1Ar3 | |
| 28 | ADDCS D1Ar5,D1Ar5,#1 | |
| 29 | CMP D1Ar5,D1Ar3 | |
| 30 | CMPEQ D0Ar6,D0Ar4 | |
| 31 | BLO $L6 | |
| 32 | $L5: | |
| 33 | MOV D0Ar4,D0Ar6 | |
| 34 | MOV D1Ar3,D1Ar5 | |
| 35 | ADDS D0Re0,D0Re0,D0Re0 | |
| 36 | ADD D1Re0,D1Re0,D1Re0 | |
| 37 | ADDCS D1Re0,D1Re0,#1 | |
| 38 | CMP D1Ar3,D1Ar1 | |
| 39 | CMPEQ D0Ar4,D0Ar2 | |
| 40 | BLO $L4 | |
| 41 | $L6: | |
| 42 | ORS A0.3,D1Re0,D0Re0 | |
| 43 | MOV D0Ar6,#0 | |
| 44 | MOV D1Ar5,D0Ar6 | |
| 45 | BEQ $L10 | |
| 46 | $L7: | |
| 47 | CMP D1Ar1,D1Ar3 | |
| 48 | CMPEQ D0Ar2,D0Ar4 | |
| 49 | BLO $L9 | |
| 50 | $L8: | |
| 51 | ADDS D0Ar6,D0Ar6,D0Re0 | |
| 52 | ADD D1Ar5,D1Ar5,D1Re0 | |
| 53 | ADDCS D1Ar5,D1Ar5,#1 | |
| 54 | ||
| 55 | SUBS D0Ar2,D0Ar2,D0Ar4 | |
| 56 | SUB D1Ar1,D1Ar1,D1Ar3 | |
| 57 | SUBCS D1Ar1,D1Ar1,#1 | |
| 58 | $L9: | |
| 59 | LSL A0.3,D1Re0,#31 | |
| 60 | LSR D0Re0,D0Re0,#1 | |
| 61 | LSR D1Re0,D1Re0,#1 | |
| 62 | OR D0Re0,D0Re0,A0.3 | |
| 63 | LSL A0.3,D1Ar3,#31 | |
| 64 | LSR D0Ar4,D0Ar4,#1 | |
| 65 | LSR D1Ar3,D1Ar3,#1 | |
| 66 | OR D0Ar4,D0Ar4,A0.3 | |
| 67 | ORS A0.3,D1Re0,D0Re0 | |
| 68 | BNE $L7 | |
| 69 | $L10: | |
| 70 | MOV D0Re0,D0Ar6 | |
| 71 | MOV D1Re0,D1Ar5 | |
| 72 | MOV PC,D1RtP | |
| 73 | .size _div_u64,.-_div_u64 | |
| 74 | ||
| 75 | .text | |
| 76 | .global _div_s64 | |
| 77 | .type _div_s64,function | |
| 78 | _div_s64: | |
| 79 | MSETL [A0StP],D0FrT,D0.5 | |
| 80 | XOR D0.5,D0Ar2,D0Ar4 | |
| 81 | XOR D1.5,D1Ar1,D1Ar3 | |
| 82 | TSTT D1Ar1,#HI(0x80000000) | |
| 83 | BZ $L25 | |
| 84 | ||
| 85 | NEGS D0Ar2,D0Ar2 | |
| 86 | NEG D1Ar1,D1Ar1 | |
| 87 | SUBCS D1Ar1,D1Ar1,#1 | |
| 88 | $L25: | |
| 89 | TSTT D1Ar3,#HI(0x80000000) | |
| 90 | BZ $L27 | |
| 91 | ||
| 92 | NEGS D0Ar4,D0Ar4 | |
| 93 | NEG D1Ar3,D1Ar3 | |
| 94 | SUBCS D1Ar3,D1Ar3,#1 | |
| 95 | $L27: | |
| 96 | CALLR D1RtP,_div_u64 | |
| 97 | TSTT D1.5,#HI(0x80000000) | |
| 98 | BZ $L29 | |
| 99 | ||
| 100 | NEGS D0Re0,D0Re0 | |
| 101 | NEG D1Re0,D1Re0 | |
| 102 | SUBCS D1Re0,D1Re0,#1 | |
| 103 | $L29: | |
| 104 | ||
| 105 | GETL D0FrT,D1RtP,[A0StP+#(-16)] | |
| 106 | GETL D0.5,D1.5,[A0StP+#(-8)] | |
| 107 | SUB A0StP,A0StP,#16 | |
| 108 | MOV PC,D1RtP | |
| 109 | .size _div_s64,.-_div_s64 |