[linux-2.6-block.git] / arch / metag / kernel / cachepart.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Meta cache partition manipulation.
 *
 * Copyright 2010 Imagination Technologies Ltd.
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <asm/processor.h>
#include <asm/cachepart.h>
#include <asm/metag_isa.h>
#include <asm/metag_mem.h>

#define SYSC_DCPART(n)	(SYSC_DCPART0 + SYSC_xCPARTn_STRIDE * (n))
#define SYSC_ICPART(n)	(SYSC_ICPART0 + SYSC_xCPARTn_STRIDE * (n))

#define CACHE_ASSOCIATIVITY 4 /* 4 way set-associative */
#define ICACHE 0
#define DCACHE 1

/* The CORE_CONFIG2 register is not available on Meta 1 */
#ifdef CONFIG_METAG_META21
unsigned int get_dcache_size(void)
{
	unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
	unsigned int sz = 0x1000 << ((config2 & METAC_CORECFG2_DCSZ_BITS)
				     >> METAC_CORECFG2_DCSZ_S);
	if (config2 & METAC_CORECFG2_DCSMALL_BIT)
		sz >>= 6;
	return sz;
}

unsigned int get_icache_size(void)
{
	unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
	unsigned int sz = 0x1000 << ((config2 & METAC_CORE_C2ICSZ_BITS)
				     >> METAC_CORE_C2ICSZ_S);
	if (config2 & METAC_CORECFG2_ICSMALL_BIT)
		sz >>= 6;
	return sz;
}

unsigned int get_global_dcache_size(void)
{
	unsigned int cpart = metag_in32(SYSC_DCPART(hard_processor_id()));
	unsigned int temp = cpart & SYSC_xCPARTG_AND_BITS;
	return (get_dcache_size() * ((temp >> SYSC_xCPARTG_AND_S) + 1)) >> 4;
}

unsigned int get_global_icache_size(void)
{
	unsigned int cpart = metag_in32(SYSC_ICPART(hard_processor_id()));
	unsigned int temp = cpart & SYSC_xCPARTG_AND_BITS;
	return (get_icache_size() * ((temp >> SYSC_xCPARTG_AND_S) + 1)) >> 4;
}

static int get_thread_cache_size(unsigned int cache, int thread_id)
{
	unsigned int cache_size;
	unsigned int t_cache_part;
	unsigned int isEnabled;
	unsigned int offset = 0;
	isEnabled = (cache == DCACHE ? metag_in32(MMCU_DCACHE_CTRL_ADDR) & 0x1 :
		metag_in32(MMCU_ICACHE_CTRL_ADDR) & 0x1);
	if (!isEnabled)
		return 0;
#if PAGE_OFFSET >= LINGLOBAL_BASE
	/* Checking for global cache */
	cache_size = (cache == DCACHE ? get_global_dcache_size() :
		get_global_icache_size());
	offset = 8;
#else
	cache_size = (cache == DCACHE ? get_dcache_size() :
		get_icache_size());
#endif
	t_cache_part = (cache == DCACHE ?
		(metag_in32(SYSC_DCPART(thread_id)) >> offset) & 0xF :
		(metag_in32(SYSC_ICPART(thread_id)) >> offset) & 0xF);
	switch (t_cache_part) {
	case 0xF:
		return cache_size;
	case 0x7:
		return cache_size / 2;
	case 0x3:
		return cache_size / 4;
	case 0x1:
		return cache_size / 8;
	case 0:
		return cache_size / 16;
	}
	return -1;
}

void check_for_cache_aliasing(int thread_id)
{
	int thread_cache_size;
	unsigned int cache_type;
	for (cache_type = ICACHE; cache_type <= DCACHE; cache_type++) {
		thread_cache_size =
				get_thread_cache_size(cache_type, thread_id);
		if (thread_cache_size < 0)
			pr_emerg("Can't read %s cache size\n",
				 cache_type ? "DCACHE" : "ICACHE");
		else if (thread_cache_size == 0)
			/* Cache is off. No need to check for aliasing */
			continue;
		if (thread_cache_size / CACHE_ASSOCIATIVITY > PAGE_SIZE) {
			pr_emerg("Potential cache aliasing detected in %s on Thread %d\n",
				 cache_type ? "DCACHE" : "ICACHE", thread_id);
			pr_warn("Total %s size: %u bytes\n",
				cache_type ? "DCACHE" : "ICACHE",
				cache_type ? get_dcache_size()
				: get_icache_size());
			pr_warn("Thread %s size: %d bytes\n",
				cache_type ? "CACHE" : "ICACHE",
				thread_cache_size);
			pr_warn("Page Size: %lu bytes\n", PAGE_SIZE);
			panic("Potential cache aliasing detected");
		}
	}
}

#else

void check_for_cache_aliasing(int thread_id)
{
	return;
}

#endif
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
42682c6c JH	2	/*
	3	* Meta cache partition manipulation.
	4	*
	5	* Copyright 2010 Imagination Technologies Ltd.
	6	*/
	7
	8	#include <linux/kernel.h>
	9	#include <linux/io.h>
	10	#include <linux/errno.h>
	11	#include <asm/processor.h>
	12	#include <asm/cachepart.h>
	13	#include <asm/metag_isa.h>
	14	#include <asm/metag_mem.h>
	15
	16	#define SYSC_DCPART(n) (SYSC_DCPART0 + SYSC_xCPARTn_STRIDE * (n))
	17	#define SYSC_ICPART(n) (SYSC_ICPART0 + SYSC_xCPARTn_STRIDE * (n))
	18
986724dd	19	#define CACHE_ASSOCIATIVITY 4 /* 4 way set-associative */
42682c6c JH	20	#define ICACHE 0
	21	#define DCACHE 1
	22
	23	/* The CORE_CONFIG2 register is not available on Meta 1 */
	24	#ifdef CONFIG_METAG_META21
	25	unsigned int get_dcache_size(void)
	26	{
	27	unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
4d8edbfe JH	28	unsigned int sz = 0x1000 << ((config2 & METAC_CORECFG2_DCSZ_BITS)
	29	>> METAC_CORECFG2_DCSZ_S);
	30	if (config2 & METAC_CORECFG2_DCSMALL_BIT)
	31	sz >>= 6;
	32	return sz;
42682c6c JH	33	}
	34
	35	unsigned int get_icache_size(void)
	36	{
	37	unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
4d8edbfe JH	38	unsigned int sz = 0x1000 << ((config2 & METAC_CORE_C2ICSZ_BITS)
	39	>> METAC_CORE_C2ICSZ_S);
	40	if (config2 & METAC_CORECFG2_ICSMALL_BIT)
	41	sz >>= 6;
	42	return sz;
42682c6c JH	43	}
	44
	45	unsigned int get_global_dcache_size(void)
	46	{
	47	unsigned int cpart = metag_in32(SYSC_DCPART(hard_processor_id()));
	48	unsigned int temp = cpart & SYSC_xCPARTG_AND_BITS;
	49	return (get_dcache_size() * ((temp >> SYSC_xCPARTG_AND_S) + 1)) >> 4;
	50	}
	51
	52	unsigned int get_global_icache_size(void)
	53	{
	54	unsigned int cpart = metag_in32(SYSC_ICPART(hard_processor_id()));
	55	unsigned int temp = cpart & SYSC_xCPARTG_AND_BITS;
	56	return (get_icache_size() * ((temp >> SYSC_xCPARTG_AND_S) + 1)) >> 4;
	57	}
	58
f93125ae	59	static int get_thread_cache_size(unsigned int cache, int thread_id)
42682c6c JH	60	{
	61	unsigned int cache_size;
	62	unsigned int t_cache_part;
	63	unsigned int isEnabled;
	64	unsigned int offset = 0;
	65	isEnabled = (cache == DCACHE ? metag_in32(MMCU_DCACHE_CTRL_ADDR) & 0x1 :
	66	metag_in32(MMCU_ICACHE_CTRL_ADDR) & 0x1);
	67	if (!isEnabled)
	68	return 0;
	69	#if PAGE_OFFSET >= LINGLOBAL_BASE
	70	/* Checking for global cache */
b7fb9e6a	71	cache_size = (cache == DCACHE ? get_global_dcache_size() :
42682c6c JH	72	get_global_icache_size());
	73	offset = 8;
	74	#else
	75	cache_size = (cache == DCACHE ? get_dcache_size() :
	76	get_icache_size());
	77	#endif
	78	t_cache_part = (cache == DCACHE ?
	79	(metag_in32(SYSC_DCPART(thread_id)) >> offset) & 0xF :
	80	(metag_in32(SYSC_ICPART(thread_id)) >> offset) & 0xF);
	81	switch (t_cache_part) {
	82	case 0xF:
	83	return cache_size;
	84	case 0x7:
	85	return cache_size / 2;
	86	case 0x3:
	87	return cache_size / 4;
	88	case 0x1:
	89	return cache_size / 8;
	90	case 0:
	91	return cache_size / 16;
	92	}
	93	return -1;
	94	}
	95
	96	void check_for_cache_aliasing(int thread_id)
	97	{
f93125ae	98	int thread_cache_size;
42682c6c JH	99	unsigned int cache_type;
	100	for (cache_type = ICACHE; cache_type <= DCACHE; cache_type++) {
	101	thread_cache_size =
	102	get_thread_cache_size(cache_type, thread_id);
	103	if (thread_cache_size < 0)
30dd5f7a	104	pr_emerg("Can't read %s cache size\n",
42682c6c JH	105	cache_type ? "DCACHE" : "ICACHE");
	106	else if (thread_cache_size == 0)
	107	/* Cache is off. No need to check for aliasing */
	108	continue;
	109	if (thread_cache_size / CACHE_ASSOCIATIVITY > PAGE_SIZE) {
30dd5f7a	110	pr_emerg("Potential cache aliasing detected in %s on Thread %d\n",
42682c6c	111	cache_type ? "DCACHE" : "ICACHE", thread_id);
30dd5f7a JH	112	pr_warn("Total %s size: %u bytes\n",
30dd5f7a JH	113	cache_type ? "DCACHE" : "ICACHE",
42682c6c JH	114	cache_type ? get_dcache_size()
42682c6c JH	115	: get_icache_size());
30dd5f7a	116	pr_warn("Thread %s size: %d bytes\n",
42682c6c JH	117	cache_type ? "CACHE" : "ICACHE",
42682c6c JH	118	thread_cache_size);
30dd5f7a JH	119	pr_warn("Page Size: %lu bytes\n", PAGE_SIZE);
30dd5f7a JH	120	panic("Potential cache aliasing detected");
42682c6c JH	121	}
	122	}
	123	}
	124
	125	#else
	126
	127	void check_for_cache_aliasing(int thread_id)
	128	{
	129	return;
	130	}
	131
	132	#endif