Commit | Line | Data |
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1da177e4 LT |
1 | /***************************************************************************/ |
2 | ||
3 | /* | |
b671b653 GU |
4 | * pit.c -- Freescale ColdFire PIT timer. Currently this type of |
5 | * hardware timer only exists in the Freescale ColdFire | |
8d80c5ee GU |
6 | * 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire |
7 | * family members will probably use it too. | |
1da177e4 | 8 | * |
8d80c5ee | 9 | * Copyright (C) 1999-2008, Greg Ungerer (gerg@snapgear.com) |
1da177e4 | 10 | * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) |
1da177e4 LT |
11 | */ |
12 | ||
13 | /***************************************************************************/ | |
14 | ||
1da177e4 LT |
15 | #include <linux/kernel.h> |
16 | #include <linux/sched.h> | |
17 | #include <linux/param.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/interrupt.h> | |
5c4525da | 20 | #include <linux/irq.h> |
2b9a6986 | 21 | #include <linux/clockchips.h> |
2f2c2679 | 22 | #include <asm/machdep.h> |
b671b653 | 23 | #include <asm/io.h> |
1da177e4 LT |
24 | #include <asm/coldfire.h> |
25 | #include <asm/mcfpit.h> | |
26 | #include <asm/mcfsim.h> | |
27 | ||
28 | /***************************************************************************/ | |
29 | ||
b671b653 GU |
30 | /* |
31 | * By default use timer1 as the system clock timer. | |
32 | */ | |
8d80c5ee | 33 | #define FREQ ((MCF_CLK / 2) / 64) |
b671b653 | 34 | #define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a)) |
2b9a6986 | 35 | #define PIT_CYCLES_PER_JIFFY (FREQ / HZ) |
8d80c5ee | 36 | |
8d80c5ee | 37 | static u32 pit_cnt; |
b671b653 | 38 | |
2b9a6986 SS |
39 | /* |
40 | * Initialize the PIT timer. | |
41 | * | |
42 | * This is also called after resume to bring the PIT into operation again. | |
43 | */ | |
44 | ||
45 | static void init_cf_pit_timer(enum clock_event_mode mode, | |
46 | struct clock_event_device *evt) | |
47 | { | |
48 | switch (mode) { | |
49 | case CLOCK_EVT_MODE_PERIODIC: | |
50 | ||
51 | __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); | |
52 | __raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR)); | |
53 | __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | \ | |
54 | MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD | \ | |
55 | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR)); | |
56 | break; | |
57 | ||
58 | case CLOCK_EVT_MODE_SHUTDOWN: | |
59 | case CLOCK_EVT_MODE_UNUSED: | |
60 | ||
61 | __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); | |
62 | break; | |
63 | ||
64 | case CLOCK_EVT_MODE_ONESHOT: | |
65 | ||
66 | __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); | |
67 | __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | \ | |
68 | MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, \ | |
69 | TA(MCFPIT_PCSR)); | |
70 | break; | |
71 | ||
72 | case CLOCK_EVT_MODE_RESUME: | |
73 | /* Nothing to do here */ | |
74 | break; | |
75 | } | |
76 | } | |
77 | ||
78 | /* | |
79 | * Program the next event in oneshot mode | |
80 | * | |
81 | * Delta is given in PIT ticks | |
82 | */ | |
83 | static int cf_pit_next_event(unsigned long delta, | |
84 | struct clock_event_device *evt) | |
85 | { | |
86 | __raw_writew(delta, TA(MCFPIT_PMR)); | |
87 | return 0; | |
88 | } | |
89 | ||
90 | struct clock_event_device cf_pit_clockevent = { | |
91 | .name = "pit", | |
92 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
93 | .set_mode = init_cf_pit_timer, | |
94 | .set_next_event = cf_pit_next_event, | |
95 | .shift = 32, | |
96 | .irq = MCFINT_VECBASE + MCFINT_PIT1, | |
97 | }; | |
98 | ||
99 | ||
100 | ||
b671b653 GU |
101 | /***************************************************************************/ |
102 | ||
8d80c5ee | 103 | static irqreturn_t pit_tick(int irq, void *dummy) |
1da177e4 | 104 | { |
2b9a6986 | 105 | struct clock_event_device *evt = &cf_pit_clockevent; |
8d80c5ee | 106 | u16 pcsr; |
1da177e4 LT |
107 | |
108 | /* Reset the ColdFire timer */ | |
b671b653 GU |
109 | pcsr = __raw_readw(TA(MCFPIT_PCSR)); |
110 | __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR)); | |
2f2c2679 | 111 | |
2b9a6986 SS |
112 | pit_cnt += PIT_CYCLES_PER_JIFFY; |
113 | evt->event_handler(evt); | |
114 | return IRQ_HANDLED; | |
1da177e4 LT |
115 | } |
116 | ||
117 | /***************************************************************************/ | |
118 | ||
8d80c5ee | 119 | static struct irqaction pit_irq = { |
2f2c2679 GU |
120 | .name = "timer", |
121 | .flags = IRQF_DISABLED | IRQF_TIMER, | |
8d80c5ee | 122 | .handler = pit_tick, |
5c4525da GU |
123 | }; |
124 | ||
8d80c5ee GU |
125 | /***************************************************************************/ |
126 | ||
8e19608e | 127 | static cycle_t pit_read_clk(struct clocksource *cs) |
1da177e4 | 128 | { |
8d80c5ee GU |
129 | unsigned long flags; |
130 | u32 cycles; | |
131 | u16 pcntr; | |
1da177e4 | 132 | |
8d80c5ee GU |
133 | local_irq_save(flags); |
134 | pcntr = __raw_readw(TA(MCFPIT_PCNTR)); | |
135 | cycles = pit_cnt; | |
136 | local_irq_restore(flags); | |
1da177e4 | 137 | |
2b9a6986 | 138 | return cycles + PIT_CYCLES_PER_JIFFY - pcntr; |
8d80c5ee | 139 | } |
1da177e4 | 140 | |
8d80c5ee | 141 | /***************************************************************************/ |
1da177e4 | 142 | |
8d80c5ee GU |
143 | static struct clocksource pit_clk = { |
144 | .name = "pit", | |
2b9a6986 | 145 | .rating = 100, |
8d80c5ee GU |
146 | .read = pit_read_clk, |
147 | .shift = 20, | |
148 | .mask = CLOCKSOURCE_MASK(32), | |
8d80c5ee | 149 | }; |
1da177e4 LT |
150 | |
151 | /***************************************************************************/ | |
152 | ||
8d80c5ee | 153 | void hw_timer_init(void) |
1da177e4 | 154 | { |
320ab2b0 | 155 | cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id()); |
2b9a6986 SS |
156 | cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32); |
157 | cf_pit_clockevent.max_delta_ns = | |
158 | clockevent_delta2ns(0xFFFF, &cf_pit_clockevent); | |
159 | cf_pit_clockevent.min_delta_ns = | |
160 | clockevent_delta2ns(0x3f, &cf_pit_clockevent); | |
161 | clockevents_register_device(&cf_pit_clockevent); | |
162 | ||
8d80c5ee | 163 | setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq); |
1da177e4 | 164 | |
8d80c5ee GU |
165 | pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift); |
166 | clocksource_register(&pit_clk); | |
1da177e4 LT |
167 | } |
168 | ||
169 | /***************************************************************************/ |