projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| cd3dd406 GU |
1 | /* |
| 2 | * intc-simr.c | |
| 3 | * | |
| 03cbc385 PDM |
4 | * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts. |
| 5 | * | |
| cd3dd406 GU |
6 | * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> |
| 7 | * | |
| 8 | * This file is subject to the terms and conditions of the GNU General Public | |
| 9 | * License. See the file COPYING in the main directory of this archive | |
| 10 | * for more details. | |
| 11 | */ | |
| 12 | ||
| 13 | #include <linux/types.h> | |
| 14 | #include <linux/init.h> | |
| 15 | #include <linux/kernel.h> | |
| 16 | #include <linux/interrupt.h> | |
| 17 | #include <linux/irq.h> | |
| 18 | #include <linux/io.h> | |
| 19 | #include <asm/coldfire.h> | |
| 20 | #include <asm/mcfsim.h> | |
| 21 | #include <asm/traps.h> | |
| 22 | ||
| f80c353c | 23 | static void intc_irq_mask(struct irq_data *d) |
| cd3dd406 | 24 | { |
| f80c353c TG |
25 | unsigned int irq = d->irq; |
| 26 | ||
| 277c5e3e GU |
27 | if (irq >= MCFINT_VECBASE) { |
| 28 | if (irq < MCFINT_VECBASE + 64) | |
| 29 | __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR); | |
| 30 | else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR) | |
| 31 | __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR); | |
| 32 | } | |
| cd3dd406 GU |
33 | } |
| 34 | ||
| f80c353c | 35 | static void intc_irq_unmask(struct irq_data *d) |
| cd3dd406 | 36 | { |
| f80c353c TG |
37 | unsigned int irq = d->irq; |
| 38 | ||
| 277c5e3e GU |
39 | if (irq >= MCFINT_VECBASE) { |
| 40 | if (irq < MCFINT_VECBASE + 64) | |
| 41 | __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR); | |
| 42 | else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR) | |
| 43 | __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR); | |
| 44 | } | |
| cd3dd406 GU |
45 | } |
| 46 | ||
| f80c353c | 47 | static int intc_irq_set_type(struct irq_data *d, unsigned int type) |
| cd3dd406 | 48 | { |
| f80c353c TG |
49 | unsigned int irq = d->irq; |
| 50 | ||
| 277c5e3e GU |
51 | if (irq >= MCFINT_VECBASE) { |
| 52 | if (irq < MCFINT_VECBASE + 64) | |
| 53 | __raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE); | |
| 54 | else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0) | |
| 55 | __raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64); | |
| 56 | } | |
| cd3dd406 GU |
57 | return 0; |
| 58 | } | |
| 59 | ||
| 60 | static struct irq_chip intc_irq_chip = { | |
| 61 | .name = "CF-INTC", | |
| f80c353c TG |
62 | .irq_mask = intc_irq_mask, |
| 63 | .irq_unmask = intc_irq_unmask, | |
| 64 | .irq_set_type = intc_irq_set_type, | |
| cd3dd406 GU |
65 | }; |
| 66 | ||
| 67 | void __init init_IRQ(void) | |
| 68 | { | |
| 69 | int irq; | |
| 70 | ||
| 71 | init_vectors(); | |
| 72 | ||
| e47cc3d6 GU |
73 | /* Mask all interrupt sources */ |
| 74 | __raw_writeb(0xff, MCFINTC0_SIMR); | |
| 75 | if (MCFINTC1_SIMR) | |
| 76 | __raw_writeb(0xff, MCFINTC1_SIMR); | |
| 77 | ||
| cd3dd406 | 78 | for (irq = 0; (irq < NR_IRQS); irq++) { |
| 04570b46 GU |
79 | set_irq_chip(irq, &intc_irq_chip); |
| 80 | set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); | |
| 81 | set_irq_handler(irq, handle_level_irq); | |
| cd3dd406 GU |
82 | } |
| 83 | } | |
| 84 |