[linux-2.6-block.git] / arch / m68k / platform / 528x / config.c

/***************************************************************************/

/*
 *	linux/arch/m68knommu/platform/528x/config.c
 *
 *	Sub-architcture dependent initialization code for the Freescale
 *	5280, 5281 and 5282 CPUs.
 *
 *	Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
 *	Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
 */

/***************************************************************************/

#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/gpio.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfqspi.h>

/***************************************************************************/

static struct mcf_platform_uart m528x_uart_platform[] = {
	{
		.mapbase	= MCFUART_BASE1,
		.irq		= MCFINT_VECBASE + MCFINT_UART0,
	},
	{
		.mapbase 	= MCFUART_BASE2,
		.irq		= MCFINT_VECBASE + MCFINT_UART0 + 1,
	},
	{
		.mapbase 	= MCFUART_BASE3,
		.irq		= MCFINT_VECBASE + MCFINT_UART0 + 2,
	},
	{ },
};

static struct platform_device m528x_uart = {
	.name			= "mcfuart",
	.id			= 0,
	.dev.platform_data	= m528x_uart_platform,
};

static struct resource m528x_fec_resources[] = {
	{
		.start		= MCFFEC_BASE,
		.end		= MCFFEC_BASE + MCFFEC_SIZE - 1,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= 64 + 23,
		.end		= 64 + 23,
		.flags		= IORESOURCE_IRQ,
	},
	{
		.start		= 64 + 27,
		.end		= 64 + 27,
		.flags		= IORESOURCE_IRQ,
	},
	{
		.start		= 64 + 29,
		.end		= 64 + 29,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device m528x_fec = {
	.name			= "fec",
	.id			= 0,
	.num_resources		= ARRAY_SIZE(m528x_fec_resources),
	.resource		= m528x_fec_resources,
};

#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
static struct resource m528x_qspi_resources[] = {
	{
		.start		= MCFQSPI_IOBASE,
		.end		= MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= MCFINT_VECBASE + MCFINT_QSPI,
		.end		= MCFINT_VECBASE + MCFINT_QSPI,
		.flags		= IORESOURCE_IRQ,
	},
};

#define MCFQSPI_CS0    147
#define MCFQSPI_CS1    148
#define MCFQSPI_CS2    149
#define MCFQSPI_CS3    150

static int m528x_cs_setup(struct mcfqspi_cs_control *cs_control)
{
	int status;

	status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
	if (status) {
		pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
		goto fail0;
	}
	status = gpio_direction_output(MCFQSPI_CS0, 1);
	if (status) {
		pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
		goto fail1;
	}

	status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
	if (status) {
		pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
		goto fail1;
	}
	status = gpio_direction_output(MCFQSPI_CS1, 1);
	if (status) {
		pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
		goto fail2;
	}

	status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
	if (status) {
		pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
		goto fail2;
	}
	status = gpio_direction_output(MCFQSPI_CS2, 1);
	if (status) {
		pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
		goto fail3;
	}

	status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
	if (status) {
		pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
		goto fail3;
	}
	status = gpio_direction_output(MCFQSPI_CS3, 1);
	if (status) {
		pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
		goto fail4;
	}

	return 0;

fail4:
	gpio_free(MCFQSPI_CS3);
fail3:
	gpio_free(MCFQSPI_CS2);
fail2:
	gpio_free(MCFQSPI_CS1);
fail1:
	gpio_free(MCFQSPI_CS0);
fail0:
	return status;
}

static void m528x_cs_teardown(struct mcfqspi_cs_control *cs_control)
{
	gpio_free(MCFQSPI_CS3);
	gpio_free(MCFQSPI_CS2);
	gpio_free(MCFQSPI_CS1);
	gpio_free(MCFQSPI_CS0);
}

static void m528x_cs_select(struct mcfqspi_cs_control *cs_control,
			    u8 chip_select, bool cs_high)
{
	gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
}

static void m528x_cs_deselect(struct mcfqspi_cs_control *cs_control,
			      u8 chip_select, bool cs_high)
{
	gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
}

static struct mcfqspi_cs_control m528x_cs_control = {
	.setup                  = m528x_cs_setup,
	.teardown               = m528x_cs_teardown,
	.select                 = m528x_cs_select,
	.deselect               = m528x_cs_deselect,
};

static struct mcfqspi_platform_data m528x_qspi_data = {
	.bus_num		= 0,
	.num_chipselect		= 4,
	.cs_control		= &m528x_cs_control,
};

static struct platform_device m528x_qspi = {
	.name			= "mcfqspi",
	.id			= 0,
	.num_resources		= ARRAY_SIZE(m528x_qspi_resources),
	.resource		= m528x_qspi_resources,
	.dev.platform_data	= &m528x_qspi_data,
};

static void __init m528x_qspi_init(void)
{
	/* setup Port QS for QSPI with gpio CS control */
	__raw_writeb(0x07, MCFGPIO_PQSPAR);
}
#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */

static struct platform_device *m528x_devices[] __initdata = {
	&m528x_uart,
	&m528x_fec,
#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
	&m528x_qspi,
#endif
};

/***************************************************************************/

static void __init m528x_uart_init_line(int line, int irq)
{
	u8 port;

	if ((line < 0) || (line > 2))
		return;

	/* make sure PUAPAR is set for UART0 and UART1 */
	if (line < 2) {
		port = readb(MCF5282_GPIO_PUAPAR);
		port |= (0x03 << (line * 2));
		writeb(port, MCF5282_GPIO_PUAPAR);
	}
}

static void __init m528x_uarts_init(void)
{
	const int nrlines = ARRAY_SIZE(m528x_uart_platform);
	int line;

	for (line = 0; (line < nrlines); line++)
		m528x_uart_init_line(line, m528x_uart_platform[line].irq);
}

/***************************************************************************/

static void __init m528x_fec_init(void)
{
	u16 v16;

	/* Set multi-function pins to ethernet mode for fec0 */
	v16 = readw(MCF_IPSBAR + 0x100056);
	writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
	writeb(0xc0, MCF_IPSBAR + 0x100058);
}

/***************************************************************************/

static void m528x_cpu_reset(void)
{
	local_irq_disable();
	__raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
}

/***************************************************************************/

#ifdef CONFIG_WILDFIRE
void wildfire_halt(void)
{
	writeb(0, 0x30000007);
	writeb(0x2, 0x30000007);
}
#endif

#ifdef CONFIG_WILDFIREMOD
void wildfiremod_halt(void)
{
	printk(KERN_INFO "WildFireMod hibernating...\n");

	/* Set portE.5 to Digital IO */
	MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2));

	/* Make portE.5 an output */
	MCF5282_GPIO_DDRE |= (1 << 5);

	/* Now toggle portE.5 from low to high */
	MCF5282_GPIO_PORTE &= ~(1 << 5);
	MCF5282_GPIO_PORTE |= (1 << 5);

	printk(KERN_EMERG "Failed to hibernate. Halting!\n");
}
#endif

void __init config_BSP(char *commandp, int size)
{
#ifdef CONFIG_WILDFIRE
	mach_halt = wildfire_halt;
#endif
#ifdef CONFIG_WILDFIREMOD
	mach_halt = wildfiremod_halt;
#endif
}

/***************************************************************************/

static int __init init_BSP(void)
{
	mach_reset = m528x_cpu_reset;
	m528x_uarts_init();
	m528x_fec_init();
#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
	m528x_qspi_init();
#endif
	platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices));
	return 0;
}

arch_initcall(init_BSP);

/***************************************************************************/
Commit	Line	Data
1da177e4 LT	1	/***************************************************************************/
	2
	3	/*
	4	* linux/arch/m68knommu/platform/528x/config.c
	5	*
25985edc	6	* Sub-architcture dependent initialization code for the Freescale
980f9235	7	* 5280, 5281 and 5282 CPUs.
1da177e4 LT	8	*
	9	* Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
	10	* Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
	11	*/
	12
	13	/***************************************************************************/
	14
1da177e4	15	#include <linux/kernel.h>
1da177e4 LT	16	#include <linux/param.h>
1da177e4 LT	17	#include <linux/init.h>
eb49e907	18	#include <linux/platform_device.h>
eb49e907	19	#include <linux/io.h>
91d60417 SK	20	#include <linux/spi/spi.h>
91d60417 SK	21	#include <linux/gpio.h>
1da177e4 LT	22	#include <asm/machdep.h>
	23	#include <asm/coldfire.h>
	24	#include <asm/mcfsim.h>
eb49e907	25	#include <asm/mcfuart.h>
91d60417	26	#include <asm/mcfqspi.h>
1da177e4 LT	27
	28	/***************************************************************************/
	29
eb49e907 GU	30	static struct mcf_platform_uart m528x_uart_platform[] = {
eb49e907 GU	31	{
a0ba4332	32	.mapbase = MCFUART_BASE1,
eb49e907 GU	33	.irq = MCFINT_VECBASE + MCFINT_UART0,
	34	},
	35	{
a0ba4332	36	.mapbase = MCFUART_BASE2,
eb49e907 GU	37	.irq = MCFINT_VECBASE + MCFINT_UART0 + 1,
	38	},
	39	{
a0ba4332	40	.mapbase = MCFUART_BASE3,
eb49e907 GU	41	.irq = MCFINT_VECBASE + MCFINT_UART0 + 2,
	42	},
	43	{ },
1da177e4 LT	44	};
1da177e4 LT	45
eb49e907 GU	46	static struct platform_device m528x_uart = {
	47	.name = "mcfuart",
	48	.id = 0,
	49	.dev.platform_data = m528x_uart_platform,
	50	};
	51
ffba3f48 GU	52	static struct resource m528x_fec_resources[] = {
ffba3f48 GU	53	{
a0ba4332 GU	54	.start = MCFFEC_BASE,
a0ba4332 GU	55	.end = MCFFEC_BASE + MCFFEC_SIZE - 1,
ffba3f48 GU	56	.flags = IORESOURCE_MEM,
	57	},
	58	{
	59	.start = 64 + 23,
	60	.end = 64 + 23,
	61	.flags = IORESOURCE_IRQ,
	62	},
	63	{
	64	.start = 64 + 27,
	65	.end = 64 + 27,
	66	.flags = IORESOURCE_IRQ,
	67	},
	68	{
	69	.start = 64 + 29,
	70	.end = 64 + 29,
	71	.flags = IORESOURCE_IRQ,
	72	},
	73	};
	74
	75	static struct platform_device m528x_fec = {
	76	.name = "fec",
	77	.id = 0,
	78	.num_resources = ARRAY_SIZE(m528x_fec_resources),
	79	.resource = m528x_fec_resources,
	80	};
	81
91d60417 SK	82	#if defined(CONFIG_SPI_COLDFIRE_QSPI) \|\| defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
	83	static struct resource m528x_qspi_resources[] = {
	84	{
	85	.start = MCFQSPI_IOBASE,
	86	.end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
	87	.flags = IORESOURCE_MEM,
	88	},
	89	{
	90	.start = MCFINT_VECBASE + MCFINT_QSPI,
	91	.end = MCFINT_VECBASE + MCFINT_QSPI,
	92	.flags = IORESOURCE_IRQ,
	93	},
	94	};
	95
	96	#define MCFQSPI_CS0 147
	97	#define MCFQSPI_CS1 148
	98	#define MCFQSPI_CS2 149
	99	#define MCFQSPI_CS3 150
	100
	101	static int m528x_cs_setup(struct mcfqspi_cs_control *cs_control)
	102	{
	103	int status;
	104
	105	status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
	106	if (status) {
	107	pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
	108	goto fail0;
	109	}
	110	status = gpio_direction_output(MCFQSPI_CS0, 1);
	111	if (status) {
	112	pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
	113	goto fail1;
	114	}
	115
	116	status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
	117	if (status) {
	118	pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
	119	goto fail1;
	120	}
	121	status = gpio_direction_output(MCFQSPI_CS1, 1);
	122	if (status) {
	123	pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
	124	goto fail2;
	125	}
	126
	127	status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
	128	if (status) {
	129	pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
	130	goto fail2;
	131	}
	132	status = gpio_direction_output(MCFQSPI_CS2, 1);
	133	if (status) {
	134	pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
	135	goto fail3;
	136	}
	137
	138	status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
	139	if (status) {
	140	pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
	141	goto fail3;
	142	}
	143	status = gpio_direction_output(MCFQSPI_CS3, 1);
	144	if (status) {
	145	pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
146	goto fail4;
147	}
148
149	return 0;
150
151	fail4:
152	gpio_free(MCFQSPI_CS3);
153	fail3:
154	gpio_free(MCFQSPI_CS2);
155	fail2:
156	gpio_free(MCFQSPI_CS1);
157	fail1:
158	gpio_free(MCFQSPI_CS0);
159	fail0:
160	return status;
161	}
162
163	static void m528x_cs_teardown(struct mcfqspi_cs_control *cs_control)
164	{
165	gpio_free(MCFQSPI_CS3);
166	gpio_free(MCFQSPI_CS2);
167	gpio_free(MCFQSPI_CS1);
168	gpio_free(MCFQSPI_CS0);
169	}
170
171	static void m528x_cs_select(struct mcfqspi_cs_control *cs_control,
172	u8 chip_select, bool cs_high)
173	{
174	gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
175	}
176
177	static void m528x_cs_deselect(struct mcfqspi_cs_control *cs_control,
178	u8 chip_select, bool cs_high)
179	{
180	gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
181	}
182
183	static struct mcfqspi_cs_control m528x_cs_control = {
184	.setup = m528x_cs_setup,
185	.teardown = m528x_cs_teardown,
186	.select = m528x_cs_select,
187	.deselect = m528x_cs_deselect,
188	};
189
190	static struct mcfqspi_platform_data m528x_qspi_data = {
191	.bus_num = 0,
192	.num_chipselect = 4,
193	.cs_control = &m528x_cs_control,
194	};
195
196	static struct platform_device m528x_qspi = {
197	.name = "mcfqspi",
198	.id = 0,
199	.num_resources = ARRAY_SIZE(m528x_qspi_resources),
200	.resource = m528x_qspi_resources,
201	.dev.platform_data = &m528x_qspi_data,
202	};
203
204	static void __init m528x_qspi_init(void)
205	{
206	/* setup Port QS for QSPI with gpio CS control */
207	__raw_writeb(0x07, MCFGPIO_PQSPAR);
208	}
209	#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) \|\| defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
ffba3f48	210
eb49e907 GU	211	static struct platform_device *m528x_devices[] __initdata = {
eb49e907 GU	212	&m528x_uart,
ffba3f48	213	&m528x_fec,
91d60417 SK	214	#if defined(CONFIG_SPI_COLDFIRE_QSPI) \|\| defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
	215	&m528x_qspi,
	216	#endif
eb49e907 GU	217	};
	218
	219	/***************************************************************************/
	220
eb49e907 GU	221	static void __init m528x_uart_init_line(int line, int irq)
	222	{
	223	u8 port;
eb49e907 GU	224
	225	if ((line < 0) \|\| (line > 2))
	226	return;
	227
eb49e907 GU	228	/* make sure PUAPAR is set for UART0 and UART1 */
eb49e907 GU	229	if (line < 2) {
a0ba4332	230	port = readb(MCF5282_GPIO_PUAPAR);
eb49e907	231	port \|= (0x03 << (line * 2));
a0ba4332	232	writeb(port, MCF5282_GPIO_PUAPAR);
eb49e907 GU	233	}
	234	}
	235
	236	static void __init m528x_uarts_init(void)
	237	{
	238	const int nrlines = ARRAY_SIZE(m528x_uart_platform);
	239	int line;
	240
	241	for (line = 0; (line < nrlines); line++)
	242	m528x_uart_init_line(line, m528x_uart_platform[line].irq);
	243	}
1da177e4 LT	244
	245	/***************************************************************************/
	246
ffba3f48 GU	247	static void __init m528x_fec_init(void)
ffba3f48 GU	248	{
ffba3f48 GU	249	u16 v16;
ffba3f48 GU	250
ffba3f48 GU	251	/* Set multi-function pins to ethernet mode for fec0 */
	252	v16 = readw(MCF_IPSBAR + 0x100056);
	253	writew(v16 \| 0xf00, MCF_IPSBAR + 0x100056);
	254	writeb(0xc0, MCF_IPSBAR + 0x100058);
	255	}
	256
	257	/***************************************************************************/
	258
dd65b1de GU	259	static void m528x_cpu_reset(void)
	260	{
	261	local_irq_disable();
	262	__raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
	263	}
	264
	265	/***************************************************************************/
	266
188a9a48 SB	267	#ifdef CONFIG_WILDFIRE
	268	void wildfire_halt(void)
	269	{
	270	writeb(0, 0x30000007);
	271	writeb(0x2, 0x30000007);
	272	}
	273	#endif
	274
	275	#ifdef CONFIG_WILDFIREMOD
	276	void wildfiremod_halt(void)
	277	{
	278	printk(KERN_INFO "WildFireMod hibernating...\n");
	279
	280	/* Set portE.5 to Digital IO */
	281	MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2));
	282
	283	/* Make portE.5 an output */
	284	MCF5282_GPIO_DDRE \|= (1 << 5);
	285
	286	/* Now toggle portE.5 from low to high */
	287	MCF5282_GPIO_PORTE &= ~(1 << 5);
	288	MCF5282_GPIO_PORTE \|= (1 << 5);
	289
	290	printk(KERN_EMERG "Failed to hibernate. Halting!\n");
	291	}
	292	#endif
	293
eb49e907	294	void __init config_BSP(char *commandp, int size)
1da177e4	295	{
188a9a48 SB	296	#ifdef CONFIG_WILDFIRE
	297	mach_halt = wildfire_halt;
	298	#endif
	299	#ifdef CONFIG_WILDFIREMOD
	300	mach_halt = wildfiremod_halt;
	301	#endif
1da177e4 LT	302	}
	303
	304	/***************************************************************************/
eb49e907 GU	305
	306	static int __init init_BSP(void)
	307	{
dd65b1de	308	mach_reset = m528x_cpu_reset;
eb49e907	309	m528x_uarts_init();
ffba3f48	310	m528x_fec_init();
91d60417 SK	311	#if defined(CONFIG_SPI_COLDFIRE_QSPI) \|\| defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
	312	m528x_qspi_init();
	313	#endif
eb49e907 GU	314	platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices));
	315	return 0;
	316	}
	317
	318	arch_initcall(init_BSP);
	319
	320	/***************************************************************************/