[linux-block.git] / arch / m68k / mm / memory.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  linux/arch/m68k/mm/memory.c
 *
 *  Copyright (C) 1995  Hamish Macdonald
 */

#include <linux/module.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/pagemap.h>
#include <linux/gfp.h>

#include <asm/setup.h>
#include <asm/segment.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/traps.h>
#include <asm/machdep.h>


/* ++andreas: {get,free}_pointer_table rewritten to use unused fields from
   struct page instead of separately kmalloced struct.  Stolen from
   arch/sparc/mm/srmmu.c ... */

typedef struct list_head ptable_desc;
static LIST_HEAD(ptable_list);

#define PD_PTABLE(page) ((ptable_desc *)&(virt_to_page(page)->lru))
#define PD_PAGE(ptable) (list_entry(ptable, struct page, lru))
#define PD_MARKBITS(dp) (*(unsigned char *)&PD_PAGE(dp)->index)

#define PTABLE_SIZE (PTRS_PER_PMD * sizeof(pmd_t))

void __init init_pointer_table(unsigned long ptable)
{
	ptable_desc *dp;
	unsigned long page = ptable & PAGE_MASK;
	unsigned char mask = 1 << ((ptable - page)/PTABLE_SIZE);

	dp = PD_PTABLE(page);
	if (!(PD_MARKBITS(dp) & mask)) {
		PD_MARKBITS(dp) = 0xff;
		list_add(dp, &ptable_list);
	}

	PD_MARKBITS(dp) &= ~mask;
	pr_debug("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp));

	/* unreserve the page so it's possible to free that page */
	PD_PAGE(dp)->flags &= ~(1 << PG_reserved);
	init_page_count(PD_PAGE(dp));

	return;
}

pmd_t *get_pointer_table (void)
{
	ptable_desc *dp = ptable_list.next;
	unsigned char mask = PD_MARKBITS (dp);
	unsigned char tmp;
	unsigned int off;

	/*
	 * For a pointer table for a user process address space, a
	 * table is taken from a page allocated for the purpose.  Each
	 * page can hold 8 pointer tables.  The page is remapped in
	 * virtual address space to be noncacheable.
	 */
	if (mask == 0) {
		void *page;
		ptable_desc *new;

		if (!(page = (void *)get_zeroed_page(GFP_KERNEL)))
			return NULL;

		flush_tlb_kernel_page(page);
		nocache_page(page);

		new = PD_PTABLE(page);
		PD_MARKBITS(new) = 0xfe;
		list_add_tail(new, dp);

		return (pmd_t *)page;
	}

	for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += PTABLE_SIZE)
		;
	PD_MARKBITS(dp) = mask & ~tmp;
	if (!PD_MARKBITS(dp)) {
		/* move to end of list */
		list_move_tail(dp, &ptable_list);
	}
	return (pmd_t *) (page_address(PD_PAGE(dp)) + off);
}

int free_pointer_table (pmd_t *ptable)
{
	ptable_desc *dp;
	unsigned long page = (unsigned long)ptable & PAGE_MASK;
	unsigned char mask = 1 << (((unsigned long)ptable - page)/PTABLE_SIZE);

	dp = PD_PTABLE(page);
	if (PD_MARKBITS (dp) & mask)
		panic ("table already free!");

	PD_MARKBITS (dp) |= mask;

	if (PD_MARKBITS(dp) == 0xff) {
		/* all tables in page are free, free page */
		list_del(dp);
		cache_page((void *)page);
		free_page (page);
		return 1;
	} else if (ptable_list.next != dp) {
		/*
		 * move this descriptor to the front of the list, since
		 * it has one or more free tables.
		 */
		list_move(dp, &ptable_list);
	}
	return 0;
}

/* invalidate page in both caches */
static inline void clear040(unsigned long paddr)
{
	asm volatile (
		"nop\n\t"
		".chip 68040\n\t"
		"cinvp %%bc,(%0)\n\t"
		".chip 68k"
		: : "a" (paddr));
}

/* invalidate page in i-cache */
static inline void cleari040(unsigned long paddr)
{
	asm volatile (
		"nop\n\t"
		".chip 68040\n\t"
		"cinvp %%ic,(%0)\n\t"
		".chip 68k"
		: : "a" (paddr));
}

/* push page in both caches */
/* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
static inline void push040(unsigned long paddr)
{
	asm volatile (
		"nop\n\t"
		".chip 68040\n\t"
		"cpushp %%bc,(%0)\n\t"
		".chip 68k"
		: : "a" (paddr));
}

/* push and invalidate page in both caches, must disable ints
 * to avoid invalidating valid data */
static inline void pushcl040(unsigned long paddr)
{
	unsigned long flags;

	local_irq_save(flags);
	push040(paddr);
	if (CPU_IS_060)
		clear040(paddr);
	local_irq_restore(flags);
}

/*
 * 040: Hit every page containing an address in the range paddr..paddr+len-1.
 * (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
 * Hit every page until there is a page or less to go. Hit the next page,
 * and the one after that if the range hits it.
 */
/* ++roman: A little bit more care is required here: The CINVP instruction
 * invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
 * and the end of the region must be treated differently if they are not
 * exactly at the beginning or end of a page boundary. Else, maybe too much
 * data becomes invalidated and thus lost forever. CPUSHP does what we need:
 * it invalidates the page after pushing dirty data to memory. (Thanks to Jes
 * for discovering the problem!)
 */
/* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
 * the DPI bit in the CACR; would it cause problems with temporarily changing
 * this?). So we have to push first and then additionally to invalidate.
 */


/*
 * cache_clear() semantics: Clear any cache entries for the area in question,
 * without writing back dirty entries first. This is useful if the data will
 * be overwritten anyway, e.g. by DMA to memory. The range is defined by a
 * _physical_ address.
 */

void cache_clear (unsigned long paddr, int len)
{
    if (CPU_IS_COLDFIRE) {
	clear_cf_bcache(0, DCACHE_MAX_ADDR);
    } else if (CPU_IS_040_OR_060) {
	int tmp;

	/*
	 * We need special treatment for the first page, in case it
	 * is not page-aligned. Page align the addresses to work
	 * around bug I17 in the 68060.
	 */
	if ((tmp = -paddr & (PAGE_SIZE - 1))) {
	    pushcl040(paddr & PAGE_MASK);
	    if ((len -= tmp) <= 0)
		return;
	    paddr += tmp;
	}
	tmp = PAGE_SIZE;
	paddr &= PAGE_MASK;
	while ((len -= tmp) >= 0) {
	    clear040(paddr);
	    paddr += tmp;
	}
	if ((len += tmp))
	    /* a page boundary gets crossed at the end */
	    pushcl040(paddr);
    }
    else /* 68030 or 68020 */
	asm volatile ("movec %/cacr,%/d0\n\t"
		      "oriw %0,%/d0\n\t"
		      "movec %/d0,%/cacr"
		      : : "i" (FLUSH_I_AND_D)
		      : "d0");
#ifdef CONFIG_M68K_L2_CACHE
    if(mach_l2_flush)
	mach_l2_flush(0);
#endif
}
EXPORT_SYMBOL(cache_clear);


/*
 * cache_push() semantics: Write back any dirty cache data in the given area,
 * and invalidate the range in the instruction cache. It needs not (but may)
 * invalidate those entries also in the data cache. The range is defined by a
 * _physical_ address.
 */

void cache_push (unsigned long paddr, int len)
{
    if (CPU_IS_COLDFIRE) {
	flush_cf_bcache(0, DCACHE_MAX_ADDR);
    } else if (CPU_IS_040_OR_060) {
	int tmp = PAGE_SIZE;

	/*
         * on 68040 or 68060, push cache lines for pages in the range;
	 * on the '040 this also invalidates the pushed lines, but not on
	 * the '060!
	 */
	len += paddr & (PAGE_SIZE - 1);

	/*
	 * Work around bug I17 in the 68060 affecting some instruction
	 * lines not being invalidated properly.
	 */
	paddr &= PAGE_MASK;

	do {
	    push040(paddr);
	    paddr += tmp;
	} while ((len -= tmp) > 0);
    }
    /*
     * 68030/68020 have no writeback cache. On the other hand,
     * cache_push is actually a superset of cache_clear (the lines
     * get written back and invalidated), so we should make sure
     * to perform the corresponding actions. After all, this is getting
     * called in places where we've just loaded code, or whatever, so
     * flushing the icache is appropriate; flushing the dcache shouldn't
     * be required.
     */
    else /* 68030 or 68020 */
	asm volatile ("movec %/cacr,%/d0\n\t"
		      "oriw %0,%/d0\n\t"
		      "movec %/d0,%/cacr"
		      : : "i" (FLUSH_I)
		      : "d0");
#ifdef CONFIG_M68K_L2_CACHE
    if(mach_l2_flush)
	mach_l2_flush(1);
#endif
}
EXPORT_SYMBOL(cache_push);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* linux/arch/m68k/mm/memory.c
	4	*
	5	* Copyright (C) 1995 Hamish Macdonald
	6	*/
	7
2e811488	8	#include <linux/module.h>
1da177e4 LT	9	#include <linux/mm.h>
	10	#include <linux/kernel.h>
	11	#include <linux/string.h>
	12	#include <linux/types.h>
1da177e4 LT	13	#include <linux/init.h>
1da177e4 LT	14	#include <linux/pagemap.h>
5a0e3ad6	15	#include <linux/gfp.h>
1da177e4 LT	16
	17	#include <asm/setup.h>
	18	#include <asm/segment.h>
	19	#include <asm/page.h>
	20	#include <asm/pgalloc.h>
1da177e4 LT	21	#include <asm/traps.h>
	22	#include <asm/machdep.h>
	23
	24
	25	/* ++andreas: {get,free}_pointer_table rewritten to use unused fields from
	26	struct page instead of separately kmalloced struct. Stolen from
	27	arch/sparc/mm/srmmu.c ... */
	28
	29	typedef struct list_head ptable_desc;
	30	static LIST_HEAD(ptable_list);
	31
	32	#define PD_PTABLE(page) ((ptable_desc *)&(virt_to_page(page)->lru))
	33	#define PD_PAGE(ptable) (list_entry(ptable, struct page, lru))
	34	#define PD_MARKBITS(dp) ((unsigned char )&PD_PAGE(dp)->index)
	35
	36	#define PTABLE_SIZE (PTRS_PER_PMD * sizeof(pmd_t))
	37
	38	void __init init_pointer_table(unsigned long ptable)
	39	{
	40	ptable_desc *dp;
	41	unsigned long page = ptable & PAGE_MASK;
	42	unsigned char mask = 1 << ((ptable - page)/PTABLE_SIZE);
	43
	44	dp = PD_PTABLE(page);
	45	if (!(PD_MARKBITS(dp) & mask)) {
	46	PD_MARKBITS(dp) = 0xff;
	47	list_add(dp, &ptable_list);
	48	}
	49
	50	PD_MARKBITS(dp) &= ~mask;
e6991137	51	pr_debug("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp));
1da177e4 LT	52
	53	/* unreserve the page so it's possible to free that page */
	54	PD_PAGE(dp)->flags &= ~(1 << PG_reserved);
7835e98b	55	init_page_count(PD_PAGE(dp));
1da177e4 LT	56
	57	return;
	58	}
	59
	60	pmd_t *get_pointer_table (void)
	61	{
	62	ptable_desc *dp = ptable_list.next;
	63	unsigned char mask = PD_MARKBITS (dp);
	64	unsigned char tmp;
	65	unsigned int off;
	66
	67	/*
	68	* For a pointer table for a user process address space, a
	69	* table is taken from a page allocated for the purpose. Each
	70	* page can hold 8 pointer tables. The page is remapped in
	71	* virtual address space to be noncacheable.
	72	*/
	73	if (mask == 0) {
	74	void *page;
	75	ptable_desc *new;
	76
	77	if (!(page = (void *)get_zeroed_page(GFP_KERNEL)))
	78	return NULL;
	79
	80	flush_tlb_kernel_page(page);
	81	nocache_page(page);
	82
	83	new = PD_PTABLE(page);
	84	PD_MARKBITS(new) = 0xfe;
	85	list_add_tail(new, dp);
	86
	87	return (pmd_t *)page;
	88	}
	89
	90	for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += PTABLE_SIZE)
	91	;
	92	PD_MARKBITS(dp) = mask & ~tmp;
	93	if (!PD_MARKBITS(dp)) {
	94	/* move to end of list */
a7addcea	95	list_move_tail(dp, &ptable_list);
1da177e4 LT	96	}
	97	return (pmd_t *) (page_address(PD_PAGE(dp)) + off);
	98	}
	99
	100	int free_pointer_table (pmd_t *ptable)
	101	{
	102	ptable_desc *dp;
	103	unsigned long page = (unsigned long)ptable & PAGE_MASK;
	104	unsigned char mask = 1 << (((unsigned long)ptable - page)/PTABLE_SIZE);
	105
	106	dp = PD_PTABLE(page);
	107	if (PD_MARKBITS (dp) & mask)
	108	panic ("table already free!");
	109
	110	PD_MARKBITS (dp) \|= mask;
	111
	112	if (PD_MARKBITS(dp) == 0xff) {
	113	/* all tables in page are free, free page */
	114	list_del(dp);
	115	cache_page((void *)page);
	116	free_page (page);
	117	return 1;
	118	} else if (ptable_list.next != dp) {
	119	/*
	120	* move this descriptor to the front of the list, since
	121	* it has one or more free tables.
	122	*/
a7addcea	123	list_move(dp, &ptable_list);
1da177e4 LT	124	}
	125	return 0;
	126	}
	127
1da177e4 LT	128	/* invalidate page in both caches */
	129	static inline void clear040(unsigned long paddr)
	130	{
	131	asm volatile (
	132	"nop\n\t"
	133	".chip 68040\n\t"
	134	"cinvp %%bc,(%0)\n\t"
	135	".chip 68k"
	136	: : "a" (paddr));
	137	}
	138
	139	/* invalidate page in i-cache */
	140	static inline void cleari040(unsigned long paddr)
	141	{
	142	asm volatile (
	143	"nop\n\t"
	144	".chip 68040\n\t"
	145	"cinvp %%ic,(%0)\n\t"
	146	".chip 68k"
	147	: : "a" (paddr));
	148	}
	149
	150	/* push page in both caches */
	151	/* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
	152	static inline void push040(unsigned long paddr)
	153	{
	154	asm volatile (
	155	"nop\n\t"
	156	".chip 68040\n\t"
	157	"cpushp %%bc,(%0)\n\t"
	158	".chip 68k"
	159	: : "a" (paddr));
	160	}
	161
	162	/* push and invalidate page in both caches, must disable ints
	163	* to avoid invalidating valid data */
	164	static inline void pushcl040(unsigned long paddr)
	165	{
	166	unsigned long flags;
	167
	168	local_irq_save(flags);
	169	push040(paddr);
	170	if (CPU_IS_060)
	171	clear040(paddr);
	172	local_irq_restore(flags);
	173	}
	174
	175	/*
	176	* 040: Hit every page containing an address in the range paddr..paddr+len-1.
	177	* (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
	178	* Hit every page until there is a page or less to go. Hit the next page,
	179	* and the one after that if the range hits it.
	180	*/
	181	/* ++roman: A little bit more care is required here: The CINVP instruction
	182	* invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
	183	* and the end of the region must be treated differently if they are not
	184	* exactly at the beginning or end of a page boundary. Else, maybe too much
	185	* data becomes invalidated and thus lost forever. CPUSHP does what we need:
	186	* it invalidates the page after pushing dirty data to memory. (Thanks to Jes
	187	* for discovering the problem!)
	188	*/
	189	/* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
	190	* the DPI bit in the CACR; would it cause problems with temporarily changing
	191	* this?). So we have to push first and then additionally to invalidate.
192	*/
193
194
195	/*
196	* cache_clear() semantics: Clear any cache entries for the area in question,
197	* without writing back dirty entries first. This is useful if the data will
198	* be overwritten anyway, e.g. by DMA to memory. The range is defined by a
199	* _physical_ address.
200	*/
201
202	void cache_clear (unsigned long paddr, int len)
203	{
60610192	204	if (CPU_IS_COLDFIRE) {
f3ff6432	205	clear_cf_bcache(0, DCACHE_MAX_ADDR);
60610192	206	} else if (CPU_IS_040_OR_060) {
1da177e4 LT	207	int tmp;
	208
	209	/*
	210	* We need special treatment for the first page, in case it
	211	* is not page-aligned. Page align the addresses to work
	212	* around bug I17 in the 68060.
	213	*/
	214	if ((tmp = -paddr & (PAGE_SIZE - 1))) {
	215	pushcl040(paddr & PAGE_MASK);
	216	if ((len -= tmp) <= 0)
	217	return;
	218	paddr += tmp;
	219	}
	220	tmp = PAGE_SIZE;
	221	paddr &= PAGE_MASK;
	222	while ((len -= tmp) >= 0) {
	223	clear040(paddr);
	224	paddr += tmp;
	225	}
	226	if ((len += tmp))
	227	/* a page boundary gets crossed at the end */
	228	pushcl040(paddr);
	229	}
	230	else /* 68030 or 68020 */
	231	asm volatile ("movec %/cacr,%/d0\n\t"
	232	"oriw %0,%/d0\n\t"
	233	"movec %/d0,%/cacr"
	234	: : "i" (FLUSH_I_AND_D)
	235	: "d0");
	236	#ifdef CONFIG_M68K_L2_CACHE
	237	if(mach_l2_flush)
	238	mach_l2_flush(0);
	239	#endif
	240	}
bf8af91b	241	EXPORT_SYMBOL(cache_clear);
1da177e4 LT	242
	243
	244	/*
	245	* cache_push() semantics: Write back any dirty cache data in the given area,
	246	* and invalidate the range in the instruction cache. It needs not (but may)
	247	* invalidate those entries also in the data cache. The range is defined by a
	248	* _physical_ address.
	249	*/
	250
	251	void cache_push (unsigned long paddr, int len)
	252	{
60610192 GU	253	if (CPU_IS_COLDFIRE) {
	254	flush_cf_bcache(0, DCACHE_MAX_ADDR);
	255	} else if (CPU_IS_040_OR_060) {
1da177e4 LT	256	int tmp = PAGE_SIZE;
	257
	258	/*
	259	* on 68040 or 68060, push cache lines for pages in the range;
	260	* on the '040 this also invalidates the pushed lines, but not on
	261	* the '060!
	262	*/
	263	len += paddr & (PAGE_SIZE - 1);
	264
	265	/*
	266	* Work around bug I17 in the 68060 affecting some instruction
	267	* lines not being invalidated properly.
	268	*/
	269	paddr &= PAGE_MASK;
	270
	271	do {
	272	push040(paddr);
	273	paddr += tmp;
	274	} while ((len -= tmp) > 0);
	275	}
	276	/*
	277	* 68030/68020 have no writeback cache. On the other hand,
	278	* cache_push is actually a superset of cache_clear (the lines
	279	* get written back and invalidated), so we should make sure
	280	* to perform the corresponding actions. After all, this is getting
	281	* called in places where we've just loaded code, or whatever, so
	282	* flushing the icache is appropriate; flushing the dcache shouldn't
	283	* be required.
	284	*/
	285	else /* 68030 or 68020 */
	286	asm volatile ("movec %/cacr,%/d0\n\t"
	287	"oriw %0,%/d0\n\t"
	288	"movec %/d0,%/cacr"
	289	: : "i" (FLUSH_I)
	290	: "d0");
	291	#ifdef CONFIG_M68K_L2_CACHE
	292	if(mach_l2_flush)
	293	mach_l2_flush(1);
	294	#endif
	295	}
bf8af91b	296	EXPORT_SYMBOL(cache_push);
1da177e4	297