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1da177e4 LT |
1 | /* |
2 | * I/O Processor (IOP) management | |
3 | * Written and (C) 1999 by Joshua M. Thompson (funaho@jurai.org) | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions | |
7 | * are met: | |
8 | * 1. Redistributions of source code must retain the above copyright | |
9 | * notice and this list of conditions. | |
10 | * 2. Redistributions in binary form must reproduce the above copyright | |
11 | * notice and this list of conditions in the documentation and/or other | |
12 | * materials provided with the distribution. | |
13 | */ | |
14 | ||
15 | /* | |
16 | * The IOP chips are used in the IIfx and some Quadras (900, 950) to manage | |
17 | * serial and ADB. They are actually a 6502 processor and some glue logic. | |
18 | * | |
19 | * 990429 (jmt) - Initial implementation, just enough to knock the SCC IOP | |
20 | * into compatible mode so nobody has to fiddle with the | |
21 | * Serial Switch control panel anymore. | |
22 | * 990603 (jmt) - Added code to grab the correct ISM IOP interrupt for OSS | |
23 | * and non-OSS machines (at least I hope it's correct on a | |
24 | * non-OSS machine -- someone with a Q900 or Q950 needs to | |
25 | * check this.) | |
26 | * 990605 (jmt) - Rearranged things a bit wrt IOP detection; iop_present is | |
27 | * gone, IOP base addresses are now in an array and the | |
28 | * globally-visible functions take an IOP number instead of an | |
29 | * an actual base address. | |
30 | * 990610 (jmt) - Finished the message passing framework and it seems to work. | |
31 | * Sending _definitely_ works; my adb-bus.c mods can send | |
32 | * messages and receive the MSG_COMPLETED status back from the | |
33 | * IOP. The trick now is figuring out the message formats. | |
34 | * 990611 (jmt) - More cleanups. Fixed problem where unclaimed messages on a | |
35 | * receive channel were never properly acknowledged. Bracketed | |
36 | * the remaining debug printk's with #ifdef's and disabled | |
37 | * debugging. I can now type on the console. | |
38 | * 990612 (jmt) - Copyright notice added. Reworked the way replies are handled. | |
39 | * It turns out that replies are placed back in the send buffer | |
40 | * for that channel; messages on the receive channels are always | |
41 | * unsolicited messages from the IOP (and our replies to them | |
42 | * should go back in the receive channel.) Also added tracking | |
43 | * of device names to the listener functions ala the interrupt | |
44 | * handlers. | |
45 | * 990729 (jmt) - Added passing of pt_regs structure to IOP handlers. This is | |
46 | * used by the new unified ADB driver. | |
47 | * | |
48 | * TODO: | |
49 | * | |
50 | * o Something should be periodically checking iop_alive() to make sure the | |
51 | * IOP hasn't died. | |
52 | * o Some of the IOP manager routines need better error checking and | |
53 | * return codes. Nothing major, just prettying up. | |
54 | */ | |
55 | ||
56 | /* | |
57 | * ----------------------- | |
58 | * IOP Message Passing 101 | |
59 | * ----------------------- | |
60 | * | |
61 | * The host talks to the IOPs using a rather simple message-passing scheme via | |
62 | * a shared memory area in the IOP RAM. Each IOP has seven "channels"; each | |
63 | * channel is conneced to a specific software driver on the IOP. For example | |
64 | * on the SCC IOP there is one channel for each serial port. Each channel has | |
65 | * an incoming and and outgoing message queue with a depth of one. | |
66 | * | |
67 | * A message is 32 bytes plus a state byte for the channel (MSG_IDLE, MSG_NEW, | |
68 | * MSG_RCVD, MSG_COMPLETE). To send a message you copy the message into the | |
69 | * buffer, set the state to MSG_NEW and signal the IOP by setting the IRQ flag | |
70 | * in the IOP control to 1. The IOP will move the state to MSG_RCVD when it | |
71 | * receives the message and then to MSG_COMPLETE when the message processing | |
72 | * has completed. It is the host's responsibility at that point to read the | |
73 | * reply back out of the send channel buffer and reset the channel state back | |
74 | * to MSG_IDLE. | |
75 | * | |
76 | * To receive message from the IOP the same procedure is used except the roles | |
77 | * are reversed. That is, the IOP puts message in the channel with a state of | |
78 | * MSG_NEW, and the host receives the message and move its state to MSG_RCVD | |
79 | * and then to MSG_COMPLETE when processing is completed and the reply (if any) | |
80 | * has been placed back in the receive channel. The IOP will then reset the | |
81 | * channel state to MSG_IDLE. | |
82 | * | |
83 | * Two sets of host interrupts are provided, INT0 and INT1. Both appear on one | |
84 | * interrupt level; they are distinguished by a pair of bits in the IOP status | |
85 | * register. The IOP will raise INT0 when one or more messages in the send | |
86 | * channels have gone to the MSG_COMPLETE state and it will raise INT1 when one | |
87 | * or more messages on the receive channels have gone to the MSG_NEW state. | |
88 | * | |
89 | * Since each channel handles only one message we have to implement a small | |
90 | * interrupt-driven queue on our end. Messages to be sent are placed on the | |
91 | * queue for sending and contain a pointer to an optional callback function. | |
92 | * The handler for a message is called when the message state goes to | |
93 | * MSG_COMPLETE. | |
94 | * | |
95 | * For receiving message we maintain a list of handler functions to call when | |
96 | * a message is received on that IOP/channel combination. The handlers are | |
97 | * called much like an interrupt handler and are passed a copy of the message | |
98 | * from the IOP. The message state will be in MSG_RCVD while the handler runs; | |
99 | * it is the handler's responsibility to call iop_complete_message() when | |
100 | * finished; this function moves the message state to MSG_COMPLETE and signals | |
101 | * the IOP. This two-step process is provided to allow the handler to defer | |
102 | * message processing to a bottom-half handler if the processing will take | |
0c79cf6a | 103 | * a significant amount of time (handlers are called at interrupt time so they |
1da177e4 LT |
104 | * should execute quickly.) |
105 | */ | |
106 | ||
1da177e4 LT |
107 | #include <linux/types.h> |
108 | #include <linux/kernel.h> | |
109 | #include <linux/mm.h> | |
110 | #include <linux/delay.h> | |
111 | #include <linux/init.h> | |
1da177e4 LT |
112 | #include <linux/interrupt.h> |
113 | ||
114 | #include <asm/bootinfo.h> | |
115 | #include <asm/macintosh.h> | |
116 | #include <asm/macints.h> | |
117 | #include <asm/mac_iop.h> | |
118 | #include <asm/mac_oss.h> | |
119 | ||
120 | /*#define DEBUG_IOP*/ | |
121 | ||
0c79cf6a | 122 | /* Set to non-zero if the IOPs are present. Set by iop_init() */ |
1da177e4 LT |
123 | |
124 | int iop_scc_present,iop_ism_present; | |
125 | ||
1da177e4 LT |
126 | /* structure for tracking channel listeners */ |
127 | ||
128 | struct listener { | |
129 | const char *devname; | |
2850bc27 | 130 | void (*handler)(struct iop_msg *); |
1da177e4 LT |
131 | }; |
132 | ||
133 | /* | |
134 | * IOP structures for the two IOPs | |
135 | * | |
136 | * The SCC IOP controls both serial ports (A and B) as its two functions. | |
137 | * The ISM IOP controls the SWIM (floppy drive) and ADB. | |
138 | */ | |
139 | ||
140 | static volatile struct mac_iop *iop_base[NUM_IOPS]; | |
141 | ||
142 | /* | |
143 | * IOP message queues | |
144 | */ | |
145 | ||
146 | static struct iop_msg iop_msg_pool[NUM_IOP_MSGS]; | |
147 | static struct iop_msg *iop_send_queue[NUM_IOPS][NUM_IOP_CHAN]; | |
148 | static struct listener iop_listeners[NUM_IOPS][NUM_IOP_CHAN]; | |
149 | ||
2850bc27 | 150 | irqreturn_t iop_ism_irq(int, void *); |
1da177e4 LT |
151 | |
152 | extern void oss_irq_enable(int); | |
153 | ||
154 | /* | |
155 | * Private access functions | |
156 | */ | |
157 | ||
158 | static __inline__ void iop_loadaddr(volatile struct mac_iop *iop, __u16 addr) | |
159 | { | |
160 | iop->ram_addr_lo = addr; | |
161 | iop->ram_addr_hi = addr >> 8; | |
162 | } | |
163 | ||
164 | static __inline__ __u8 iop_readb(volatile struct mac_iop *iop, __u16 addr) | |
165 | { | |
166 | iop->ram_addr_lo = addr; | |
167 | iop->ram_addr_hi = addr >> 8; | |
168 | return iop->ram_data; | |
169 | } | |
170 | ||
171 | static __inline__ void iop_writeb(volatile struct mac_iop *iop, __u16 addr, __u8 data) | |
172 | { | |
173 | iop->ram_addr_lo = addr; | |
174 | iop->ram_addr_hi = addr >> 8; | |
175 | iop->ram_data = data; | |
176 | } | |
177 | ||
178 | static __inline__ void iop_stop(volatile struct mac_iop *iop) | |
179 | { | |
180 | iop->status_ctrl &= ~IOP_RUN; | |
181 | } | |
182 | ||
183 | static __inline__ void iop_start(volatile struct mac_iop *iop) | |
184 | { | |
185 | iop->status_ctrl = IOP_RUN | IOP_AUTOINC; | |
186 | } | |
187 | ||
188 | static __inline__ void iop_bypass(volatile struct mac_iop *iop) | |
189 | { | |
190 | iop->status_ctrl |= IOP_BYPASS; | |
191 | } | |
192 | ||
193 | static __inline__ void iop_interrupt(volatile struct mac_iop *iop) | |
194 | { | |
195 | iop->status_ctrl |= IOP_IRQ; | |
196 | } | |
197 | ||
198 | static int iop_alive(volatile struct mac_iop *iop) | |
199 | { | |
200 | int retval; | |
201 | ||
202 | retval = (iop_readb(iop, IOP_ADDR_ALIVE) == 0xFF); | |
203 | iop_writeb(iop, IOP_ADDR_ALIVE, 0); | |
204 | return retval; | |
205 | } | |
206 | ||
207 | static struct iop_msg *iop_alloc_msg(void) | |
208 | { | |
209 | int i; | |
210 | unsigned long flags; | |
211 | ||
212 | local_irq_save(flags); | |
213 | ||
214 | for (i = 0 ; i < NUM_IOP_MSGS ; i++) { | |
215 | if (iop_msg_pool[i].status == IOP_MSGSTATUS_UNUSED) { | |
216 | iop_msg_pool[i].status = IOP_MSGSTATUS_WAITING; | |
217 | local_irq_restore(flags); | |
218 | return &iop_msg_pool[i]; | |
219 | } | |
220 | } | |
221 | ||
222 | local_irq_restore(flags); | |
223 | return NULL; | |
224 | } | |
225 | ||
226 | static void iop_free_msg(struct iop_msg *msg) | |
227 | { | |
228 | msg->status = IOP_MSGSTATUS_UNUSED; | |
229 | } | |
230 | ||
231 | /* | |
232 | * This is called by the startup code before anything else. Its purpose | |
233 | * is to find and initialize the IOPs early in the boot sequence, so that | |
234 | * the serial IOP can be placed into bypass mode _before_ we try to | |
235 | * initialize the serial console. | |
236 | */ | |
237 | ||
238 | void __init iop_preinit(void) | |
239 | { | |
240 | if (macintosh_config->scc_type == MAC_SCC_IOP) { | |
241 | if (macintosh_config->ident == MAC_MODEL_IIFX) { | |
242 | iop_base[IOP_NUM_SCC] = (struct mac_iop *) SCC_IOP_BASE_IIFX; | |
243 | } else { | |
244 | iop_base[IOP_NUM_SCC] = (struct mac_iop *) SCC_IOP_BASE_QUADRA; | |
245 | } | |
246 | iop_base[IOP_NUM_SCC]->status_ctrl = 0x87; | |
247 | iop_scc_present = 1; | |
248 | } else { | |
249 | iop_base[IOP_NUM_SCC] = NULL; | |
250 | iop_scc_present = 0; | |
251 | } | |
252 | if (macintosh_config->adb_type == MAC_ADB_IOP) { | |
253 | if (macintosh_config->ident == MAC_MODEL_IIFX) { | |
254 | iop_base[IOP_NUM_ISM] = (struct mac_iop *) ISM_IOP_BASE_IIFX; | |
255 | } else { | |
256 | iop_base[IOP_NUM_ISM] = (struct mac_iop *) ISM_IOP_BASE_QUADRA; | |
257 | } | |
258 | iop_base[IOP_NUM_ISM]->status_ctrl = 0; | |
259 | iop_ism_present = 1; | |
260 | } else { | |
261 | iop_base[IOP_NUM_ISM] = NULL; | |
262 | iop_ism_present = 0; | |
263 | } | |
264 | } | |
265 | ||
266 | /* | |
267 | * Initialize the IOPs, if present. | |
268 | */ | |
269 | ||
270 | void __init iop_init(void) | |
271 | { | |
272 | int i; | |
273 | ||
274 | if (iop_scc_present) { | |
275 | printk("IOP: detected SCC IOP at %p\n", iop_base[IOP_NUM_SCC]); | |
276 | } | |
277 | if (iop_ism_present) { | |
278 | printk("IOP: detected ISM IOP at %p\n", iop_base[IOP_NUM_ISM]); | |
279 | iop_start(iop_base[IOP_NUM_ISM]); | |
280 | iop_alive(iop_base[IOP_NUM_ISM]); /* clears the alive flag */ | |
281 | } | |
282 | ||
283 | /* Make the whole pool available and empty the queues */ | |
284 | ||
285 | for (i = 0 ; i < NUM_IOP_MSGS ; i++) { | |
286 | iop_msg_pool[i].status = IOP_MSGSTATUS_UNUSED; | |
287 | } | |
288 | ||
289 | for (i = 0 ; i < NUM_IOP_CHAN ; i++) { | |
a5d361fc AV |
290 | iop_send_queue[IOP_NUM_SCC][i] = NULL; |
291 | iop_send_queue[IOP_NUM_ISM][i] = NULL; | |
1da177e4 LT |
292 | iop_listeners[IOP_NUM_SCC][i].devname = NULL; |
293 | iop_listeners[IOP_NUM_SCC][i].handler = NULL; | |
294 | iop_listeners[IOP_NUM_ISM][i].devname = NULL; | |
295 | iop_listeners[IOP_NUM_ISM][i].handler = NULL; | |
296 | } | |
1da177e4 LT |
297 | } |
298 | ||
299 | /* | |
300 | * Register the interrupt handler for the IOPs. | |
301 | * TODO: might be wrong for non-OSS machines. Anyone? | |
302 | */ | |
303 | ||
304 | void __init iop_register_interrupts(void) | |
305 | { | |
306 | if (iop_ism_present) { | |
307 | if (oss_present) { | |
92c3dd15 | 308 | if (request_irq(OSS_IRQLEV_IOPISM, iop_ism_irq, |
1da177e4 | 309 | IRQ_FLG_LOCK, "ISM IOP", |
92c3dd15 GU |
310 | (void *) IOP_NUM_ISM)) |
311 | pr_err("Couldn't register ISM IOP interrupt\n"); | |
1da177e4 LT |
312 | oss_irq_enable(IRQ_MAC_ADB); |
313 | } else { | |
92c3dd15 | 314 | if (request_irq(IRQ_VIA2_0, iop_ism_irq, |
1da177e4 | 315 | IRQ_FLG_LOCK|IRQ_FLG_FAST, "ISM IOP", |
92c3dd15 GU |
316 | (void *) IOP_NUM_ISM)) |
317 | pr_err("Couldn't register ISM IOP interrupt\n"); | |
1da177e4 LT |
318 | } |
319 | if (!iop_alive(iop_base[IOP_NUM_ISM])) { | |
320 | printk("IOP: oh my god, they killed the ISM IOP!\n"); | |
321 | } else { | |
322 | printk("IOP: the ISM IOP seems to be alive.\n"); | |
323 | } | |
324 | } | |
325 | } | |
326 | ||
327 | /* | |
328 | * Register or unregister a listener for a specific IOP and channel | |
329 | * | |
330 | * If the handler pointer is NULL the current listener (if any) is | |
331 | * unregistered. Otherwise the new listener is registered provided | |
332 | * there is no existing listener registered. | |
333 | */ | |
334 | ||
335 | int iop_listen(uint iop_num, uint chan, | |
2850bc27 | 336 | void (*handler)(struct iop_msg *), |
1da177e4 LT |
337 | const char *devname) |
338 | { | |
339 | if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return -EINVAL; | |
340 | if (chan >= NUM_IOP_CHAN) return -EINVAL; | |
341 | if (iop_listeners[iop_num][chan].handler && handler) return -EINVAL; | |
342 | iop_listeners[iop_num][chan].devname = devname; | |
343 | iop_listeners[iop_num][chan].handler = handler; | |
344 | return 0; | |
345 | } | |
346 | ||
347 | /* | |
348 | * Complete reception of a message, which just means copying the reply | |
349 | * into the buffer, setting the channel state to MSG_COMPLETE and | |
350 | * notifying the IOP. | |
351 | */ | |
352 | ||
353 | void iop_complete_message(struct iop_msg *msg) | |
354 | { | |
355 | int iop_num = msg->iop_num; | |
356 | int chan = msg->channel; | |
357 | int i,offset; | |
358 | ||
359 | #ifdef DEBUG_IOP | |
360 | printk("iop_complete(%p): iop %d chan %d\n", msg, msg->iop_num, msg->channel); | |
361 | #endif | |
362 | ||
363 | offset = IOP_ADDR_RECV_MSG + (msg->channel * IOP_MSG_LEN); | |
364 | ||
365 | for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) { | |
366 | iop_writeb(iop_base[iop_num], offset, msg->reply[i]); | |
367 | } | |
368 | ||
369 | iop_writeb(iop_base[iop_num], | |
370 | IOP_ADDR_RECV_STATE + chan, IOP_MSG_COMPLETE); | |
371 | iop_interrupt(iop_base[msg->iop_num]); | |
372 | ||
373 | iop_free_msg(msg); | |
374 | } | |
375 | ||
376 | /* | |
377 | * Actually put a message into a send channel buffer | |
378 | */ | |
379 | ||
380 | static void iop_do_send(struct iop_msg *msg) | |
381 | { | |
382 | volatile struct mac_iop *iop = iop_base[msg->iop_num]; | |
383 | int i,offset; | |
384 | ||
385 | offset = IOP_ADDR_SEND_MSG + (msg->channel * IOP_MSG_LEN); | |
386 | ||
387 | for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) { | |
388 | iop_writeb(iop, offset, msg->message[i]); | |
389 | } | |
390 | ||
391 | iop_writeb(iop, IOP_ADDR_SEND_STATE + msg->channel, IOP_MSG_NEW); | |
392 | ||
393 | iop_interrupt(iop); | |
394 | } | |
395 | ||
396 | /* | |
397 | * Handle sending a message on a channel that | |
398 | * has gone into the IOP_MSG_COMPLETE state. | |
399 | */ | |
400 | ||
2850bc27 | 401 | static void iop_handle_send(uint iop_num, uint chan) |
1da177e4 LT |
402 | { |
403 | volatile struct mac_iop *iop = iop_base[iop_num]; | |
404 | struct iop_msg *msg,*msg2; | |
405 | int i,offset; | |
406 | ||
407 | #ifdef DEBUG_IOP | |
408 | printk("iop_handle_send: iop %d channel %d\n", iop_num, chan); | |
409 | #endif | |
410 | ||
411 | iop_writeb(iop, IOP_ADDR_SEND_STATE + chan, IOP_MSG_IDLE); | |
412 | ||
413 | if (!(msg = iop_send_queue[iop_num][chan])) return; | |
414 | ||
415 | msg->status = IOP_MSGSTATUS_COMPLETE; | |
416 | offset = IOP_ADDR_SEND_MSG + (chan * IOP_MSG_LEN); | |
417 | for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) { | |
418 | msg->reply[i] = iop_readb(iop, offset); | |
419 | } | |
2850bc27 | 420 | if (msg->handler) (*msg->handler)(msg); |
1da177e4 LT |
421 | msg2 = msg; |
422 | msg = msg->next; | |
423 | iop_free_msg(msg2); | |
424 | ||
425 | iop_send_queue[iop_num][chan] = msg; | |
426 | if (msg) iop_do_send(msg); | |
427 | } | |
428 | ||
429 | /* | |
430 | * Handle reception of a message on a channel that has | |
431 | * gone into the IOP_MSG_NEW state. | |
432 | */ | |
433 | ||
2850bc27 | 434 | static void iop_handle_recv(uint iop_num, uint chan) |
1da177e4 LT |
435 | { |
436 | volatile struct mac_iop *iop = iop_base[iop_num]; | |
437 | int i,offset; | |
438 | struct iop_msg *msg; | |
439 | ||
440 | #ifdef DEBUG_IOP | |
441 | printk("iop_handle_recv: iop %d channel %d\n", iop_num, chan); | |
442 | #endif | |
443 | ||
444 | msg = iop_alloc_msg(); | |
445 | msg->iop_num = iop_num; | |
446 | msg->channel = chan; | |
447 | msg->status = IOP_MSGSTATUS_UNSOL; | |
448 | msg->handler = iop_listeners[iop_num][chan].handler; | |
449 | ||
450 | offset = IOP_ADDR_RECV_MSG + (chan * IOP_MSG_LEN); | |
451 | ||
452 | for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) { | |
453 | msg->message[i] = iop_readb(iop, offset); | |
454 | } | |
455 | ||
456 | iop_writeb(iop, IOP_ADDR_RECV_STATE + chan, IOP_MSG_RCVD); | |
457 | ||
458 | /* If there is a listener, call it now. Otherwise complete */ | |
459 | /* the message ourselves to avoid possible stalls. */ | |
460 | ||
461 | if (msg->handler) { | |
2850bc27 | 462 | (*msg->handler)(msg); |
1da177e4 LT |
463 | } else { |
464 | #ifdef DEBUG_IOP | |
465 | printk("iop_handle_recv: unclaimed message on iop %d channel %d\n", iop_num, chan); | |
466 | printk("iop_handle_recv:"); | |
467 | for (i = 0 ; i < IOP_MSG_LEN ; i++) { | |
468 | printk(" %02X", (uint) msg->message[i]); | |
469 | } | |
470 | printk("\n"); | |
471 | #endif | |
472 | iop_complete_message(msg); | |
473 | } | |
474 | } | |
475 | ||
476 | /* | |
477 | * Send a message | |
478 | * | |
479 | * The message is placed at the end of the send queue. Afterwards if the | |
480 | * channel is idle we force an immediate send of the next message in the | |
481 | * queue. | |
482 | */ | |
483 | ||
484 | int iop_send_message(uint iop_num, uint chan, void *privdata, | |
485 | uint msg_len, __u8 *msg_data, | |
2850bc27 | 486 | void (*handler)(struct iop_msg *)) |
1da177e4 LT |
487 | { |
488 | struct iop_msg *msg, *q; | |
489 | ||
490 | if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return -EINVAL; | |
491 | if (chan >= NUM_IOP_CHAN) return -EINVAL; | |
492 | if (msg_len > IOP_MSG_LEN) return -EINVAL; | |
493 | ||
494 | msg = iop_alloc_msg(); | |
495 | if (!msg) return -ENOMEM; | |
496 | ||
497 | msg->next = NULL; | |
498 | msg->status = IOP_MSGSTATUS_WAITING; | |
499 | msg->iop_num = iop_num; | |
500 | msg->channel = chan; | |
501 | msg->caller_priv = privdata; | |
502 | memcpy(msg->message, msg_data, msg_len); | |
503 | msg->handler = handler; | |
504 | ||
505 | if (!(q = iop_send_queue[iop_num][chan])) { | |
506 | iop_send_queue[iop_num][chan] = msg; | |
507 | } else { | |
508 | while (q->next) q = q->next; | |
509 | q->next = msg; | |
510 | } | |
511 | ||
512 | if (iop_readb(iop_base[iop_num], | |
513 | IOP_ADDR_SEND_STATE + chan) == IOP_MSG_IDLE) { | |
514 | iop_do_send(msg); | |
515 | } | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
520 | /* | |
521 | * Upload code to the shared RAM of an IOP. | |
522 | */ | |
523 | ||
524 | void iop_upload_code(uint iop_num, __u8 *code_start, | |
525 | uint code_len, __u16 shared_ram_start) | |
526 | { | |
527 | if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return; | |
528 | ||
529 | iop_loadaddr(iop_base[iop_num], shared_ram_start); | |
530 | ||
531 | while (code_len--) { | |
532 | iop_base[iop_num]->ram_data = *code_start++; | |
533 | } | |
534 | } | |
535 | ||
536 | /* | |
537 | * Download code from the shared RAM of an IOP. | |
538 | */ | |
539 | ||
540 | void iop_download_code(uint iop_num, __u8 *code_start, | |
541 | uint code_len, __u16 shared_ram_start) | |
542 | { | |
543 | if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return; | |
544 | ||
545 | iop_loadaddr(iop_base[iop_num], shared_ram_start); | |
546 | ||
547 | while (code_len--) { | |
548 | *code_start++ = iop_base[iop_num]->ram_data; | |
549 | } | |
550 | } | |
551 | ||
552 | /* | |
553 | * Compare the code in the shared RAM of an IOP with a copy in system memory | |
554 | * and return 0 on match or the first nonmatching system memory address on | |
555 | * failure. | |
556 | */ | |
557 | ||
558 | __u8 *iop_compare_code(uint iop_num, __u8 *code_start, | |
559 | uint code_len, __u16 shared_ram_start) | |
560 | { | |
561 | if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return code_start; | |
562 | ||
563 | iop_loadaddr(iop_base[iop_num], shared_ram_start); | |
564 | ||
565 | while (code_len--) { | |
566 | if (*code_start != iop_base[iop_num]->ram_data) { | |
567 | return code_start; | |
568 | } | |
569 | code_start++; | |
570 | } | |
571 | return (__u8 *) 0; | |
572 | } | |
573 | ||
574 | /* | |
575 | * Handle an ISM IOP interrupt | |
576 | */ | |
577 | ||
2850bc27 | 578 | irqreturn_t iop_ism_irq(int irq, void *dev_id) |
1da177e4 LT |
579 | { |
580 | uint iop_num = (uint) dev_id; | |
581 | volatile struct mac_iop *iop = iop_base[iop_num]; | |
582 | int i,state; | |
583 | ||
584 | #ifdef DEBUG_IOP | |
585 | printk("iop_ism_irq: status = %02X\n", (uint) iop->status_ctrl); | |
586 | #endif | |
587 | ||
588 | /* INT0 indicates a state change on an outgoing message channel */ | |
589 | ||
590 | if (iop->status_ctrl & IOP_INT0) { | |
591 | iop->status_ctrl = IOP_INT0 | IOP_RUN | IOP_AUTOINC; | |
592 | #ifdef DEBUG_IOP | |
593 | printk("iop_ism_irq: new status = %02X, send states", | |
594 | (uint) iop->status_ctrl); | |
595 | #endif | |
596 | for (i = 0 ; i < NUM_IOP_CHAN ; i++) { | |
597 | state = iop_readb(iop, IOP_ADDR_SEND_STATE + i); | |
598 | #ifdef DEBUG_IOP | |
599 | printk(" %02X", state); | |
600 | #endif | |
601 | if (state == IOP_MSG_COMPLETE) { | |
2850bc27 | 602 | iop_handle_send(iop_num, i); |
1da177e4 LT |
603 | } |
604 | } | |
605 | #ifdef DEBUG_IOP | |
606 | printk("\n"); | |
607 | #endif | |
608 | } | |
609 | ||
610 | if (iop->status_ctrl & IOP_INT1) { /* INT1 for incoming msgs */ | |
611 | iop->status_ctrl = IOP_INT1 | IOP_RUN | IOP_AUTOINC; | |
612 | #ifdef DEBUG_IOP | |
613 | printk("iop_ism_irq: new status = %02X, recv states", | |
614 | (uint) iop->status_ctrl); | |
615 | #endif | |
616 | for (i = 0 ; i < NUM_IOP_CHAN ; i++) { | |
617 | state = iop_readb(iop, IOP_ADDR_RECV_STATE + i); | |
618 | #ifdef DEBUG_IOP | |
619 | printk(" %02X", state); | |
620 | #endif | |
621 | if (state == IOP_MSG_NEW) { | |
2850bc27 | 622 | iop_handle_recv(iop_num, i); |
1da177e4 LT |
623 | } |
624 | } | |
625 | #ifdef DEBUG_IOP | |
626 | printk("\n"); | |
627 | #endif | |
628 | } | |
629 | return IRQ_HANDLED; | |
630 | } |