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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * linux/arch/m68knommu/kernel/setup.c | |
4 | * | |
2f75d109 GU |
5 | * Copyright (C) 1999-2007 Greg Ungerer (gerg@snapgear.com) |
6 | * Copyright (C) 1998,1999 D. Jeff Dionne <jeff@uClinux.org> | |
1da177e4 LT |
7 | * Copyleft ()) 2000 James D. Schettine {james@telos-systems.com} |
8 | * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com> | |
9 | * Copyright (C) 1995 Hamish Macdonald | |
e6070a17 | 10 | * Copyright (C) 2000 Lineo Inc. (www.lineo.com) |
1da177e4 LT |
11 | * Copyright (C) 2001 Lineo, Inc. <www.lineo.com> |
12 | * | |
13 | * 68VZ328 Fixes/support Evan Stawnyczy <e@lineo.ca> | |
14 | */ | |
15 | ||
16 | /* | |
17 | * This file handles the architecture-dependent parts of system setup | |
18 | */ | |
19 | ||
1da177e4 LT |
20 | #include <linux/kernel.h> |
21 | #include <linux/sched.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/interrupt.h> | |
1da177e4 | 24 | #include <linux/fb.h> |
e6070a17 | 25 | #include <linux/module.h> |
27ac792c | 26 | #include <linux/mm.h> |
1da177e4 | 27 | #include <linux/console.h> |
1da177e4 LT |
28 | #include <linux/errno.h> |
29 | #include <linux/string.h> | |
1008a115 | 30 | #include <linux/memblock.h> |
1da177e4 | 31 | #include <linux/seq_file.h> |
1da177e4 | 32 | #include <linux/init.h> |
588baeac LS |
33 | #include <linux/initrd.h> |
34 | #include <linux/root_dev.h> | |
95177461 | 35 | #include <linux/rtc.h> |
1da177e4 LT |
36 | |
37 | #include <asm/setup.h> | |
aa5ac789 | 38 | #include <asm/bootinfo.h> |
1da177e4 LT |
39 | #include <asm/irq.h> |
40 | #include <asm/machdep.h> | |
1da177e4 | 41 | #include <asm/pgtable.h> |
c06e9bb4 | 42 | #include <asm/sections.h> |
1da177e4 | 43 | |
1da177e4 LT |
44 | unsigned long memory_start; |
45 | unsigned long memory_end; | |
46 | ||
e6070a17 GU |
47 | EXPORT_SYMBOL(memory_start); |
48 | EXPORT_SYMBOL(memory_end); | |
49 | ||
f2a09e19 | 50 | char __initdata command_line[COMMAND_LINE_SIZE]; |
1da177e4 | 51 | |
1da177e4 | 52 | /* machine dependent timer functions */ |
35aefb26 | 53 | void (*mach_sched_init)(irq_handler_t handler) __initdata = NULL; |
95177461 | 54 | int (*mach_hwclk) (int, struct rtc_time*); |
2f75d109 GU |
55 | |
56 | /* machine dependent reboot functions */ | |
57 | void (*mach_reset)(void); | |
58 | void (*mach_halt)(void); | |
59 | void (*mach_power_off)(void); | |
1da177e4 | 60 | |
1a62fe8d | 61 | #ifdef CONFIG_M68000 |
5198f847 | 62 | #if defined(CONFIG_M68328) |
7fc82b65 | 63 | #define CPU_NAME "MC68328" |
5198f847 | 64 | #elif defined(CONFIG_M68EZ328) |
7fc82b65 | 65 | #define CPU_NAME "MC68EZ328" |
5198f847 | 66 | #elif defined(CONFIG_M68VZ328) |
7fc82b65 | 67 | #define CPU_NAME "MC68VZ328" |
5198f847 DP |
68 | #else |
69 | #define CPU_NAME "MC68000" | |
1da177e4 | 70 | #endif |
5198f847 | 71 | #endif /* CONFIG_M68000 */ |
7fc82b65 GU |
72 | #ifndef CPU_NAME |
73 | #define CPU_NAME "UNKNOWN" | |
1da177e4 LT |
74 | #endif |
75 | ||
733f31b7 GU |
76 | /* |
77 | * Different cores have different instruction execution timings. | |
78 | * The old/traditional 68000 cores are basically all the same, at 16. | |
79 | * The ColdFire cores vary a little, their values are defined in their | |
80 | * headers. We default to the standard 68000 value here. | |
81 | */ | |
82 | #ifndef CPU_INSTR_PER_JIFFY | |
83 | #define CPU_INSTR_PER_JIFFY 16 | |
84 | #endif | |
85 | ||
1d2842e0 | 86 | void __init setup_arch(char **cmdline_p) |
1da177e4 | 87 | { |
1da177e4 | 88 | memory_start = PAGE_ALIGN(_ramstart); |
2f75d109 | 89 | memory_end = _ramend; |
1da177e4 LT |
90 | |
91 | init_mm.start_code = (unsigned long) &_stext; | |
92 | init_mm.end_code = (unsigned long) &_etext; | |
93 | init_mm.end_data = (unsigned long) &_edata; | |
e6070a17 | 94 | init_mm.brk = (unsigned long) 0; |
1da177e4 LT |
95 | |
96 | config_BSP(&command_line[0], sizeof(command_line)); | |
97 | ||
bc72450a GU |
98 | #if defined(CONFIG_BOOTPARAM) |
99 | strncpy(&command_line[0], CONFIG_BOOTPARAM_STRING, sizeof(command_line)); | |
100 | command_line[sizeof(command_line) - 1] = 0; | |
588baeac LS |
101 | #endif /* CONFIG_BOOTPARAM */ |
102 | ||
aa5ac789 | 103 | process_uboot_commandline(&command_line[0], sizeof(command_line)); |
bc72450a | 104 | |
3ec53d6f | 105 | pr_info("uClinux with CPU " CPU_NAME "\n"); |
1da177e4 LT |
106 | |
107 | #ifdef CONFIG_UCDIMM | |
3ec53d6f | 108 | pr_info("uCdimm by Lineo, Inc. <www.lineo.com>\n"); |
1da177e4 LT |
109 | #endif |
110 | #ifdef CONFIG_M68VZ328 | |
3ec53d6f | 111 | pr_info("M68VZ328 support by Evan Stawnyczy <e@lineo.ca>\n"); |
1da177e4 LT |
112 | #endif |
113 | #ifdef CONFIG_COLDFIRE | |
3ec53d6f | 114 | pr_info("COLDFIRE port done by Greg Ungerer, gerg@snapgear.com\n"); |
1da177e4 | 115 | #ifdef CONFIG_M5307 |
3ec53d6f | 116 | pr_info("Modified for M5307 by Dave Miller, dmiller@intellistor.com\n"); |
1da177e4 LT |
117 | #endif |
118 | #ifdef CONFIG_ELITE | |
3ec53d6f | 119 | pr_info("Modified for M5206eLITE by Rob Scott, rscott@mtrob.fdns.net\n"); |
e6070a17 | 120 | #endif |
1da177e4 | 121 | #endif |
3ec53d6f | 122 | pr_info("Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne\n"); |
1da177e4 LT |
123 | |
124 | #if defined( CONFIG_PILOT ) && defined( CONFIG_M68328 ) | |
3ec53d6f | 125 | pr_info("TRG SuperPilot FLASH card support <info@trgnet.com>\n"); |
1da177e4 | 126 | #endif |
1da177e4 | 127 | #if defined( CONFIG_PILOT ) && defined( CONFIG_M68EZ328 ) |
3ec53d6f | 128 | pr_info("PalmV support by Lineo Inc. <jeff@uclinux.com>\n"); |
1da177e4 | 129 | #endif |
1da177e4 | 130 | #ifdef CONFIG_DRAGEN2 |
3ec53d6f | 131 | pr_info("DragonEngine II board support by Georges Menie\n"); |
1da177e4 | 132 | #endif |
e6070a17 | 133 | #ifdef CONFIG_M5235EVB |
3ec53d6f | 134 | pr_info("Motorola M5235EVB support (C)2005 Syn-tech Systems, Inc. (Jate Sujjavanich)\n"); |
e6070a17 | 135 | #endif |
1da177e4 | 136 | |
54503b1d | 137 | pr_debug("KERNEL -> TEXT=0x%p-0x%p DATA=0x%p-0x%p BSS=0x%p-0x%p\n", |
dc061051 | 138 | _stext, _etext, _sdata, _edata, __bss_start, __bss_stop); |
54503b1d | 139 | pr_debug("MEMORY -> ROMFS=0x%p-0x%06lx MEM=0x%06lx-0x%06lx\n ", |
dc061051 | 140 | __bss_stop, memory_start, memory_start, memory_end); |
1da177e4 | 141 | |
1008a115 MR |
142 | memblock_add(memory_start, memory_end - memory_start); |
143 | ||
1da177e4 LT |
144 | /* Keep a copy of command line */ |
145 | *cmdline_p = &command_line[0]; | |
f2a09e19 ABL |
146 | memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); |
147 | boot_command_line[COMMAND_LINE_SIZE-1] = 0; | |
1da177e4 | 148 | |
1da177e4 LT |
149 | #if defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_DUMMY_CONSOLE) |
150 | conswitchp = &dummy_con; | |
151 | #endif | |
152 | ||
153 | /* | |
154 | * Give all the memory to the bootmap allocator, tell it to put the | |
155 | * boot mem_map at the start of memory. | |
156 | */ | |
b66f55cd GU |
157 | min_low_pfn = PFN_DOWN(memory_start); |
158 | max_pfn = max_low_pfn = PFN_DOWN(memory_end); | |
159 | ||
588baeac LS |
160 | #if defined(CONFIG_UBOOT) && defined(CONFIG_BLK_DEV_INITRD) |
161 | if ((initrd_start > 0) && (initrd_start < initrd_end) && | |
162 | (initrd_end < memory_end)) | |
1008a115 | 163 | memblock_reserve(initrd_start, initrd_end - initrd_start); |
588baeac LS |
164 | #endif /* if defined(CONFIG_BLK_DEV_INITRD) */ |
165 | ||
1da177e4 LT |
166 | /* |
167 | * Get kmalloc into gear. | |
168 | */ | |
169 | paging_init(); | |
170 | } | |
171 | ||
1da177e4 LT |
172 | /* |
173 | * Get CPU information for use by the procfs. | |
174 | */ | |
1da177e4 LT |
175 | static int show_cpuinfo(struct seq_file *m, void *v) |
176 | { | |
22982a56 GU |
177 | char *cpu, *mmu, *fpu; |
178 | u_long clockfreq; | |
1da177e4 | 179 | |
7fc82b65 | 180 | cpu = CPU_NAME; |
22982a56 GU |
181 | mmu = "none"; |
182 | fpu = "none"; | |
733f31b7 | 183 | clockfreq = (loops_per_jiffy * HZ) * CPU_INSTR_PER_JIFFY; |
22982a56 GU |
184 | |
185 | seq_printf(m, "CPU:\t\t%s\n" | |
186 | "MMU:\t\t%s\n" | |
187 | "FPU:\t\t%s\n" | |
188 | "Clocking:\t%lu.%1luMHz\n" | |
189 | "BogoMips:\t%lu.%02lu\n" | |
190 | "Calibration:\t%lu loops\n", | |
191 | cpu, mmu, fpu, | |
192 | clockfreq / 1000000, | |
193 | (clockfreq / 100000) % 10, | |
194 | (loops_per_jiffy * HZ) / 500000, | |
195 | ((loops_per_jiffy * HZ) / 5000) % 100, | |
196 | (loops_per_jiffy * HZ)); | |
1da177e4 LT |
197 | |
198 | return 0; | |
199 | } | |
200 | ||
201 | static void *c_start(struct seq_file *m, loff_t *pos) | |
202 | { | |
203 | return *pos < NR_CPUS ? ((void *) 0x12345678) : NULL; | |
204 | } | |
205 | ||
206 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
207 | { | |
208 | ++*pos; | |
209 | return c_start(m, pos); | |
210 | } | |
211 | ||
212 | static void c_stop(struct seq_file *m, void *v) | |
213 | { | |
214 | } | |
215 | ||
03a44825 | 216 | const struct seq_operations cpuinfo_op = { |
1da177e4 LT |
217 | .start = c_start, |
218 | .next = c_next, | |
219 | .stop = c_stop, | |
220 | .show = show_cpuinfo, | |
221 | }; | |
222 |