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ea49f8ff | 1 | /* |
5b2e6555 | 2 | * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support. |
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3 | */ |
4 | ||
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5 | #ifndef m54xxsim_h |
6 | #define m54xxsim_h | |
ea49f8ff | 7 | |
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8 | #define CPU_NAME "COLDFIRE(m54xx)" |
9 | #define CPU_INSTR_PER_JIFFY 2 | |
ce3de78a | 10 | #define MCF_BUSCLK (MCF_CLK / 2) |
7fc82b65 | 11 | |
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12 | #include <asm/m54xxacr.h> |
13 | ||
733f31b7 | 14 | #define MCFINT_VECBASE 64 |
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15 | |
16 | /* | |
17 | * Interrupt Controller Registers | |
18 | */ | |
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19 | #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */ |
20 | ||
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21 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
22 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | |
23 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | |
24 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | |
25 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | |
26 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | |
27 | #define MCFINTC_IRLR 0x18 /* */ | |
28 | #define MCFINTC_IACKL 0x19 /* */ | |
29 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | |
30 | ||
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31 | /* |
32 | * UART module. | |
33 | */ | |
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34 | #define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */ |
35 | #define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */ | |
36 | #define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */ | |
37 | #define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */ | |
57015421 | 38 | |
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39 | /* |
40 | * Define system peripheral IRQ usage. | |
41 | */ | |
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42 | #define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */ |
43 | #define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */ | |
44 | #define MCF_IRQ_UART0 (MCFINT_VECBASE + 35) | |
45 | #define MCF_IRQ_UART1 (MCFINT_VECBASE + 34) | |
46 | #define MCF_IRQ_UART2 (MCFINT_VECBASE + 33) | |
47 | #define MCF_IRQ_UART3 (MCFINT_VECBASE + 32) | |
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48 | |
49 | /* | |
50 | * Generic GPIO support | |
51 | */ | |
52 | #define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */ | |
53 | #define MCFGPIO_IRQ_MAX -1 | |
54 | #define MCFGPIO_IRQ_VECBASE -1 | |
55 | ||
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56 | /* |
57 | * EDGE Port support. | |
58 | */ | |
59 | #define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */ | |
60 | #define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */ | |
61 | #define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */ | |
62 | #define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */ | |
63 | #define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */ | |
64 | #define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ | |
65 | ||
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66 | /* |
67 | * Some PSC related definitions | |
68 | */ | |
69 | #define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) | |
70 | #define MCF_PAR_SDA (0x0008) | |
71 | #define MCF_PAR_SCL (0x0004) | |
72 | #define MCF_PAR_PSC_TXD (0x04) | |
73 | #define MCF_PAR_PSC_RXD (0x08) | |
74 | #define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) | |
75 | #define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) | |
76 | #define MCF_PAR_PSC_CTS_GPIO (0x00) | |
77 | #define MCF_PAR_PSC_CTS_BCLK (0x80) | |
78 | #define MCF_PAR_PSC_CTS_CTS (0xC0) | |
79 | #define MCF_PAR_PSC_RTS_GPIO (0x00) | |
80 | #define MCF_PAR_PSC_RTS_FSYNC (0x20) | |
81 | #define MCF_PAR_PSC_RTS_RTS (0x30) | |
82 | #define MCF_PAR_PSC_CANRX (0x40) | |
83 | ||
5b2e6555 | 84 | #endif /* m54xxsim_h */ |