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910ce396 GU |
1 | /****************************************************************************/ |
2 | ||
3 | /* | |
4 | * m523xsim.h -- ColdFire 523x System Integration Module support. | |
5 | * | |
6 | * (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com> | |
7 | */ | |
8 | ||
9 | /****************************************************************************/ | |
10 | #ifndef m523xsim_h | |
11 | #define m523xsim_h | |
12 | /****************************************************************************/ | |
13 | ||
733f31b7 GU |
14 | #define CPU_NAME "COLDFIRE(m523x)" |
15 | #define CPU_INSTR_PER_JIFFY 3 | |
ce3de78a | 16 | #define MCF_BUSCLK (MCF_CLK / 2) |
910ce396 | 17 | |
a12cf0a8 GU |
18 | #include <asm/m52xxacr.h> |
19 | ||
910ce396 GU |
20 | /* |
21 | * Define the 523x SIM register set addresses. | |
22 | */ | |
254eef74 GU |
23 | #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ |
24 | #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ | |
25 | ||
910ce396 GU |
26 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
27 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | |
28 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | |
29 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | |
30 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | |
31 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | |
32 | #define MCFINTC_IRLR 0x18 /* */ | |
33 | #define MCFINTC_IACKL 0x19 /* */ | |
34 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | |
35 | ||
36 | #define MCFINT_VECBASE 64 /* Vector base number */ | |
37 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ | |
38 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ | |
39 | #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ | |
40 | ||
41 | /* | |
42 | * SDRAM configuration registers. | |
43 | */ | |
6a92e198 GU |
44 | #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ |
45 | #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ | |
46 | #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ | |
47 | #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ | |
48 | #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ | |
910ce396 | 49 | |
55b33f31 | 50 | /* |
25985edc | 51 | * Reset Control Unit (relative to IPSBAR). |
55b33f31 GU |
52 | */ |
53 | #define MCF_RCR 0x110000 | |
54 | #define MCF_RSR 0x110001 | |
55 | ||
56 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ | |
57 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ | |
58 | ||
57015421 GU |
59 | /* |
60 | * UART module. | |
61 | */ | |
b62384af GU |
62 | #define MCFUART_BASE1 (MCF_IPSBAR + 0x200) |
63 | #define MCFUART_BASE2 (MCF_IPSBAR + 0x240) | |
64 | #define MCFUART_BASE3 (MCF_IPSBAR + 0x280) | |
57015421 | 65 | |
b62384af GU |
66 | /* |
67 | * FEC ethernet module. | |
68 | */ | |
69 | #define MCFFEC_BASE (MCF_IPSBAR + 0x1000) | |
70 | #define MCFFEC_SIZE 0x800 | |
71 | ||
72 | /* | |
73 | * GPIO module. | |
74 | */ | |
a03ce7d9 | 75 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) |
76 | #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) | |
77 | #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) | |
78 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) | |
79 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) | |
80 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) | |
81 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) | |
82 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) | |
83 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) | |
84 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) | |
85 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) | |
86 | #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) | |
87 | #define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C) | |
88 | ||
89 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) | |
90 | #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) | |
91 | #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) | |
92 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) | |
93 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) | |
94 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) | |
95 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) | |
96 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) | |
97 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) | |
98 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) | |
99 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) | |
100 | #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) | |
101 | #define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C) | |
102 | ||
103 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) | |
104 | #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) | |
105 | #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) | |
106 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) | |
107 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) | |
108 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) | |
109 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) | |
110 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) | |
111 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) | |
112 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) | |
113 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) | |
114 | #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) | |
115 | #define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C) | |
116 | ||
117 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) | |
118 | #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) | |
119 | #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) | |
120 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) | |
121 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) | |
122 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) | |
123 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) | |
124 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) | |
125 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) | |
126 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) | |
127 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) | |
128 | #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) | |
129 | #define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) | |
130 | ||
131 | /* | |
f317c71a | 132 | * PIT timer base addresses. |
a03ce7d9 | 133 | */ |
f317c71a GU |
134 | #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) |
135 | #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) | |
136 | #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) | |
137 | #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) | |
a03ce7d9 | 138 | |
f317c71a GU |
139 | /* |
140 | * EPort | |
141 | */ | |
57b48143 | 142 | #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) |
a03ce7d9 | 143 | #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) |
57b48143 | 144 | #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) |
a03ce7d9 | 145 | #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) |
146 | #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) | |
57b48143 | 147 | #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) |
a03ce7d9 | 148 | |
149 | /* | |
150 | * Generic GPIO support | |
151 | */ | |
152 | #define MCFGPIO_PODR MCFGPIO_PODR_ADDR | |
153 | #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR | |
154 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR | |
155 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR | |
156 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR | |
157 | ||
158 | #define MCFGPIO_PIN_MAX 107 | |
159 | #define MCFGPIO_IRQ_MAX 8 | |
160 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | |
161 | ||
91d60417 SK |
162 | /* |
163 | * Pin Assignment | |
164 | */ | |
165 | #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) | |
166 | #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) | |
babc08b7 GU |
167 | |
168 | /* | |
169 | * DMA unit base addresses. | |
170 | */ | |
171 | #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) | |
172 | #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) | |
173 | #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) | |
174 | #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) | |
175 | ||
910ce396 GU |
176 | /****************************************************************************/ |
177 | #endif /* m523xsim_h */ |