Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /***************************************************************************/ |
3 | ||
4 | /* | |
ece9ae65 | 5 | * m5307.c -- platform support for ColdFire 5307 based boards |
1da177e4 LT |
6 | * |
7 | * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) | |
8 | * Copyright (C) 2000, Lineo (www.lineo.com) | |
9 | */ | |
10 | ||
11 | /***************************************************************************/ | |
12 | ||
63aadb77 | 13 | #include <linux/clkdev.h> |
1da177e4 | 14 | #include <linux/kernel.h> |
1da177e4 LT |
15 | #include <linux/param.h> |
16 | #include <linux/init.h> | |
96db271a | 17 | #include <linux/io.h> |
1da177e4 LT |
18 | #include <asm/machdep.h> |
19 | #include <asm/coldfire.h> | |
1da177e4 | 20 | #include <asm/mcfsim.h> |
1da177e4 | 21 | #include <asm/mcfwdebug.h> |
91ca1bbd | 22 | #include <asm/mcfclk.h> |
1da177e4 LT |
23 | |
24 | /***************************************************************************/ | |
25 | ||
1da177e4 LT |
26 | /* |
27 | * Some platforms need software versions of the GPIO data registers. | |
28 | */ | |
29 | unsigned short ppdata; | |
30 | unsigned char ledbank = 0xff; | |
31 | ||
32 | /***************************************************************************/ | |
33 | ||
91ca1bbd GU |
34 | DEFINE_CLK(pll, "pll.0", MCF_CLK); |
35 | DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); | |
63aadb77 AB |
36 | |
37 | static struct clk_lookup m5307_clk_lookup[] = { | |
38 | CLKDEV_INIT(NULL, "pll.0", &clk_pll), | |
39 | CLKDEV_INIT(NULL, "sys.0", &clk_sys), | |
40 | CLKDEV_INIT("mcftmr.0", NULL, &clk_sys), | |
41 | CLKDEV_INIT("mcftmr.1", NULL, &clk_sys), | |
42 | CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), | |
43 | CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), | |
44 | CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys), | |
91ca1bbd GU |
45 | }; |
46 | ||
47 | /***************************************************************************/ | |
48 | ||
2d24b532 SK |
49 | static void __init m5307_i2c_init(void) |
50 | { | |
51 | #if IS_ENABLED(CONFIG_I2C_IMX) | |
52 | writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, | |
53 | MCFSIM_I2CICR); | |
54 | mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C); | |
55 | #endif /* IS_ENABLED(CONFIG_I2C_IMX) */ | |
56 | } | |
57 | ||
58 | /***************************************************************************/ | |
59 | ||
96db271a | 60 | void __init config_BSP(char *commandp, int size) |
1da177e4 | 61 | { |
3947fca7 | 62 | #if defined(CONFIG_NETtel) || \ |
cff28b56 | 63 | defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA) |
1da177e4 LT |
64 | /* Copy command line from FLASH to local buffer... */ |
65 | memcpy(commandp, (char *) 0xf0004000, size); | |
66 | commandp[size-1] = 0; | |
1da177e4 LT |
67 | #endif |
68 | ||
35aefb26 | 69 | mach_sched_init = hw_timer_init; |
39f0fb6a GU |
70 | |
71 | /* Only support the external interrupts on their primary level */ | |
72 | mcf_mapirq2imr(25, MCFINTC_EINT1); | |
73 | mcf_mapirq2imr(27, MCFINTC_EINT3); | |
74 | mcf_mapirq2imr(29, MCFINTC_EINT5); | |
75 | mcf_mapirq2imr(31, MCFINTC_EINT7); | |
1da177e4 | 76 | |
96db271a | 77 | #ifdef CONFIG_BDM_DISABLE |
1da177e4 LT |
78 | /* |
79 | * Disable the BDM clocking. This also turns off most of the rest of | |
80 | * the BDM device. This is good for EMC reasons. This option is not | |
81 | * incompatible with the memory protection option. | |
82 | */ | |
83 | wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK); | |
84 | #endif | |
2d24b532 | 85 | m5307_i2c_init(); |
63aadb77 AB |
86 | |
87 | clkdev_add_table(m5307_clk_lookup, ARRAY_SIZE(m5307_clk_lookup)); | |
1da177e4 LT |
88 | } |
89 | ||
90 | /***************************************************************************/ |