Commit | Line | Data |
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1da177e4 LT |
1 | /***************************************************************************/ |
2 | ||
3 | /* | |
ece9ae65 | 4 | * m528x.c -- platform support for ColdFire 528x based boards |
1da177e4 | 5 | * |
25985edc | 6 | * Sub-architcture dependent initialization code for the Freescale |
980f9235 | 7 | * 5280, 5281 and 5282 CPUs. |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com) | |
10 | * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) | |
11 | */ | |
12 | ||
13 | /***************************************************************************/ | |
14 | ||
1da177e4 | 15 | #include <linux/kernel.h> |
1da177e4 LT |
16 | #include <linux/param.h> |
17 | #include <linux/init.h> | |
eb49e907 | 18 | #include <linux/platform_device.h> |
eb49e907 | 19 | #include <linux/io.h> |
1da177e4 LT |
20 | #include <asm/machdep.h> |
21 | #include <asm/coldfire.h> | |
22 | #include <asm/mcfsim.h> | |
eb49e907 | 23 | #include <asm/mcfuart.h> |
87f37769 GU |
24 | #include <asm/mcfclk.h> |
25 | ||
26 | /***************************************************************************/ | |
27 | ||
28 | DEFINE_CLK(pll, "pll.0", MCF_CLK); | |
29 | DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); | |
30 | DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); | |
31 | DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); | |
32 | DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); | |
33 | DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); | |
34 | DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); | |
35 | DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); | |
36 | DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); | |
74859523 | 37 | DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); |
87f37769 GU |
38 | DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); |
39 | ||
40 | struct clk *mcf_clks[] = { | |
41 | &clk_pll, | |
42 | &clk_sys, | |
43 | &clk_mcfpit0, | |
44 | &clk_mcfpit1, | |
45 | &clk_mcfpit2, | |
46 | &clk_mcfpit3, | |
47 | &clk_mcfuart0, | |
48 | &clk_mcfuart1, | |
49 | &clk_mcfuart2, | |
74859523 | 50 | &clk_mcfqspi0, |
87f37769 GU |
51 | &clk_fec0, |
52 | NULL | |
53 | }; | |
1da177e4 LT |
54 | |
55 | /***************************************************************************/ | |
56 | ||
91d60417 SK |
57 | static void __init m528x_qspi_init(void) |
58 | { | |
151d14f4 | 59 | #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) |
91d60417 SK |
60 | /* setup Port QS for QSPI with gpio CS control */ |
61 | __raw_writeb(0x07, MCFGPIO_PQSPAR); | |
83ca6009 | 62 | #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ |
151d14f4 | 63 | } |
eb49e907 GU |
64 | |
65 | /***************************************************************************/ | |
66 | ||
cae82a83 | 67 | static void __init m528x_uarts_init(void) |
eb49e907 GU |
68 | { |
69 | u8 port; | |
eb49e907 | 70 | |
eb49e907 | 71 | /* make sure PUAPAR is set for UART0 and UART1 */ |
0371a1c5 | 72 | port = readb(MCFGPIO_PUAPAR); |
cae82a83 | 73 | port |= 0x03 | (0x03 << 2); |
eac57949 | 74 | writeb(port, MCFGPIO_PUAPAR); |
eb49e907 | 75 | } |
1da177e4 LT |
76 | |
77 | /***************************************************************************/ | |
78 | ||
ffba3f48 GU |
79 | static void __init m528x_fec_init(void) |
80 | { | |
ffba3f48 GU |
81 | u16 v16; |
82 | ||
ffba3f48 | 83 | /* Set multi-function pins to ethernet mode for fec0 */ |
a91f7415 GU |
84 | v16 = readw(MCFGPIO_PASPAR); |
85 | writew(v16 | 0xf00, MCFGPIO_PASPAR); | |
86 | writeb(0xc0, MCFGPIO_PEHLPAR); | |
ffba3f48 GU |
87 | } |
88 | ||
89 | /***************************************************************************/ | |
90 | ||
188a9a48 SB |
91 | #ifdef CONFIG_WILDFIRE |
92 | void wildfire_halt(void) | |
93 | { | |
94 | writeb(0, 0x30000007); | |
95 | writeb(0x2, 0x30000007); | |
96 | } | |
97 | #endif | |
98 | ||
99 | #ifdef CONFIG_WILDFIREMOD | |
100 | void wildfiremod_halt(void) | |
101 | { | |
102 | printk(KERN_INFO "WildFireMod hibernating...\n"); | |
103 | ||
104 | /* Set portE.5 to Digital IO */ | |
105 | MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2)); | |
106 | ||
107 | /* Make portE.5 an output */ | |
108 | MCF5282_GPIO_DDRE |= (1 << 5); | |
109 | ||
110 | /* Now toggle portE.5 from low to high */ | |
111 | MCF5282_GPIO_PORTE &= ~(1 << 5); | |
112 | MCF5282_GPIO_PORTE |= (1 << 5); | |
113 | ||
114 | printk(KERN_EMERG "Failed to hibernate. Halting!\n"); | |
115 | } | |
116 | #endif | |
117 | ||
eb49e907 | 118 | void __init config_BSP(char *commandp, int size) |
1da177e4 | 119 | { |
188a9a48 SB |
120 | #ifdef CONFIG_WILDFIRE |
121 | mach_halt = wildfire_halt; | |
122 | #endif | |
123 | #ifdef CONFIG_WILDFIREMOD | |
124 | mach_halt = wildfiremod_halt; | |
125 | #endif | |
35aefb26 | 126 | mach_sched_init = hw_timer_init; |
eb49e907 | 127 | m528x_uarts_init(); |
ffba3f48 | 128 | m528x_fec_init(); |
91d60417 | 129 | m528x_qspi_init(); |
eb49e907 GU |
130 | } |
131 | ||
eb49e907 | 132 | /***************************************************************************/ |